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/arch/sparc/crypto/
Daes_asm.S231 ld [%o0 + 0x10], %f4
236 std %f4, [%o1 + 0x00]
297 ld [%o0 + 0x10], %f4
300 std %f4, [%o1 + 0x00]
375 std %f4, [%o1 + 0x00]
404 ld [%o1 + 0x00], %f4
430 fxor %f8, %f4, %f4
433 st %f4, [%o2 + 0x00]
445 ld [%o1 + 0x00], %f4
453 fxor %f8, %f4, %f4
[all …]
Ddes_asm.S30 std %f4, [%o1 + 0x10]
55 ldd [%o0 + 0x10], %f4
90 ldd [%o0 + 0x10], %f4
188 ldd [%o0 + 0x10], %f4
207 ldd [%o0 + 0x90], %f4
233 ldd [%o0 + 0x110], %f4
276 ldd [%o0 + 0x10], %f4
331 ldd [%o0 + 0x140], %f4; \
360 ldd [%o0 + 0x10], %f4; \
Dcamellia_asm.S137 ldd [%o1 + 0x20], %f4 ! k[ 8, 9]
139 fxor %f0, %f4, %f0
213 ldd [%o1 + 0x28], %f4
219 std %f4, [%o3 + 0x10]
249 ldd [%o0 + 0x00], %f4
253 fxor %f4, %f0, %f0
314 ldd [%o0 + 0x00], %f4
349 fxor %f4, %f0, %f0
371 fxor %f4, %f0, %f0
419 fxor %f4, %f0, %f0
[all …]
Dsha1_asm.S15 ld [%o0 + 0x10], %f4
38 st %f4, [%o0 + 0x10]
Dsha256_asm.S13 ld [%o0 + 0x10], %f4
41 st %f4, [%o0 + 0x10]
Dsha512_asm.S11 ldd [%o0 + 0x10], %f4
47 std %f4, [%o0 + 0x10]
/arch/sparc/lib/
DU1memcpy.S68 #define FREG_FROB(f1, f2, f3, f4, f5, f6, f7, f8, f9) \ argument
71 faligndata %f3, %f4, %f52; \
72 faligndata %f4, %f5, %f54; \
294 EX_LD_FP(LOAD(ldd, %o1, %f4), U1_g2_0_fp)
298 faligndata %f4, %f6, %f0
303 EX_LD_FP(LOAD(ldd, %o1 + 0x8, %f4), U1_g2_0_fp)
306 faligndata %f6, %f4, %f0
355 1: FREG_FROB(f0, f2, f4, f6, f8, f10,f12,f14,f16)
369 FREG_FROB(f0, f2, f4, f6, f8, f10,f12,f14,f16)
371 3: FREG_FROB(f0, f2, f4, f6, f8, f10,f12,f14,f16)
[all …]
Dcopy_page.S105 ldd [%o1 + 0x010], %f4
111 fsrc2 %f4, %f20
121 ldd [%o1 + 0x050], %f4
129 fsrc2 %f4, %f20
144 ldd [%o1 + 0x050], %f4
152 fsrc2 %f4, %f20
181 1: TOUCH(f0, f2, f4, f6, f8, f10, f12, f14)
202 TOUCH(f0, f2, f4, f6, f8, f10, f12, f14)
DNG2memcpy.S88 faligndata %x2, %x3, %f4; \
103 fsrc2 %x2, %f4;
107 fsrc2 %x2, %f4; \
112 fsrc2 %x2, %f4; \
118 fsrc2 %x2, %f4; \
125 fsrc2 %x2, %f4; \
133 fsrc2 %x2, %f4; \
349 FREG_FROB(f0, f2, f4, f6, f8, f10, f12, f14, f16)
360 FREG_LOAD_7(%g2, f0, f2, f4, f6, f8, f10, f12)
363 FREG_FROB(f0, f2, f4, f6, f8, f10, f12, f16, f18)
[all …]
DU3memcpy.S219 EX_LD_FP(LOAD(ldd, %o1, %f4), U3_retl_o2_plus_g2)
223 faligndata %f4, %f6, %f0
228 EX_LD_FP(LOAD(ldd, %o1 + 0x8, %f4), U3_retl_o2_plus_g2)
231 faligndata %f6, %f4, %f2
246 EX_LD_FP(LOAD(ldd, %o1 + 0x010, %f4), U3_retl_o2)
250 faligndata %f2, %f4, %f18
252 faligndata %f4, %f6, %f20
273 EX_LD_FP(LOAD(ldd, %o1 + 0x010, %f4), U3_retl_o2_plus_o3_sll_6_plus_0x80)
281 faligndata %f2, %f4, %f18
283 faligndata %f4, %f6, %f20
[all …]
Dxor.S43 fxor %f4, %f20, %f20
70 fxor %f4, %f20, %f20
113 fxor %f4, %f20, %f52
138 fxor %f4, %f20, %f52
179 fxor %f4, %f20, %f20
214 fxor %f4, %f20, %f20
265 fxor %f4, %f20, %f52
310 fxor %f4, %f20, %f52
Dclear_page.S80 faddd %f0, %f2, %f4
/arch/mips/include/asm/
Dfpregdef.h45 #define ft0 $f4 /* caller saved */
86 #define ft0 $f4 /* caller saved */
Dasmmacro-32.h21 s.d $f4, THREAD_FPR4(\thread)
45 l.d $f4, THREAD_FPR4(\thread)
/arch/mips/kernel/
Dr6000_fpu.S35 sdc1 $f4,(SC_FPREGS+32)(a0)
72 ldc1 $f4,(SC_FPREGS+32)(a0)
Dr4k_switch.S174 mtc1 t1, $f4
214 mthc1 t1, $f4
248 dmtc1 t1, $f4
Dr2300_fpu.S39 EX(swc1 $f4,(SC_FPREGS+32)(a0))
94 EX(lwc1 $f4,(SC_FPREGS+32)(a0))
Dr2300_switch.S112 mtc1 t0, $f4
Dr4k_fpu.S90 EX sdc1 $f4, 32(a0)
155 EX ldc1 $f4, 32(a0)
/arch/mips/kvm/
Dfpu.S46 sdc1 $f4, VCPU_FPR4(a0)
90 ldc1 $f4, VCPU_FPR4(a0)
/arch/powerpc/crypto/
Daes-tab-4k.S58 .long R(68, 34, 34, 5c), R(51, a5, a5, f4)
131 .long R(f3, f4, f4, 07), R(cf, ea, ea, 25)
132 .long R(ca, 65, 65, af), R(f4, 7a, 7a, 8e)
169 .long R(51, f4, a7, 50), R(7e, 41, 65, 53)
185 .long R(75, c2, 89, 6a), R(f4, 8e, 79, 78)
203 .long R(65, da, f4, cd), R(06, 05, be, d5)
261 .long R(cd, 26, 78, 09), R(6e, 59, 18, f4)
/arch/ia64/include/uapi/asm/
Dptrace.h162 struct ia64_fpreg f4; /* preserved */ member
/arch/sparc/kernel/
Dfpu_traps.S35 faddd %f0, %f2, %f4
67 faddd %f0, %f2, %f4
252 fitod %f4, %f62
295 fdtos %f62, %f4
/arch/x86/crypto/sha-mb/
Dsha1_x8_avx2.S77 # r5 = {f7 f6 f5 f4 f3 f2 f1 f0}
86 # r4 = {h4 g4 f4 e4 d4 c4 b4 a4}
105 vshufps $0x44, \r5, \r4, \r2 # r2 = {f5 f4 e5 e4 f1 f0 e1 e0}
112 vshufps $0x88, \t1, \r2, \t1 # t1 = {h4 g4 f4 e4 h0 g0 f0 e0}
/arch/ia64/kernel/
Dentry.h45 .spillsp f4,SW(F4)+16+(off); .spillsp f5,SW(F5)+16+(off); \

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