| /arch/sh/kernel/ |
| D | traps_32.c | 86 static int handle_unaligned_ins(insn_size_t instruction, struct pt_regs *regs, in handle_unaligned_ins() argument
94 index = (instruction>>8)&15; /* 0x0F00 */ in handle_unaligned_ins()
97 index = (instruction>>4)&15; /* 0x00F0 */ in handle_unaligned_ins()
100 count = 1<<(instruction&3); in handle_unaligned_ins()
110 switch (instruction>>12) { in handle_unaligned_ins()
112 if (instruction & 8) { in handle_unaligned_ins()
144 dstu += (instruction&0x000F)<<2; in handle_unaligned_ins()
152 if (instruction & 4) in handle_unaligned_ins()
166 srcu += (instruction & 0x000F) << 2; in handle_unaligned_ins()
177 if (instruction & 4) in handle_unaligned_ins()
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| D | io_trapped.c | 274 insn_size_t instruction; in handle_trapped_io() local
286 if (copy_from_user(&instruction, (void *)(regs->pc), in handle_trapped_io()
287 sizeof(instruction))) { in handle_trapped_io()
292 tmp = handle_unaligned_access(instruction, regs, in handle_trapped_io()
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| /arch/nios2/platform/ |
| D | Kconfig.platform | 57 bool "Enable MUL instruction"
61 instruction. This will enable the -mhw-mul compiler flag.
64 bool "Enable MULX instruction"
68 instruction. Enables the -mhw-mulx compiler flag.
71 bool "Enable DIV instruction"
75 instruction. Enables the -mhw-div compiler flag.
84 bool "Byteswap custom instruction"
87 Use the byteswap (endian converter) Nios II custom instruction provided
92 int "Byteswap custom instruction number" if NIOS2_CI_SWAB_SUPPORT
95 Number of the instruction as configured in QSYS Builder.
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| /arch/openrisc/ |
| D | Kconfig | 79 bool "Have instruction l.ff1"
82 Select this if your implementation has the Class II instruction l.ff1
85 bool "Have instruction l.fl1"
88 Select this if your implementation has the Class II instruction l.fl1
91 bool "Have instruction l.mul for hardware multiply"
94 Select this if your implementation has a hardware multiply instruction
97 bool "Have instruction l.div for hardware divide"
100 Select this if your implementation has a hardware divide instruction
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| /arch/m68k/fpsp040/ |
| D | smovecr.S | 5 | offset given in the instruction field.
7 | Input: An offset in the instruction word.
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| D | bugfix.S | 247 | dest and the dest of the xu. We must clear the instruction in
248 | the cu and restore the state, allowing the instruction in the
249 | xu to complete. Remember, the instruction in the nu
251 | If the result of the xu instruction is not exceptional, we can
252 | restore the instruction from the cu to the frame and continue
275 | Check if the instruction which just completed was exceptional.
280 | It is necessary to isolate the result of the instruction in the
369 | dest and the dest of the xu. We must clear the instruction in
370 | the cu and restore the state, allowing the instruction in the
371 | xu to complete. Remember, the instruction in the nu
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| /arch/arm/nwfpe/ |
| D | entry.S | 90 bne next @ get the next instruction;
93 bl EmulateAll @ emulate the instruction
99 .Lx1: ldrt r6, [r5], #4 @ get the next instruction and
116 @ plain LDR instruction. Weird, but it seems harmless.
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| D | fpmodule.inl | 24 /* Note: The CPU thinks it has dealt with the current instruction.
26 instruction, and points 4 bytes beyond the actual instruction
27 that caused the invalid instruction trap to occur. We adjust
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| /arch/arm/probes/kprobes/ |
| D | test-core.h | 157 #define TEST_INSTRUCTION(instruction) \ argument
159 "1: "instruction" \n\t" \
162 #define TEST_BRANCH_F(instruction) \ argument
163 TEST_INSTRUCTION(instruction) \
167 #define TEST_BRANCH_B(instruction) \ argument
172 TEST_INSTRUCTION(instruction)
174 #define TEST_BRANCH_FX(instruction, codex) \ argument
175 TEST_INSTRUCTION(instruction) \
181 #define TEST_BRANCH_BX(instruction, codex) \ argument
187 TEST_INSTRUCTION(instruction)
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| /arch/frv/kernel/ |
| D | cmode.S | 88 # (4) Preload a series of following instructions to the instruction
111 # (5) Flush the content of all caches by the DCEF instruction.
123 # (8) Execute memory barrier instruction (MEMBAR).
132 # (10) Execute memory barrier instruction (MEMBAR).
144 # (13) Execute the instruction just after the memory barrier
145 # instruction that executes the self-loop 256 times. (Meanwhile,
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| /arch/xtensa/ |
| D | Kconfig.debug | 27 bool "Perform S32C1I instruction self-test at boot"
30 Enable this option to test S32C1I instruction behavior at boot.
31 Correct operation of this instruction requires some cooperation from hardware
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| /arch/powerpc/xmon/ |
| D | ppc.h | 179 (unsigned long instruction, long op, int dialect, const char **errmsg);
198 long (*extract) (unsigned long instruction, int dialect, int *invalid);
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| /arch/arm/kernel/ |
| D | entry-armv.S | 242 @ Correct the PC such that it is pointing at the instruction
243 @ which caused the fault. If the faulting instruction was ARM
244 @ the PC will be pointing at the next instruction, and have to
246 @ pointing at the second half of the Thumb instruction. We
257 @ If a kprobe is about to simulate a "stmdb sp..." instruction,
266 @ the instruction, or the more conventional lr if we are to treat
267 @ this as a real undefined instruction
269 @ r0 - instruction
275 ldrh r0, [r4, #-2] @ Thumb instruction at LR - 2
276 cmp r0, #0xe800 @ 32-bit instruction if xx >= 0
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| /arch/ia64/scripts/ |
| D | check-serialize.S | 2 .serialize.instruction
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| /arch/m68k/ifpsp060/src/ |
| D | isp.S | 1218 mov.l EXC_EXTWPTR(%a6),%a0 # fetch instruction addr
1219 addq.l &0x2,EXC_EXTWPTR(%a6) # incr instruction ptr
1230 mov.l EXC_EXTWPTR(%a6),%a0 # fetch instruction addr
1231 addq.l &0x2,EXC_EXTWPTR(%a6) # incr instruction ptr
1242 mov.l EXC_EXTWPTR(%a6),%a0 # fetch instruction addr
1243 addq.l &0x2,EXC_EXTWPTR(%a6) # incr instruction ptr
1254 mov.l EXC_EXTWPTR(%a6),%a0 # fetch instruction addr
1255 addq.l &0x2,EXC_EXTWPTR(%a6) # incr instruction ptr
1266 mov.l EXC_EXTWPTR(%a6),%a0 # fetch instruction addr
1267 addq.l &0x2,EXC_EXTWPTR(%a6) # incr instruction ptr
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| D | pfpsp.S | 1228 # the FPIAR holds the "current PC" of the faulting instruction
1232 mov.l EXC_EXTWPTR(%a6),%a0 # fetch instruction addr
1233 addq.l &0x4,EXC_EXTWPTR(%a6) # incr instruction ptr
1234 bsr.l _imem_read_long # fetch the instruction words
1722 # three instruction exceptions don't update the stack pointer. so, if the
2038 # The opclass two PACKED instruction that took an "Unimplemented Data Type"
2371 # _imem_read_long() - read instruction longword #
2384 # fmovm_dynamic() - emulate dynamic fmovm instruction #
2385 # fmovm_ctrl() - emulate fmovm control instruction #
2404 # (2) The "fmovm.x" instruction w/ dynamic register specification. #
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| /arch/mips/bcm47xx/ |
| D | Kconfig | 19 This will generate an image with support for SSB and MIPS32 R1 instruction set.
36 This will generate an image with support for BCMA and MIPS32 R2 instruction set.
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| /arch/arm/vfp/ |
| D | entry.S | 20 @ r0 = instruction opcode (32-bit ARM or two 16-bit Thumb)
24 @ lr = unrecognised instruction return address
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| /arch/m68k/ifpsp060/ |
| D | CHANGES | 41 3) For an opclass three FP instruction where the effective addressing
62 next instruction, and the result created in fp0 will be
78 For instruction read access errors, the info stacked is:
80 PC = PC of instruction being emulated
82 ADDRESS = PC of instruction being emulated
102 PC = PC of instruction being emulated
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| D | ilsp.doc | 35 and the "cmp2" instruction. These instructions are not
71 function. A branch instruction located at the selected entry point
78 For example, to use a 64-bit multiply instruction,
115 An example of using the "cmp2" instruction is as follows:
128 If the instruction being emulated is a divide and the source
130 instruction, executes an implemented divide using a zero
133 point to the correct instruction, the user will at least be able
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| /arch/powerpc/lib/ |
| D | code-patching.c | 67 unsigned int instruction; in create_branch() local
79 instruction = 0x48000000 | (flags & 0x3) | (offset & 0x03FFFFFC); in create_branch()
81 return instruction; in create_branch()
87 unsigned int instruction; in create_cond_branch() local
99 instruction = 0x40000000 | (flags & 0x3FF0003) | (offset & 0xFFFC); in create_cond_branch()
101 return instruction; in create_cond_branch()
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| /arch/unicore32/mm/ |
| D | Kconfig | 4 # which CPUs we support in the kernel image, and the compiler instruction
15 Say Y here to disable the processor instruction cache. Unless
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| /arch/mips/dec/prom/ |
| D | locore.S | 26 addiu k0, 4 # skip the causing instruction
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| /arch/powerpc/kernel/ |
| D | align.c | 772 unsigned int instr, nb, flags, instruction = 0; in fix_alignment() local
824 instruction = instr; in fix_alignment()
848 if (IS_XFORM(instruction)) { in fix_alignment()
849 switch (get_xop(instruction)) { in fix_alignment()
890 if ((instruction & 0xfc00003e) == 0x7c000018) { in fix_alignment()
894 reg |= (instruction & 0x1) << 5; in fix_alignment()
898 if (instruction & 0x200) in fix_alignment()
904 if (instruction & 0x80) in fix_alignment()
910 if (instruction & 0x100) in fix_alignment()
912 if (instruction & 0x040) in fix_alignment()
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| /arch/s390/include/asm/ |
| D | dis.h | 45 int insn_to_mnemonic(unsigned char *instruction, char *buf, unsigned int len);
|