| /arch/mn10300/mm/ |
| D | Makefile | 8 cacheflush-$(CONFIG_SMP) += cache-smp.o cache-smp-inv.o $(cache-smp-wback-y)
9 cacheflush-$(CONFIG_MN10300_CACHE_INV_ICACHE) += cache-inv-icache.o
11 cacheflush-$(CONFIG_MN10300_CACHE_INV_BY_TAG) += cache-inv-by-tag.o
12 cacheflush-$(CONFIG_MN10300_CACHE_INV_BY_REG) += cache-inv-by-reg.o
17 cache-dbg-flush-by-tag.o cache-dbg-inv-by-tag.o
21 cache-dbg-inv-by-tag.o cache-dbg-inv.o
23 cache-dbg-inv-by-reg.o cache-dbg-inv.o
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| /arch/cris/arch-v10/mm/ |
| D | fault.c | 46 int acc, inv; in handle_mmu_bus_fault() local
63 inv = IO_EXTRACT(R_MMU_CAUSE, inv_excp, cause); in handle_mmu_bus_fault()
71 regs->irp, address, miss, inv, we, acc, index, page_id)); in handle_mmu_bus_fault()
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| /arch/arm/boot/dts/ |
| D | stih416-b2020.dts | 29 st,pcie-tx-pol-inv;
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| D | stih416-b2020e.dts | 47 st,pcie-tx-pol-inv;
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| /arch/arm/mm/ |
| D | proc-feroceon.S | 265 mcr p15, 5, r0, c15, c15, 0 @ D clean/inv range start
266 mcr p15, 5, r1, c15, c15, 1 @ D clean/inv range top
311 mcr p15, 5, r0, c15, c14, 0 @ D inv range start
312 mcr p15, 5, r1, c15, c14, 1 @ D inv range top
374 mcr p15, 5, r0, c15, c15, 0 @ D clean/inv range start
375 mcr p15, 5, r1, c15, c15, 1 @ D clean/inv range top
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| /arch/x86/kernel/cpu/ |
| D | perf_event_p6.c | 187 PMU_FORMAT_ATTR(inv, "config:23" );
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| D | perf_event_intel.c | 2465 u64 alt_config = X86_CONFIG(.event=0xc0, .inv=1, .cmask=16); in intel_pebs_aliases_core2()
2493 u64 alt_config = X86_CONFIG(.event=0xc2, .umask=0x01, .inv=1, .cmask=16); in intel_pebs_aliases_snb()
2730 PMU_FORMAT_ATTR(inv, "config:23" );
3335 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1); in intel_pmu_init()
3338 X86_CONFIG(.event=0xb1, .umask=0x3f, .inv=1, .cmask=1); in intel_pmu_init()
3398 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1); in intel_pmu_init()
3401 X86_CONFIG(.event=0xb1, .umask=0x3f, .inv=1, .cmask=1); in intel_pmu_init()
3435 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1); in intel_pmu_init()
3438 X86_CONFIG(.event=0xb1, .umask=0x01, .inv=1, .cmask=1); in intel_pmu_init()
3471 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1); in intel_pmu_init()
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| D | perf_event_intel_uncore_snb.c | 69 DEFINE_UNCORE_FORMAT_ATTR(inv, inv, "config:23");
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| D | perf_event_knc.c | 277 PMU_FORMAT_ATTR(inv, "config:23" );
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| D | perf_event_amd.c | 455 PMU_FORMAT_ATTR(inv, "config:23" );
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| D | perf_event_intel_uncore_nhmex.c | 193 DEFINE_UNCORE_FORMAT_ATTR(inv, inv, "config:23");
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| D | perf_event.h | 484 inv:1, member
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| D | perf_event.c | 1660 bool inv = (config & ARCH_PERFMON_EVENTSEL_INV); in x86_event_sysfs_show() local
1681 if (inv) in x86_event_sysfs_show()
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| D | perf_event_intel_uncore_snbep.c | 218 DEFINE_UNCORE_FORMAT_ATTR(inv, inv, "config:23");
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| /arch/cris/arch-v32/mm/ |
| D | init.c | 53 REG_STATE(mmu, rw_mm_cfg, inv, on) | in cris_mmu_init()
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| /arch/cris/include/arch-v32/arch/hwregs/iop/ |
| D | iop_timer_grp_defs.h | 121 unsigned int inv : 1; member
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| /arch/cris/arch-v32/kernel/ |
| D | head.S | 93 | REG_STATE(mmu, rw_mm_cfg, inv, on) \
114 | REG_STATE(mmu, rw_mm_cfg, inv, on) \
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| /arch/arm/crypto/ |
| D | bsaes-armv7.pl | 380 my $inv=@_[16]; # optional
422 $code.=<<___ if (!$inv);
431 $code.=<<___ if ($inv);
|