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Searched refs:msel (Results 1 – 2 of 2) sorted by relevance

/arch/blackfin/mach-bf609/
Dclock.c141 u32 msel; in pll_get_rate() local
146 msel = (ctl & CGU0_CTL_MSEL_MASK) >> CGU0_CTL_MSEL_SHIFT; in pll_get_rate()
149 return clk->parent->rate / (df + 1) * msel * 2; in pll_get_rate()
161 u32 msel; in pll_set_rate() local
169 msel = rate / clk->parent->rate / 2; in pll_set_rate()
170 clk_reg_write_mask(CGU0_CTL, msel << CGU0_CTL_MSEL_SHIFT, in pll_set_rate()
187 u32 msel; in sys_clk_get_rate() local
192 msel = (ctl & CGU0_CTL_MSEL_MASK) >> CGU0_CTL_MSEL_SHIFT; in sys_clk_get_rate()
197 drate *= msel; in sys_clk_get_rate()
217 u32 msel; in sys_clk_round_rate() local
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/arch/blackfin/kernel/
Dsetup.c1149 u_long msel, pll_ctl; local
1158 msel = (pll_ctl >> 9) & 0x3F;
1159 if (0 == msel)
1160 msel = 64;
1164 cached_vco *= msel;