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Searched refs:mstp_clks (Results 1 – 12 of 12) sorted by relevance

/arch/sh/kernel/cpu/sh4a/
Dclock-sh7734.c127 static struct clk mstp_clks[MSTP_NR] = { variable
195 CLKDEV_DEV_ID("i2c-sh7734.0", &mstp_clks[MSTP030]),
196 CLKDEV_DEV_ID("i2c-sh7734.1", &mstp_clks[MSTP029]),
197 CLKDEV_ICK_ID("sci_fck", "sh-sci.0", &mstp_clks[MSTP026]),
198 CLKDEV_ICK_ID("sci_fck", "sh-sci.1", &mstp_clks[MSTP025]),
199 CLKDEV_ICK_ID("sci_fck", "sh-sci.2", &mstp_clks[MSTP024]),
200 CLKDEV_ICK_ID("sci_fck", "sh-sci.3", &mstp_clks[MSTP023]),
201 CLKDEV_ICK_ID("sci_fck", "sh-sci.4", &mstp_clks[MSTP022]),
202 CLKDEV_ICK_ID("sci_fck", "sh-sci.5", &mstp_clks[MSTP021]),
203 CLKDEV_CON_ID("hscif", &mstp_clks[MSTP019]),
[all …]
Dclock-sh7723.c153 static struct clk mstp_clks[] = { variable
228 CLKDEV_CON_ID("tlb0", &mstp_clks[HWBLK_TLB]),
229 CLKDEV_CON_ID("ic0", &mstp_clks[HWBLK_IC]),
230 CLKDEV_CON_ID("oc0", &mstp_clks[HWBLK_OC]),
231 CLKDEV_CON_ID("l2c0", &mstp_clks[HWBLK_L2C]),
232 CLKDEV_CON_ID("ilmem0", &mstp_clks[HWBLK_ILMEM]),
233 CLKDEV_CON_ID("fpu0", &mstp_clks[HWBLK_FPU]),
234 CLKDEV_CON_ID("intc0", &mstp_clks[HWBLK_INTC]),
235 CLKDEV_DEV_ID("sh-dma-engine.0", &mstp_clks[HWBLK_DMAC0]),
236 CLKDEV_CON_ID("sh0", &mstp_clks[HWBLK_SHYWAY]),
[all …]
Dclock-sh7724.c214 static struct clk mstp_clks[HWBLK_NR] = { variable
294 CLKDEV_CON_ID("tlb0", &mstp_clks[HWBLK_TLB]),
295 CLKDEV_CON_ID("ic0", &mstp_clks[HWBLK_IC]),
296 CLKDEV_CON_ID("oc0", &mstp_clks[HWBLK_OC]),
297 CLKDEV_CON_ID("rs0", &mstp_clks[HWBLK_RSMEM]),
298 CLKDEV_CON_ID("ilmem0", &mstp_clks[HWBLK_ILMEM]),
299 CLKDEV_CON_ID("l2c0", &mstp_clks[HWBLK_L2C]),
300 CLKDEV_CON_ID("fpu0", &mstp_clks[HWBLK_FPU]),
301 CLKDEV_CON_ID("intc0", &mstp_clks[HWBLK_INTC]),
302 CLKDEV_DEV_ID("sh-dma-engine.0", &mstp_clks[HWBLK_DMAC0]),
[all …]
Dclock-sh7786.c93 static struct clk mstp_clks[MSTP_NR] = { variable
142 CLKDEV_ICK_ID("sci_fck", "sh-sci.5", &mstp_clks[MSTP029]),
143 CLKDEV_ICK_ID("sci_fck", "sh-sci.4", &mstp_clks[MSTP028]),
144 CLKDEV_ICK_ID("sci_fck", "sh-sci.3", &mstp_clks[MSTP027]),
145 CLKDEV_ICK_ID("sci_fck", "sh-sci.2", &mstp_clks[MSTP026]),
146 CLKDEV_ICK_ID("sci_fck", "sh-sci.1", &mstp_clks[MSTP025]),
147 CLKDEV_ICK_ID("sci_fck", "sh-sci.0", &mstp_clks[MSTP024]),
149 CLKDEV_CON_ID("ssi3_fck", &mstp_clks[MSTP023]),
150 CLKDEV_CON_ID("ssi2_fck", &mstp_clks[MSTP022]),
151 CLKDEV_CON_ID("ssi1_fck", &mstp_clks[MSTP021]),
[all …]
Dclock-sh7343.c150 static struct clk mstp_clks[MSTP_NR] = { variable
218 CLKDEV_CON_ID("tlb0", &mstp_clks[MSTP031]),
219 CLKDEV_CON_ID("ic0", &mstp_clks[MSTP030]),
220 CLKDEV_CON_ID("oc0", &mstp_clks[MSTP029]),
221 CLKDEV_CON_ID("uram0", &mstp_clks[MSTP028]),
222 CLKDEV_CON_ID("xymem0", &mstp_clks[MSTP026]),
223 CLKDEV_CON_ID("intc3", &mstp_clks[MSTP023]),
224 CLKDEV_CON_ID("intc0", &mstp_clks[MSTP022]),
225 CLKDEV_CON_ID("dmac0", &mstp_clks[MSTP021]),
226 CLKDEV_CON_ID("sh0", &mstp_clks[MSTP020]),
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Dclock-sh7366.c152 static struct clk mstp_clks[MSTP_NR] = { variable
216 CLKDEV_CON_ID("tlb0", &mstp_clks[MSTP031]),
217 CLKDEV_CON_ID("ic0", &mstp_clks[MSTP030]),
218 CLKDEV_CON_ID("oc0", &mstp_clks[MSTP029]),
219 CLKDEV_CON_ID("rsmem0", &mstp_clks[MSTP028]),
220 CLKDEV_CON_ID("xymem0", &mstp_clks[MSTP026]),
221 CLKDEV_CON_ID("intc3", &mstp_clks[MSTP023]),
222 CLKDEV_CON_ID("intc0", &mstp_clks[MSTP022]),
223 CLKDEV_CON_ID("dmac0", &mstp_clks[MSTP021]),
224 CLKDEV_CON_ID("sh0", &mstp_clks[MSTP020]),
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Dclock-sh7757.c86 static struct clk mstp_clks[MSTP_NR] = { variable
116 CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[MSTP004]),
117 CLKDEV_CON_ID("riic0", &mstp_clks[MSTP000]),
118 CLKDEV_CON_ID("riic1", &mstp_clks[MSTP000]),
119 CLKDEV_CON_ID("riic2", &mstp_clks[MSTP000]),
120 CLKDEV_CON_ID("riic3", &mstp_clks[MSTP000]),
121 CLKDEV_CON_ID("riic4", &mstp_clks[MSTP000]),
122 CLKDEV_CON_ID("riic5", &mstp_clks[MSTP000]),
123 CLKDEV_CON_ID("riic6", &mstp_clks[MSTP000]),
124 CLKDEV_CON_ID("riic7", &mstp_clks[MSTP000]),
[all …]
Dclock-sh7785.c92 static struct clk mstp_clks[MSTP_NR] = { variable
135 CLKDEV_ICK_ID("sci_fck", "sh-sci.5", &mstp_clks[MSTP029]),
136 CLKDEV_ICK_ID("sci_fck", "sh-sci.4", &mstp_clks[MSTP028]),
137 CLKDEV_ICK_ID("sci_fck", "sh-sci.3", &mstp_clks[MSTP027]),
138 CLKDEV_ICK_ID("sci_fck", "sh-sci.2", &mstp_clks[MSTP026]),
139 CLKDEV_ICK_ID("sci_fck", "sh-sci.1", &mstp_clks[MSTP025]),
140 CLKDEV_ICK_ID("sci_fck", "sh-sci.0", &mstp_clks[MSTP024]),
142 CLKDEV_CON_ID("ssi1_fck", &mstp_clks[MSTP021]),
143 CLKDEV_CON_ID("ssi0_fck", &mstp_clks[MSTP020]),
144 CLKDEV_CON_ID("hac1_fck", &mstp_clks[MSTP017]),
[all …]
Dclock-sh7722.c153 static struct clk mstp_clks[HWBLK_NR] = { variable
203 CLKDEV_CON_ID("uram0", &mstp_clks[HWBLK_URAM]),
204 CLKDEV_CON_ID("xymem0", &mstp_clks[HWBLK_XYMEM]),
206 CLKDEV_ICK_ID("fck", "sh-tmu.0", &mstp_clks[HWBLK_TMU]),
208 CLKDEV_ICK_ID("fck", "sh-cmt-32.0", &mstp_clks[HWBLK_CMT]),
209 CLKDEV_DEV_ID("sh-wdt.0", &mstp_clks[HWBLK_RWDT]),
210 CLKDEV_CON_ID("flctl0", &mstp_clks[HWBLK_FLCTL]),
212 CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[HWBLK_SCIF0]),
213 CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[HWBLK_SCIF1]),
214 CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[HWBLK_SCIF2]),
[all …]
Dclock-shx3.c84 static struct clk mstp_clks[MSTP_NR] = { variable
117 CLKDEV_ICK_ID("sci_fck", "sh-sci.3", &mstp_clks[MSTP027]),
118 CLKDEV_ICK_ID("sci_fck", "sh-sci.2", &mstp_clks[MSTP026]),
119 CLKDEV_ICK_ID("sci_fck", "sh-sci.1", &mstp_clks[MSTP025]),
120 CLKDEV_ICK_ID("sci_fck", "sh-sci.0", &mstp_clks[MSTP024]),
122 CLKDEV_CON_ID("h8ex_fck", &mstp_clks[MSTP003]),
123 CLKDEV_CON_ID("csm_fck", &mstp_clks[MSTP002]),
124 CLKDEV_CON_ID("fe1_fck", &mstp_clks[MSTP001]),
125 CLKDEV_CON_ID("fe0_fck", &mstp_clks[MSTP000]),
127 CLKDEV_ICK_ID("fck", "sh-tmu.0", &mstp_clks[MSTP008]),
[all …]
/arch/sh/kernel/cpu/sh2a/
Dclock-sh7269.c125 static struct clk mstp_clks[MSTP_NR] = { variable
153 CLKDEV_ICK_ID("sci_fck", "sh-sci.0", &mstp_clks[MSTP47]),
154 CLKDEV_ICK_ID("sci_fck", "sh-sci.1", &mstp_clks[MSTP46]),
155 CLKDEV_ICK_ID("sci_fck", "sh-sci.2", &mstp_clks[MSTP45]),
156 CLKDEV_ICK_ID("sci_fck", "sh-sci.3", &mstp_clks[MSTP44]),
157 CLKDEV_ICK_ID("sci_fck", "sh-sci.4", &mstp_clks[MSTP43]),
158 CLKDEV_ICK_ID("sci_fck", "sh-sci.5", &mstp_clks[MSTP42]),
159 CLKDEV_ICK_ID("sci_fck", "sh-sci.6", &mstp_clks[MSTP41]),
160 CLKDEV_ICK_ID("sci_fck", "sh-sci.7", &mstp_clks[MSTP40]),
161 CLKDEV_ICK_ID("fck", "sh-cmt-16.0", &mstp_clks[MSTP72]),
[all …]
Dclock-sh7264.c95 static struct clk mstp_clks[MSTP_NR] = { variable
118 CLKDEV_CON_ID("sci_ick", &mstp_clks[MSTP77]),
119 CLKDEV_CON_ID("vdc3", &mstp_clks[MSTP74]),
120 CLKDEV_ICK_ID("fck", "sh-cmt-16.0", &mstp_clks[MSTP72]),
121 CLKDEV_CON_ID("usb0", &mstp_clks[MSTP60]),
122 CLKDEV_ICK_ID("fck", "sh-mtu2", &mstp_clks[MSTP35]),
123 CLKDEV_CON_ID("sdhi0", &mstp_clks[MSTP34]),
124 CLKDEV_CON_ID("sdhi1", &mstp_clks[MSTP33]),
125 CLKDEV_CON_ID("adc0", &mstp_clks[MSTP32]),
126 CLKDEV_CON_ID("rtc0", &mstp_clks[MSTP30]),
[all …]