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Searched refs:nlw (Results 1 – 2 of 2) sorted by relevance

/arch/mips/pci/
Dpcie-octeon.c658 switch (pciercx_cfg032.s.nlw) { in __cvmx_pcie_rc_initialize_link_gen1()
1077 cvmx_dprintf("PCIe: Port %d link active, %d lanes\n", pcie_port, pciercx_cfg032.s.nlw); in __cvmx_pcie_rc_initialize_gen1()
1121 switch (pciercx_cfg032.s.nlw) { in __cvmx_pcie_rc_initialize_link_gen2()
1432 …pr_notice("PCIe: Port %d link active, %d lanes, speed gen%d\n", pcie_port, pciercx_cfg032.s.nlw, p… in __cvmx_pcie_rc_initialize_gen2()
/arch/mips/include/asm/octeon/
Dcvmx-pciercx-defs.h1031 uint32_t nlw:6; member
1059 uint32_t nlw:6;