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/arch/powerpc/boot/dts/fsl/
Dqoriq-clockgen1.dtsi56 pll1: pll1@820 { label
61 clock-output-names = "pll1", "pll1-div2";
67 clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
68 clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
75 clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
76 clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
Dt1040si-post.dtsi432 <&pll1 0>, <&pll1 1>, <&pll1 2>;
433 clock-names = "pll0", "pll0-div2", "pll1-div4",
434 "pll1", "pll1-div2", "pll1-div4";
443 <&pll1 0>, <&pll1 1>, <&pll1 2>;
444 clock-names = "pll0", "pll0-div2", "pll1-div4",
445 "pll1", "pll1-div2", "pll1-div4";
454 <&pll1 0>, <&pll1 1>, <&pll1 2>;
455 clock-names = "pll0", "pll0-div2", "pll1-div4",
456 "pll1", "pll1-div2", "pll1-div4";
465 <&pll1 0>, <&pll1 1>, <&pll1 2>;
Dqoriq-clockgen2.dtsi55 pll1: pll1@820 { label
60 clock-output-names = "pll1", "pll1-div2", "pll1-div4";
Dt2081si-post.dtsi544 <&pll1 0>, <&pll1 1>, <&pll1 2>;
546 "pll1", "pll1-div2", "pll1-div4";
555 <&pll1 0>, <&pll1 1>, <&pll1 2>;
557 "pll1", "pll1-div2", "pll1-div4";
Dp2041si-post.dtsi335 clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
336 clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
344 clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
345 clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
Dp5040si-post.dtsi327 clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
328 clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
336 clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
337 clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
Dp3041si-post.dtsi362 clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
363 clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
371 clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
372 clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
Dp4080si-post.dtsi398 clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
399 clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
407 clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
408 clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
Db4si-post.dtsi410 <&pll1 0>, <&pll1 1>, <&pll1 2>;
412 "pll1", "pll1-div2", "pll1-div4";
Dt4240si-post.dtsi983 <&pll1 0>, <&pll1 1>, <&pll1 2>,
986 "pll1", "pll1-div2", "pll1-div4",
996 <&pll1 0>, <&pll1 1>, <&pll1 2>,
999 "pll1", "pll1-div2", "pll1-div4",
/arch/avr32/boards/favr-32/
Dsetup.c277 struct clk *pll1; in set_abdac_rate() local
289 pll1 = clk_get(NULL, "pll1"); in set_abdac_rate()
290 if (IS_ERR(pll1)) { in set_abdac_rate()
291 retval = PTR_ERR(pll1); in set_abdac_rate()
301 retval = clk_set_parent(pll1, osc1); in set_abdac_rate()
311 retval = clk_round_rate(pll1, in set_abdac_rate()
318 retval = clk_set_rate(pll1, retval); in set_abdac_rate()
322 retval = clk_set_parent(abdac, pll1); in set_abdac_rate()
329 clk_put(pll1); in set_abdac_rate()
/arch/arm/boot/dts/
Dstih415-clock.dtsi40 "clk-s-a0-pll1";
98 "clk-s-a1-pll1";
165 clk_m_a0_pll1: clk-m-a0-pll1 {
171 clock-output-names = "clk-m-a0-pll1-phi0",
172 "clk-m-a0-pll1-phi1",
173 "clk-m-a0-pll1-phi2",
174 "clk-m-a0-pll1-phi3";
279 clk_m_a1_pll1: clk-m-a1-pll1 {
285 clock-output-names = "clk-m-a1-pll1-phi0",
286 "clk-m-a1-pll1-phi1",
[all …]
Dstih416-clock.dtsi41 "clk-s-a0-pll1";
99 "clk-s-a1-pll1";
167 clk_m_a0_pll1: clk-m-a0-pll1 {
173 clock-output-names = "clk-m-a0-pll1-phi0",
174 "clk-m-a0-pll1-phi1",
175 "clk-m-a0-pll1-phi2",
176 "clk-m-a0-pll1-phi3";
281 clk_m_a1_pll1: clk-m-a1-pll1 {
287 clock-output-names = "clk-m-a1-pll1-phi0",
288 "clk-m-a1-pll1-phi1",
[all …]
Ddra72x.dtsi42 reg-names = "dss", "pll1_clkctrl", "pll1";
Ddove-cubox.dts92 /* connect xtal input as source of pll0 and pll1 */
Dsun5i.dtsi98 pll1: clk@01c20000 { label
100 compatible = "allwinner,sun4i-a10-pll1-clk";
103 clock-output-names = "pll1";
117 compatible = "allwinner,sun4i-a10-pll1-clk";
144 clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>;
Dsun8i-a23-a33.dtsi115 pll1: clk@01c20000 { label
117 compatible = "allwinner,sun8i-a23-pll1-clk";
120 clock-output-names = "pll1";
150 clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll1>;
Ddra74x.dtsi113 reg-names = "dss", "pll1_clkctrl", "pll1",
Dstih407-clock.dtsi144 clk_s_c0_pll1: clk-s-c0-pll1 {
150 clock-output-names = "clk-s-c0-pll1-odf-0";
Dstih410-clock.dtsi147 clk_s_c0_pll1: clk-s-c0-pll1 {
153 clock-output-names = "clk-s-c0-pll1-odf-0";
Dstih418-clock.dtsi147 clk_s_c0_pll1: clk-s-c0-pll1 {
153 clock-output-names = "clk-s-c0-pll1-odf-0";
Dls1021a.dtsi207 clock-output-names = "cga-pll1", "cga-pll1-div2",
208 "cga-pll1-div4";
Dsun4i-a10.dtsi191 pll1: clk@01c20000 { label
193 compatible = "allwinner,sun4i-a10-pll1-clk";
196 clock-output-names = "pll1";
210 compatible = "allwinner,sun4i-a10-pll1-clk";
237 clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>;
Dsun6i-a31.dtsi195 pll1: clk@01c20000 { label
197 compatible = "allwinner,sun6i-a31-pll1-clk";
200 clock-output-names = "pll1";
222 clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll1>;
/arch/avr32/mach-at32ap/
Dat32ap700x.c316 static struct clk pll1 = { variable
572 if (parent == &osc1 || parent == &pll1) in genclk_set_parent()
579 if (parent == &pll0 || parent == &pll1) in genclk_set_parent()
599 parent = (control & PM_BIT(PLLSEL)) ? &pll1 : &osc1; in genclk_init_parent()
2201 &pll1,
2277 pll1.parent = &osc1; in setup_platform()

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