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Searched refs:pll_rate (Results 1 – 4 of 4) sorted by relevance

/arch/mips/ralink/
Dmt7620.c349 mt7620_get_cpu_rate(unsigned long pll_rate) in mt7620_get_cpu_rate() argument
361 return mt7620_calc_rate(pll_rate, mul, div); in mt7620_get_cpu_rate()
373 mt7620_get_dram_rate(unsigned long pll_rate) in mt7620_get_dram_rate() argument
376 return pll_rate / 4; in mt7620_get_dram_rate()
378 return pll_rate / 3; in mt7620_get_dram_rate()
407 unsigned long pll_rate; in ralink_clk_init() local
431 pll_rate = mt7620_get_pll_rate(xtal_rate, cpu_pll_rate); in ralink_clk_init()
433 cpu_rate = mt7620_get_cpu_rate(pll_rate); in ralink_clk_init()
434 dram_rate = mt7620_get_dram_rate(pll_rate); in ralink_clk_init()
441 RINT(pll_rate), RFRAC(pll_rate)); in ralink_clk_init()
/arch/arm/mach-omap1/
Dopp.h21 unsigned long pll_rate; member
Dclock.c224 ck_dpll1_p->rate = ptr->pll_rate; in omap1_select_table_rate()
/arch/unicore32/kernel/
Dclock.c182 u32 pll_rate, divstatus = readl(PM_DIVSTATUS); in clk_set_rate() local
189 pll_rate = mclk_clk_table[i].prate; in clk_set_rate()
204 writel(pll_rate, PM_PLLSYSCFG); in clk_set_rate()