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Searched refs:priv1 (Results 1 – 7 of 7) sorted by relevance

/arch/powerpc/platforms/cell/
Dspu_priv1_mmio.c43 old_mask = in_be64(&spu->priv1->int_mask_RW[class]); in int_mask_and()
44 out_be64(&spu->priv1->int_mask_RW[class], old_mask & mask); in int_mask_and()
51 old_mask = in_be64(&spu->priv1->int_mask_RW[class]); in int_mask_or()
52 out_be64(&spu->priv1->int_mask_RW[class], old_mask | mask); in int_mask_or()
57 out_be64(&spu->priv1->int_mask_RW[class], mask); in int_mask_set()
62 return in_be64(&spu->priv1->int_mask_RW[class]); in int_mask_get()
67 out_be64(&spu->priv1->int_stat_RW[class], stat); in int_stat_clear()
72 return in_be64(&spu->priv1->int_stat_RW[class]); in int_stat_get()
90 out_be64(&spu->priv1->int_route_RW, route); in cpu_affinity_set()
95 return in_be64(&spu->priv1->mfc_dar_RW); in mfc_dar_get()
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DMakefile18 spu-priv1-$(CONFIG_PPC_CELL_COMMON) += spu_priv1_mmio.o
24 $(spu-priv1-y) \
Dspu_manage.c73 iounmap(spu->priv1); in spu_unmap()
164 spu->priv1 = spu_map_prop_old(spu, node, "priv1"); in spu_map_device_old()
165 if (!spu->priv1) in spu_map_device_old()
262 (void __iomem**)&spu->priv1, NULL); in spu_map_device()
274 pr_debug(" priv1 : 0x%p\n", spu->priv1); in spu_map_device()
354 spu->local_store, spu->problem, spu->priv1, in of_create_spu()
/arch/powerpc/platforms/cell/spufs/
Dbacking_ops.c108 ctx->csa.priv1.int_stat_class2_RW &= in spu_backing_mbox_stat_poll()
110 ctx->csa.priv1.int_mask_class2_RW |= in spu_backing_mbox_stat_poll()
118 ctx->csa.priv1.int_stat_class2_RW &= in spu_backing_mbox_stat_poll()
120 ctx->csa.priv1.int_mask_class2_RW |= in spu_backing_mbox_stat_poll()
145 ctx->csa.priv1.int_mask_class2_RW |= CLASS2_ENABLE_MAILBOX_INTR; in spu_backing_ibox_read()
175 ctx->csa.priv1.int_mask_class2_RW |= in spu_backing_wbox_write()
314 sr1 = csa->priv1.mfc_sr1_RW | MFC_STATE1_MASTER_RUN_CONTROL_MASK; in spu_backing_master_start()
315 csa->priv1.mfc_sr1_RW = sr1; in spu_backing_master_start()
325 sr1 = csa->priv1.mfc_sr1_RW & ~MFC_STATE1_MASTER_RUN_CONTROL_MASK; in spu_backing_master_stop()
326 csa->priv1.mfc_sr1_RW = sr1; in spu_backing_master_stop()
Dswitch.c126 csa->priv1.int_mask_class0_RW = spu_int_mask_get(spu, 0); in disable_interrupts()
127 csa->priv1.int_mask_class1_RW = spu_int_mask_get(spu, 1); in disable_interrupts()
128 csa->priv1.int_mask_class2_RW = spu_int_mask_get(spu, 2); in disable_interrupts()
231 csa->priv1.mfc_sr1_RW = spu_mfc_sr1_get(spu); in save_mfc_sr1()
456 csa->priv1.mfc_tclass_id_RW = spu_mfc_tclass_id_get(spu); in save_mfc_tclass_id()
593 csa->priv1.resource_allocation_groupID_RW = in save_mfc_rag()
595 csa->priv1.resource_allocation_enable_RW = in save_mfc_rag()
1247 csa->priv1.resource_allocation_groupID_RW); in restore_mfc_rag()
1249 csa->priv1.resource_allocation_enable_RW); in restore_mfc_rag()
1526 spu_mfc_tclass_id_set(spu, csa->priv1.mfc_tclass_id_RW); in restore_mfc_tclass_id()
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/arch/powerpc/include/asm/
Dspu_csa.h245 struct spu_priv1_collapsed priv1; member
Dspu.h166 struct spu_priv1 __iomem *priv1; member