/arch/arm/boot/dts/ |
D | socfpga_cyclone5_de0_sockit.dts | 59 txd0-skew-ps = <0>; /* -420ps */ 60 txd1-skew-ps = <0>; /* -420ps */ 61 txd2-skew-ps = <0>; /* -420ps */ 62 txd3-skew-ps = <0>; /* -420ps */ 63 rxd0-skew-ps = <420>; /* 0ps */ 64 rxd1-skew-ps = <420>; /* 0ps */ 65 rxd2-skew-ps = <420>; /* 0ps */ 66 rxd3-skew-ps = <420>; /* 0ps */ 67 txen-skew-ps = <0>; /* -420ps */ 68 txc-skew-ps = <1860>; /* 960ps */ [all …]
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D | socfpga_arria10_socdk.dtsi | 50 * These skews assume the user's FPGA design is adding 600ps of delay 57 txd0-skew-ps = <0>; /* -420ps */ 58 txd1-skew-ps = <0>; /* -420ps */ 59 txd2-skew-ps = <0>; /* -420ps */ 60 txd3-skew-ps = <0>; /* -420ps */ 61 rxd0-skew-ps = <420>; /* 0ps */ 62 rxd1-skew-ps = <420>; /* 0ps */ 63 rxd2-skew-ps = <420>; /* 0ps */ 64 rxd3-skew-ps = <420>; /* 0ps */ 65 txen-skew-ps = <0>; /* -420ps */ [all …]
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D | sama5d3xcm.dtsi | 47 txen-skew-ps = <800>; 48 txc-skew-ps = <3000>; 49 rxdv-skew-ps = <400>; 50 rxc-skew-ps = <3000>; 51 rxd0-skew-ps = <400>; 52 rxd1-skew-ps = <400>; 53 rxd2-skew-ps = <400>; 54 rxd3-skew-ps = <400>; 61 txen-skew-ps = <800>; 62 txc-skew-ps = <3000>; [all …]
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D | orion5x-rd88f5182-nas.dts | 52 devbus,turn-off-ps = <90000>; 53 devbus,badr-skew-ps = <0>; 54 devbus,acc-first-ps = <186000>; 55 devbus,acc-next-ps = <186000>; 58 devbus,wr-high-ps = <90000>; 59 devbus,wr-low-ps = <90000>; 60 devbus,ale-wr-ps = <90000>; 74 devbus,turn-off-ps = <90000>; 75 devbus,badr-skew-ps = <0>; 76 devbus,acc-first-ps = <186000>; [all …]
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D | socfpga_cyclone5_sockit.dts | 54 rxd0-skew-ps = <0>; 55 rxd1-skew-ps = <0>; 56 rxd2-skew-ps = <0>; 57 rxd3-skew-ps = <0>; 58 txen-skew-ps = <0>; 59 txc-skew-ps = <2600>; 60 rxdv-skew-ps = <0>; 61 rxc-skew-ps = <2000>;
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D | socfpga_arria5_socdk.dts | 54 rxd0-skew-ps = <0>; 55 rxd1-skew-ps = <0>; 56 rxd2-skew-ps = <0>; 57 rxd3-skew-ps = <0>; 58 txen-skew-ps = <0>; 59 txc-skew-ps = <2600>; 60 rxdv-skew-ps = <0>; 61 rxc-skew-ps = <2000>;
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D | socfpga_cyclone5_socdk.dts | 54 rxd0-skew-ps = <0>; 55 rxd1-skew-ps = <0>; 56 rxd2-skew-ps = <0>; 57 rxd3-skew-ps = <0>; 58 txen-skew-ps = <0>; 59 txc-skew-ps = <2600>; 60 rxdv-skew-ps = <0>; 61 rxc-skew-ps = <2000>;
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D | orion5x-lacie-ethernet-disk-mini-v2.dts | 72 devbus,turn-off-ps = <90000>; 73 devbus,badr-skew-ps = <0>; 74 devbus,acc-first-ps = <186000>; 75 devbus,acc-next-ps = <186000>; 78 devbus,wr-high-ps = <90000>; 79 devbus,wr-low-ps = <90000>; 80 devbus,ale-wr-ps = <90000>;
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D | armada-xp-openblocks-ax3-4.dts | 79 devbus,turn-off-ps = <60000>; 80 devbus,badr-skew-ps = <0>; 81 devbus,acc-first-ps = <124000>; 82 devbus,acc-next-ps = <248000>; 83 devbus,rd-setup-ps = <0>; 84 devbus,rd-hold-ps = <0>; 88 devbus,wr-high-ps = <60000>; 89 devbus,wr-low-ps = <60000>; 90 devbus,ale-wr-ps = <60000>;
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D | armada-xp-db.dts | 89 devbus,turn-off-ps = <60000>; 90 devbus,badr-skew-ps = <0>; 91 devbus,acc-first-ps = <124000>; 92 devbus,acc-next-ps = <248000>; 93 devbus,rd-setup-ps = <0>; 94 devbus,rd-hold-ps = <0>; 98 devbus,wr-high-ps = <60000>; 99 devbus,wr-low-ps = <60000>; 100 devbus,ale-wr-ps = <60000>;
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D | armada-xp-gp.dts | 108 devbus,turn-off-ps = <60000>; 109 devbus,badr-skew-ps = <0>; 110 devbus,acc-first-ps = <124000>; 111 devbus,acc-next-ps = <248000>; 112 devbus,rd-setup-ps = <0>; 113 devbus,rd-hold-ps = <0>; 117 devbus,wr-high-ps = <60000>; 118 devbus,wr-low-ps = <60000>; 119 devbus,ale-wr-ps = <60000>;
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/arch/sparc/include/asm/ |
D | ide.h | 40 u16 *ps = dst; in __ide_insw() local 43 if(((unsigned long)ps) & 0x2) { in __ide_insw() 44 *ps++ = __raw_readw(port); in __ide_insw() 47 pi = (u32 *)ps; in __ide_insw() 56 ps = (u16 *)pi; in __ide_insw() 58 *ps++ = __raw_readw(port); in __ide_insw() 70 const u16 *ps = src; in __ide_outsw() local 74 __raw_writew(*ps++, port); in __ide_outsw() 77 pi = (const u32 *)ps; in __ide_outsw() 86 ps = (const u16 *)pi; in __ide_outsw() [all …]
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/arch/sparc/lib/ |
D | PeeCeeI.c | 120 u16 *ps = dst; in insw() local 123 if (((unsigned long)ps) & 0x2) { in insw() 124 *ps++ = __raw_readw(addr); in insw() 127 pi = (u32 *)ps; in insw() 136 ps = (u16 *)pi; in insw() 138 *ps = __raw_readw(addr); in insw() 154 u16 *ps; in insl() local 159 ps = dst; in insl() 162 *ps++ = l; in insl() 163 pi = (u32 *)ps; in insl() [all …]
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/arch/x86/kvm/ |
D | i8254.c | 111 struct kvm_kpit_state *ps = &kvm->arch.vpit->pit_state; in __kpit_elapsed() local 113 if (!ps->period) in __kpit_elapsed() 125 remaining = hrtimer_get_remaining(&ps->timer); in __kpit_elapsed() 126 elapsed = ps->period - ktime_to_ns(remaining); in __kpit_elapsed() 237 struct kvm_kpit_state *ps = container_of(kian, struct kvm_kpit_state, in kvm_pit_ack_irq() local 241 spin_lock(&ps->inject_lock); in kvm_pit_ack_irq() 242 value = atomic_dec_return(&ps->pending); in kvm_pit_ack_irq() 247 atomic_inc(&ps->pending); in kvm_pit_ack_irq() 248 else if (value > 0 && ps->reinject) in kvm_pit_ack_irq() 252 queue_kthread_work(&ps->pit->worker, &ps->pit->expired); in kvm_pit_ack_irq() [all …]
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/arch/tile/mm/ |
D | hugetlbpage.c | 248 static __init int __setup_hugepagesz(unsigned long ps) in __setup_hugepagesz() argument 250 int log_ps = __builtin_ctzl(ps); in __setup_hugepagesz() 253 if ((1UL << log_ps) != ps || (log_ps & 1) != 0) { in __setup_hugepagesz() 255 ps); in __setup_hugepagesz() 259 if (ps > 64*1024*1024*1024UL) { in __setup_hugepagesz() 261 ps >> 20); in __setup_hugepagesz() 263 } else if (ps >= PUD_SIZE) { in __setup_hugepagesz() 274 } else if (ps >= PMD_SIZE) { in __setup_hugepagesz() 277 } else if (ps > PAGE_SIZE) { in __setup_hugepagesz() 281 pr_err("hugepagesz: huge page size %ld too small\n", ps); in __setup_hugepagesz() [all …]
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/arch/powerpc/boot/dts/ |
D | virtex440-ml507.dts | 189 xlnx,mch-plb-clk-period-ps = <0x2710>; 218 xlnx,tavdv-ps-mem-0 = <0x1adb0>; 219 xlnx,tavdv-ps-mem-1 = <0x3a98>; 220 xlnx,tavdv-ps-mem-2 = <0x3a98>; 221 xlnx,tavdv-ps-mem-3 = <0x3a98>; 222 xlnx,tcedv-ps-mem-0 = <0x1adb0>; 223 xlnx,tcedv-ps-mem-1 = <0x3a98>; 224 xlnx,tcedv-ps-mem-2 = <0x3a98>; 225 xlnx,tcedv-ps-mem-3 = <0x3a98>; 226 xlnx,thzce-ps-mem-0 = <0x88b8>; [all …]
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D | virtex440-ml510.dts | 160 xlnx,mch-plb-clk-period-ps = <0x2710>; 189 xlnx,tavdv-ps-mem-0 = <0x1adb0>; 190 xlnx,tavdv-ps-mem-1 = <0x3a98>; 191 xlnx,tavdv-ps-mem-2 = <0x3a98>; 192 xlnx,tavdv-ps-mem-3 = <0x3a98>; 193 xlnx,tcedv-ps-mem-0 = <0x1adb0>; 194 xlnx,tcedv-ps-mem-1 = <0x3a98>; 195 xlnx,tcedv-ps-mem-2 = <0x3a98>; 196 xlnx,tcedv-ps-mem-3 = <0x3a98>; 197 xlnx,thzce-ps-mem-0 = <0x88b8>; [all …]
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/arch/microblaze/boot/dts/ |
D | system.dts | 152 xlnx,mch-plb-clk-period-ps = <0x1f40>; 181 xlnx,tavdv-ps-mem-0 = <0x1adb0>; 182 xlnx,tavdv-ps-mem-1 = <0x3a98>; 183 xlnx,tavdv-ps-mem-2 = <0x3a98>; 184 xlnx,tavdv-ps-mem-3 = <0x3a98>; 185 xlnx,tcedv-ps-mem-0 = <0x1adb0>; 186 xlnx,tcedv-ps-mem-1 = <0x3a98>; 187 xlnx,tcedv-ps-mem-2 = <0x3a98>; 188 xlnx,tcedv-ps-mem-3 = <0x3a98>; 189 xlnx,thzce-ps-mem-0 = <0x88b8>; [all …]
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/arch/ia64/include/asm/sn/ |
D | pcibr_provider.h | 20 #define IS_PCIX(ps) ((ps)->pbi_bridge_mode & BUSTYPE_MASK) argument 23 #define IS_PIC_SOFT(ps) (ps->pbi_bridge_type == PCIBR_BRIDGETYPE_PIC) argument 24 #define IS_TIOCP_SOFT(ps) (ps->pbi_bridge_type == PCIBR_BRIDGETYPE_TIOCP) argument
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/arch/xtensa/kernel/ |
D | ptrace.c | 63 __put_user(regs->ps & ~(1 << PS_EXCM_BIT), &gregset->ps); in ptrace_getregs() 83 unsigned long ps; in ptrace_setregs() local 90 __get_user(ps, &gregset->ps); in ptrace_setregs() 98 regs->ps = (regs->ps & ~ps_mask) | (ps & ps_mask) | (1 << PS_EXCM_BIT); in ptrace_setregs() 203 tmp = (regs->ps & ~(1 << PS_EXCM_BIT)); in ptrace_peekusr()
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/arch/powerpc/boot/ |
D | addnote.c | 122 unsigned long ph, ps, np; in main() local 156 ps = GET_16(E_PHENTSIZE); in main() 158 if (ph < E_HSIZE || ps < PH_HSIZE || np < 1) in main() 160 if (ph + (np + 2) * ps + nnote + nnote2 > n) in main() 169 ph += ps; in main() 173 for (i = 0; i < 2 * ps + nnote + nnote2; ++i) in main() 178 ns = ph + 2 * ps; in main() 201 ph += ps; in main()
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/arch/xtensa/include/asm/ |
D | ptrace.h | 26 unsigned long ps; /* 8 */ member 60 # define user_mode(regs) (((regs)->ps & 0x00000020)!=0)
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/arch/x86/mm/ |
D | hugetlbpage.c | 162 unsigned long ps = memparse(opt, &opt); in setup_hugepagesz() local 163 if (ps == PMD_SIZE) { in setup_hugepagesz() 165 } else if (ps == PUD_SIZE && cpu_has_gbpages) { in setup_hugepagesz() 169 ps >> 20); in setup_hugepagesz()
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/arch/ia64/sn/pci/ |
D | tioca_provider.c | 375 int ps, ps_shift, entry, entries, mapsize; in tioca_dma_mapped() local 407 ps = tioca_kern->ca_ap_pagesize; /* will be power of 2 */ in tioca_dma_mapped() 408 ps_shift = ffs(ps) - 1; in tioca_dma_mapped() 424 bus_addr = tioca_kern->ca_pciap_base + (entry * ps); in tioca_dma_mapped() 431 if (xio_addr % ps) { in tioca_dma_mapped() 433 bus_addr += xio_addr & (ps - 1); in tioca_dma_mapped() 434 xio_addr &= ~(ps - 1); in tioca_dma_mapped() 435 xio_addr += ps; in tioca_dma_mapped() 441 xio_addr += ps; in tioca_dma_mapped()
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D | tioce_provider.c | 165 #define ATE_PAGESHIFT(ps) (__ffs(ps)) argument 166 #define ATE_PAGEMASK(ps) ((ps)-1) argument 168 #define ATE_PAGE(x, ps) ((x) >> ATE_PAGESHIFT(ps)) argument 173 #define ATE_MAKE(addr, ps, msi) \ argument 174 (((addr) & ~ATE_PAGEMASK(ps)) | (1UL << 63) | ((msi)?(1UL << 62):0)) 704 int ate_index, last_ate, ps; in tioce_reserve_m32() local 708 ps = ce_kern->ce_ate3240_pagesize; in tioce_reserve_m32() 709 ate_index = ATE_PAGE(base, ps); in tioce_reserve_m32() 710 last_ate = ate_index + ATE_NPAGES(base, limit-base+1, ps) - 1; in tioce_reserve_m32() 721 ate = ATE_MAKE(0xdeadbeef, ps, 0); in tioce_reserve_m32() [all …]
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