/arch/sh/kernel/ |
D | head_64.S | 189 movi MMUIR_FIRST, r21 192 putcfg r21, 0, ZERO /* Clear MMUIR[n].PTEH.V */ 193 addi r21, MMUIR_STEP, r21 194 bne r21, r22, tr1 198 movi MMUDR_FIRST, r21 201 putcfg r21, 0, ZERO /* Clear MMUDR[n].PTEH.V */ 202 addi r21, MMUDR_STEP, r21 203 bne r21, r22, tr1 206 movi MMUIR_FIRST, r21 209 putcfg r21, 1, r22 /* Set MMUIR[0].PTEL */ [all …]
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/arch/sh/boot/compressed/ |
D | head_64.S | 65 movi ITLB_FIXED, r21 67 1: putcfg r21, 0, r63 /* Clear MMUIR[n].PTEH.V */ 68 addi r21, TLB_STEP, r21 69 bne r21, r22, tr1 73 movi DTLB_FIXED, r21 75 1: putcfg r21, 0, r63 /* Clear MMUDR[n].PTEH.V */ 76 addi r21, TLB_STEP, r21 77 bne r21, r22, tr1 80 movi ITLB_FIXED, r21 82 putcfg r21, 1, r22 /* Set MMUIR[0].PTEL */ [all …]
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/arch/sh/lib64/ |
D | sdivsi3.S | 18 shari r25, 58, r21 /* extract 5(6) bit index (s2.4 with hole -1..1) */ 20 ldx.ub r20, r21, r19 /* u0.8 */ 22 shlli r21, 1, r21 24 ldx.w r20, r21, r21 /* s2.14 */ 27 sub r21, r19, r19 /* some 11 bit inverse in s1.14 */ 28 muls.l r19, r19, r21 /* u0.28 */ 31 muls.l r25, r21, r18 /* s2.58 */ 45 xor r21, r0, r21 /* You could also use the constant 1 << 27. */ 46 add r21, r25, r21 47 sub r21, r19, r21 [all …]
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D | udivdi3.S | 9 movi 0xffffffffffffbaf1,r21 /* .l shift count 17. */ 10 sub r21,r5,r1 35 mshalds.l r1,r21,r1 42 shlri r2,22,r21 43 mulu.l r21,r1,r21 46 shlrd r21,r0,r21 47 mulu.l r21,r3,r5 48 add r8,r21,r8 49 mcmpgt.l r21,r63,r21 // See Note 1 51 mshfhi.l r63,r21,r21 [all …]
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D | udivsi3.S | 16 sub r20,r25,r21 17 mmulfx.w r21,r21,r19 18 mshflo.w r21,r63,r21 23 msub.w r21,r19,r19 30 addi r19,-2,r21 31 mulu.l r4,r21,r18 33 shlli r21,15,r21 36 mmacnfx.wl r25,r19,r21 40 mulu.l r25,r21,r19 49 mulu.l r25,r21,r19
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D | strcpy.S | 35 sub r3, r2, r21 36 addi r21, 8, r20 37 ldx.q r0, r21, r5 87 ldx.q r0, r21, r5
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/arch/ia64/lib/ |
D | flush.S | 29 mov r21=1 36 shl r21=r21,r20 // r21: stride size of the i-cache(s) 52 add r24=r21,r24 // we flush "stride size" bytes per iteration 81 mov r21=1 89 shl r21=r21,r20 // r21: stride size of the i-cache(s) 107 add r24=r21,r24 // we flush "stride size" bytes per iteration
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D | ip_fast_csum.S | 43 (p7) ld4 r21=[r15],8 50 add r20=r20,r21 98 ld4 r21=[in1],4 108 add r16=r20,r21
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D | memcpy_mck.S | 41 #define src_pre_l2 r21 172 and r21=-8,tmp 178 add src0=src0,r21 // setting up src pointer 179 add dst0=dst0,r21 // setting up dest pointer 294 shr.u r21=in2,7 // this much cache line 299 cmp.lt p7,p8=1,r21 300 add cnt=-1,r21 362 (p6) or r21=r28,r27 392 EX(.ex_handler, (p6) st8 [dst1]=r21,8) // more than 8 byte to copy 512 shrp r21=r22,r38,shift; /* speculative work */ \ [all …]
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/arch/parisc/kernel/ |
D | pacache.S | 82 LDREG ITLB_SID_STRIDE(%r1), %r21 95 add %r21, %r20, %r20 /* increment space */ 118 add %r21, %r20, %r20 /* increment space */ 125 LDREG DTLB_SID_STRIDE(%r1), %r21 138 add %r21, %r20, %r20 /* increment space */ 161 add %r21, %r20, %r20 /* increment space */ 452 ldd 16(%r25), %r21 459 std %r21, 16(%r26) 462 ldd 48(%r25), %r21 469 std %r21, 48(%r26) [all …]
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D | syscall.S | 131 depdi 0, 31, 32, %r21 182 STREG %r21, TASK_PT_GR21(%r1) 209 stw %r21, -56(%r30) /* 6th argument */ 344 LDREG TASK_PT_GR21(%r1), %r21 349 stw %r21, -56(%r30) /* 6th argument */ 485 LDREGX %r20(%sr2,r28), %r21 /* Scratch use of r21 */ 488 be,n 0(%sr2,%r21) 491 ldo -ENOSYS(%r0),%r21 /* set errno */ 584 mfctl %cr27, %r21 /* Get current thread register */ 585 cmpb,<>,n %r21, %r28, cas_lock /* Called recursive? */ [all …]
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D | sys_parisc32.c | 19 int r22, int r21, int r20) in sys32_unimplemented() argument
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/arch/tile/kernel/ |
D | intvec_64.S | 630 push_reg r21, r52 662 PTREGS_PTR(r21, PTREGS_OFFSET_FLAGS) 674 st r21, r32 693 IRQ_DISABLE(r20, r21) 701 moveli r21, hw2_last(__per_cpu_offset) 704 shl16insli r21, r21, hw1(__per_cpu_offset) 707 shl16insli r21, r21, hw0(__per_cpu_offset) 708 shl3add r20, r20, r21 727 moveli r21, hw2_last(intvec_feedback) 728 shl16insli r21, r21, hw1(intvec_feedback) [all …]
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D | intvec_32.S | 430 push_reg r21, r52 456 moveli r21, lo16(__per_cpu_offset) 459 auli r21, r21, ha16(__per_cpu_offset) 462 s2a r20, r20, r21 478 PTREGS_PTR(r21, PTREGS_OFFSET_FLAGS) 490 sw r21, r32 550 IRQ_DISABLE(r20, r21) 819 IRQ_DISABLE(r20,r21) 867 IRQ_DISABLE(r20, r21) 936 IRQ_DISABLE(r20,r21) [all …]
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/arch/tile/lib/ |
D | atomic_asm_32.S | 136 tns r21, ATOMIC_LOCK_REG_NAME 140 bzt r21, 1b /* branch if lock acquired */ 154 tns r21, ATOMIC_LOCK_REG_NAME 158 bzt r21, 1b /* branch if lock acquired */
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/arch/ia64/kernel/ |
D | ivt.S | 120 shl r21=r16,3 // shift bit 60 into sign bit 123 shr.u r22=r21,3 143 (p6) shr.u r21=r21,PGDIR_SHIFT+PAGE_SHIFT 144 (p7) shr.u r21=r21,PGDIR_SHIFT+PAGE_SHIFT-3 148 cmp.eq p7,p6=0,r21 // unused address bits all zeroes? 174 dep r21=r19,r20,3,(PAGE_SHIFT-3) // r21=pte_offset(pmd,addr) 176 (p7) ld8 r18=[r21] // read *pte 223 ld8 r25=[r21] // read *pte again 341 MOV_FROM_IPSR(p0, r21) 356 extr.u r23=r21,IA64_PSR_CPL0_BIT,2 // extract psr.cpl [all …]
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D | fsys.S | 201 add r21 = IA64_CLKSRC_MMIO_OFFSET,r20 218 ld8 r30 = [r21] // clocksource->mmio_ptr 281 mov r21 = r8 300 (p14) shr.u r21 = r2, 4 303 EX(.fail_efault, st8 [r23] = r21) 401 mov r21=ar.fpsr 520 ld8 r21=[r17] // cumulated utime 527 add r21=r21,r18 // sum utime 530 st8 [r17]=r21 // update utime
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D | entry.S | 179 adds r21=IA64_TASK_THREAD_KSP_OFFSET,in0 193 ld8 sp=[r21] // load kernel stack pointer of new task 287 mov r21=b0 301 st8 [r14]=r21,SW(B1)-SW(B0) // save b0 308 mov r21=ar.lc // I-unit 318 st8 [r15]=r21 // save ar.lc 346 mov r21=pr 349 st8 [r3]=r21 // save predicate registers 378 ld8 r21=[r2],16 // restore b0 413 mov b0=r21 [all …]
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/arch/microblaze/lib/ |
D | uaccess_old.S | 110 4: lwi r21, r6, 0x000C + offset; \ 118 12: swi r21, r5, 0x000C + offset; \ 198 swi r21, r1, 20 221 lwi r21, r1, 20 241 lwi r21, r1, 20
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/arch/alpha/include/uapi/asm/ |
D | ptrace.h | 31 unsigned long r21; member
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/arch/arc/include/uapi/asm/ |
D | ptrace.h | 44 unsigned long r25, r24, r23, r22, r21, r20; member
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/arch/powerpc/boot/ |
D | ppc_asm.h | 50 #define r21 21 macro
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/arch/arc/include/asm/ |
D | unwind.h | 38 unsigned long r21; member 97 PTREGS_INFO(r21), \
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/arch/hexagon/include/uapi/asm/ |
D | user.h | 34 unsigned long r21; member
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/arch/powerpc/crypto/ |
D | aes-spe-regs.h | 32 #define rW5 r21
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