1 #ifndef __gio_defs_h 2 #define __gio_defs_h 3 4 /* 5 * This file is autogenerated from 6 * file: gio.r 7 * 8 * by ../../../tools/rdesc/bin/rdes2c -outfile gio_defs.h gio.r 9 * Any changes here will be lost. 10 * 11 * -*- buffer-read-only: t -*- 12 */ 13 /* Main access macros */ 14 #ifndef REG_RD 15 #define REG_RD( scope, inst, reg ) \ 16 REG_READ( reg_##scope##_##reg, \ 17 (inst) + REG_RD_ADDR_##scope##_##reg ) 18 #endif 19 20 #ifndef REG_WR 21 #define REG_WR( scope, inst, reg, val ) \ 22 REG_WRITE( reg_##scope##_##reg, \ 23 (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) 24 #endif 25 26 #ifndef REG_RD_VECT 27 #define REG_RD_VECT( scope, inst, reg, index ) \ 28 REG_READ( reg_##scope##_##reg, \ 29 (inst) + REG_RD_ADDR_##scope##_##reg + \ 30 (index) * STRIDE_##scope##_##reg ) 31 #endif 32 33 #ifndef REG_WR_VECT 34 #define REG_WR_VECT( scope, inst, reg, index, val ) \ 35 REG_WRITE( reg_##scope##_##reg, \ 36 (inst) + REG_WR_ADDR_##scope##_##reg + \ 37 (index) * STRIDE_##scope##_##reg, (val) ) 38 #endif 39 40 #ifndef REG_RD_INT 41 #define REG_RD_INT( scope, inst, reg ) \ 42 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) 43 #endif 44 45 #ifndef REG_WR_INT 46 #define REG_WR_INT( scope, inst, reg, val ) \ 47 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) 48 #endif 49 50 #ifndef REG_RD_INT_VECT 51 #define REG_RD_INT_VECT( scope, inst, reg, index ) \ 52 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ 53 (index) * STRIDE_##scope##_##reg ) 54 #endif 55 56 #ifndef REG_WR_INT_VECT 57 #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ 58 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ 59 (index) * STRIDE_##scope##_##reg, (val) ) 60 #endif 61 62 #ifndef REG_TYPE_CONV 63 #define REG_TYPE_CONV( type, orgtype, val ) \ 64 ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) 65 #endif 66 67 #ifndef reg_page_size 68 #define reg_page_size 8192 69 #endif 70 71 #ifndef REG_ADDR 72 #define REG_ADDR( scope, inst, reg ) \ 73 ( (inst) + REG_RD_ADDR_##scope##_##reg ) 74 #endif 75 76 #ifndef REG_ADDR_VECT 77 #define REG_ADDR_VECT( scope, inst, reg, index ) \ 78 ( (inst) + REG_RD_ADDR_##scope##_##reg + \ 79 (index) * STRIDE_##scope##_##reg ) 80 #endif 81 82 /* C-code for register scope gio */ 83 84 /* Register r_pa_din, scope gio, type r */ 85 typedef struct { 86 unsigned int data : 32; 87 } reg_gio_r_pa_din; 88 #define REG_RD_ADDR_gio_r_pa_din 0 89 90 /* Register rw_pa_dout, scope gio, type rw */ 91 typedef struct { 92 unsigned int data : 32; 93 } reg_gio_rw_pa_dout; 94 #define REG_RD_ADDR_gio_rw_pa_dout 4 95 #define REG_WR_ADDR_gio_rw_pa_dout 4 96 97 /* Register rw_pa_oe, scope gio, type rw */ 98 typedef struct { 99 unsigned int oe : 32; 100 } reg_gio_rw_pa_oe; 101 #define REG_RD_ADDR_gio_rw_pa_oe 8 102 #define REG_WR_ADDR_gio_rw_pa_oe 8 103 104 /* Register rw_pa_byte0_dout, scope gio, type rw */ 105 typedef struct { 106 unsigned int data : 8; 107 unsigned int dummy1 : 24; 108 } reg_gio_rw_pa_byte0_dout; 109 #define REG_RD_ADDR_gio_rw_pa_byte0_dout 12 110 #define REG_WR_ADDR_gio_rw_pa_byte0_dout 12 111 112 /* Register rw_pa_byte0_oe, scope gio, type rw */ 113 typedef struct { 114 unsigned int oe : 8; 115 unsigned int dummy1 : 24; 116 } reg_gio_rw_pa_byte0_oe; 117 #define REG_RD_ADDR_gio_rw_pa_byte0_oe 16 118 #define REG_WR_ADDR_gio_rw_pa_byte0_oe 16 119 120 /* Register rw_pa_byte1_dout, scope gio, type rw */ 121 typedef struct { 122 unsigned int data : 8; 123 unsigned int dummy1 : 24; 124 } reg_gio_rw_pa_byte1_dout; 125 #define REG_RD_ADDR_gio_rw_pa_byte1_dout 20 126 #define REG_WR_ADDR_gio_rw_pa_byte1_dout 20 127 128 /* Register rw_pa_byte1_oe, scope gio, type rw */ 129 typedef struct { 130 unsigned int oe : 8; 131 unsigned int dummy1 : 24; 132 } reg_gio_rw_pa_byte1_oe; 133 #define REG_RD_ADDR_gio_rw_pa_byte1_oe 24 134 #define REG_WR_ADDR_gio_rw_pa_byte1_oe 24 135 136 /* Register rw_pa_byte2_dout, scope gio, type rw */ 137 typedef struct { 138 unsigned int data : 8; 139 unsigned int dummy1 : 24; 140 } reg_gio_rw_pa_byte2_dout; 141 #define REG_RD_ADDR_gio_rw_pa_byte2_dout 28 142 #define REG_WR_ADDR_gio_rw_pa_byte2_dout 28 143 144 /* Register rw_pa_byte2_oe, scope gio, type rw */ 145 typedef struct { 146 unsigned int oe : 8; 147 unsigned int dummy1 : 24; 148 } reg_gio_rw_pa_byte2_oe; 149 #define REG_RD_ADDR_gio_rw_pa_byte2_oe 32 150 #define REG_WR_ADDR_gio_rw_pa_byte2_oe 32 151 152 /* Register rw_pa_byte3_dout, scope gio, type rw */ 153 typedef struct { 154 unsigned int data : 8; 155 unsigned int dummy1 : 24; 156 } reg_gio_rw_pa_byte3_dout; 157 #define REG_RD_ADDR_gio_rw_pa_byte3_dout 36 158 #define REG_WR_ADDR_gio_rw_pa_byte3_dout 36 159 160 /* Register rw_pa_byte3_oe, scope gio, type rw */ 161 typedef struct { 162 unsigned int oe : 8; 163 unsigned int dummy1 : 24; 164 } reg_gio_rw_pa_byte3_oe; 165 #define REG_RD_ADDR_gio_rw_pa_byte3_oe 40 166 #define REG_WR_ADDR_gio_rw_pa_byte3_oe 40 167 168 /* Register r_pb_din, scope gio, type r */ 169 typedef struct { 170 unsigned int data : 32; 171 } reg_gio_r_pb_din; 172 #define REG_RD_ADDR_gio_r_pb_din 44 173 174 /* Register rw_pb_dout, scope gio, type rw */ 175 typedef struct { 176 unsigned int data : 32; 177 } reg_gio_rw_pb_dout; 178 #define REG_RD_ADDR_gio_rw_pb_dout 48 179 #define REG_WR_ADDR_gio_rw_pb_dout 48 180 181 /* Register rw_pb_oe, scope gio, type rw */ 182 typedef struct { 183 unsigned int oe : 32; 184 } reg_gio_rw_pb_oe; 185 #define REG_RD_ADDR_gio_rw_pb_oe 52 186 #define REG_WR_ADDR_gio_rw_pb_oe 52 187 188 /* Register rw_pb_byte0_dout, scope gio, type rw */ 189 typedef struct { 190 unsigned int data : 8; 191 unsigned int dummy1 : 24; 192 } reg_gio_rw_pb_byte0_dout; 193 #define REG_RD_ADDR_gio_rw_pb_byte0_dout 56 194 #define REG_WR_ADDR_gio_rw_pb_byte0_dout 56 195 196 /* Register rw_pb_byte0_oe, scope gio, type rw */ 197 typedef struct { 198 unsigned int oe : 8; 199 unsigned int dummy1 : 24; 200 } reg_gio_rw_pb_byte0_oe; 201 #define REG_RD_ADDR_gio_rw_pb_byte0_oe 60 202 #define REG_WR_ADDR_gio_rw_pb_byte0_oe 60 203 204 /* Register rw_pb_byte1_dout, scope gio, type rw */ 205 typedef struct { 206 unsigned int data : 8; 207 unsigned int dummy1 : 24; 208 } reg_gio_rw_pb_byte1_dout; 209 #define REG_RD_ADDR_gio_rw_pb_byte1_dout 64 210 #define REG_WR_ADDR_gio_rw_pb_byte1_dout 64 211 212 /* Register rw_pb_byte1_oe, scope gio, type rw */ 213 typedef struct { 214 unsigned int oe : 8; 215 unsigned int dummy1 : 24; 216 } reg_gio_rw_pb_byte1_oe; 217 #define REG_RD_ADDR_gio_rw_pb_byte1_oe 68 218 #define REG_WR_ADDR_gio_rw_pb_byte1_oe 68 219 220 /* Register rw_pb_byte2_dout, scope gio, type rw */ 221 typedef struct { 222 unsigned int data : 8; 223 unsigned int dummy1 : 24; 224 } reg_gio_rw_pb_byte2_dout; 225 #define REG_RD_ADDR_gio_rw_pb_byte2_dout 72 226 #define REG_WR_ADDR_gio_rw_pb_byte2_dout 72 227 228 /* Register rw_pb_byte2_oe, scope gio, type rw */ 229 typedef struct { 230 unsigned int oe : 8; 231 unsigned int dummy1 : 24; 232 } reg_gio_rw_pb_byte2_oe; 233 #define REG_RD_ADDR_gio_rw_pb_byte2_oe 76 234 #define REG_WR_ADDR_gio_rw_pb_byte2_oe 76 235 236 /* Register rw_pb_byte3_dout, scope gio, type rw */ 237 typedef struct { 238 unsigned int data : 8; 239 unsigned int dummy1 : 24; 240 } reg_gio_rw_pb_byte3_dout; 241 #define REG_RD_ADDR_gio_rw_pb_byte3_dout 80 242 #define REG_WR_ADDR_gio_rw_pb_byte3_dout 80 243 244 /* Register rw_pb_byte3_oe, scope gio, type rw */ 245 typedef struct { 246 unsigned int oe : 8; 247 unsigned int dummy1 : 24; 248 } reg_gio_rw_pb_byte3_oe; 249 #define REG_RD_ADDR_gio_rw_pb_byte3_oe 84 250 #define REG_WR_ADDR_gio_rw_pb_byte3_oe 84 251 252 /* Register r_pc_din, scope gio, type r */ 253 typedef struct { 254 unsigned int data : 16; 255 unsigned int dummy1 : 16; 256 } reg_gio_r_pc_din; 257 #define REG_RD_ADDR_gio_r_pc_din 88 258 259 /* Register rw_pc_dout, scope gio, type rw */ 260 typedef struct { 261 unsigned int data : 16; 262 unsigned int dummy1 : 16; 263 } reg_gio_rw_pc_dout; 264 #define REG_RD_ADDR_gio_rw_pc_dout 92 265 #define REG_WR_ADDR_gio_rw_pc_dout 92 266 267 /* Register rw_pc_oe, scope gio, type rw */ 268 typedef struct { 269 unsigned int oe : 16; 270 unsigned int dummy1 : 16; 271 } reg_gio_rw_pc_oe; 272 #define REG_RD_ADDR_gio_rw_pc_oe 96 273 #define REG_WR_ADDR_gio_rw_pc_oe 96 274 275 /* Register rw_pc_byte0_dout, scope gio, type rw */ 276 typedef struct { 277 unsigned int data : 8; 278 unsigned int dummy1 : 24; 279 } reg_gio_rw_pc_byte0_dout; 280 #define REG_RD_ADDR_gio_rw_pc_byte0_dout 100 281 #define REG_WR_ADDR_gio_rw_pc_byte0_dout 100 282 283 /* Register rw_pc_byte0_oe, scope gio, type rw */ 284 typedef struct { 285 unsigned int oe : 8; 286 unsigned int dummy1 : 24; 287 } reg_gio_rw_pc_byte0_oe; 288 #define REG_RD_ADDR_gio_rw_pc_byte0_oe 104 289 #define REG_WR_ADDR_gio_rw_pc_byte0_oe 104 290 291 /* Register rw_pc_byte1_dout, scope gio, type rw */ 292 typedef struct { 293 unsigned int data : 8; 294 unsigned int dummy1 : 24; 295 } reg_gio_rw_pc_byte1_dout; 296 #define REG_RD_ADDR_gio_rw_pc_byte1_dout 108 297 #define REG_WR_ADDR_gio_rw_pc_byte1_dout 108 298 299 /* Register rw_pc_byte1_oe, scope gio, type rw */ 300 typedef struct { 301 unsigned int oe : 8; 302 unsigned int dummy1 : 24; 303 } reg_gio_rw_pc_byte1_oe; 304 #define REG_RD_ADDR_gio_rw_pc_byte1_oe 112 305 #define REG_WR_ADDR_gio_rw_pc_byte1_oe 112 306 307 /* Register r_pd_din, scope gio, type r */ 308 typedef struct { 309 unsigned int data : 32; 310 } reg_gio_r_pd_din; 311 #define REG_RD_ADDR_gio_r_pd_din 116 312 313 /* Register rw_intr_cfg, scope gio, type rw */ 314 typedef struct { 315 unsigned int intr0 : 3; 316 unsigned int intr1 : 3; 317 unsigned int intr2 : 3; 318 unsigned int intr3 : 3; 319 unsigned int intr4 : 3; 320 unsigned int intr5 : 3; 321 unsigned int intr6 : 3; 322 unsigned int intr7 : 3; 323 unsigned int dummy1 : 8; 324 } reg_gio_rw_intr_cfg; 325 #define REG_RD_ADDR_gio_rw_intr_cfg 120 326 #define REG_WR_ADDR_gio_rw_intr_cfg 120 327 328 /* Register rw_intr_pins, scope gio, type rw */ 329 typedef struct { 330 unsigned int intr0 : 4; 331 unsigned int intr1 : 4; 332 unsigned int intr2 : 4; 333 unsigned int intr3 : 4; 334 unsigned int intr4 : 4; 335 unsigned int intr5 : 4; 336 unsigned int intr6 : 4; 337 unsigned int intr7 : 4; 338 } reg_gio_rw_intr_pins; 339 #define REG_RD_ADDR_gio_rw_intr_pins 124 340 #define REG_WR_ADDR_gio_rw_intr_pins 124 341 342 /* Register rw_intr_mask, scope gio, type rw */ 343 typedef struct { 344 unsigned int intr0 : 1; 345 unsigned int intr1 : 1; 346 unsigned int intr2 : 1; 347 unsigned int intr3 : 1; 348 unsigned int intr4 : 1; 349 unsigned int intr5 : 1; 350 unsigned int intr6 : 1; 351 unsigned int intr7 : 1; 352 unsigned int i2c0_done : 1; 353 unsigned int i2c1_done : 1; 354 unsigned int dummy1 : 22; 355 } reg_gio_rw_intr_mask; 356 #define REG_RD_ADDR_gio_rw_intr_mask 128 357 #define REG_WR_ADDR_gio_rw_intr_mask 128 358 359 /* Register rw_ack_intr, scope gio, type rw */ 360 typedef struct { 361 unsigned int intr0 : 1; 362 unsigned int intr1 : 1; 363 unsigned int intr2 : 1; 364 unsigned int intr3 : 1; 365 unsigned int intr4 : 1; 366 unsigned int intr5 : 1; 367 unsigned int intr6 : 1; 368 unsigned int intr7 : 1; 369 unsigned int i2c0_done : 1; 370 unsigned int i2c1_done : 1; 371 unsigned int dummy1 : 22; 372 } reg_gio_rw_ack_intr; 373 #define REG_RD_ADDR_gio_rw_ack_intr 132 374 #define REG_WR_ADDR_gio_rw_ack_intr 132 375 376 /* Register r_intr, scope gio, type r */ 377 typedef struct { 378 unsigned int intr0 : 1; 379 unsigned int intr1 : 1; 380 unsigned int intr2 : 1; 381 unsigned int intr3 : 1; 382 unsigned int intr4 : 1; 383 unsigned int intr5 : 1; 384 unsigned int intr6 : 1; 385 unsigned int intr7 : 1; 386 unsigned int i2c0_done : 1; 387 unsigned int i2c1_done : 1; 388 unsigned int dummy1 : 22; 389 } reg_gio_r_intr; 390 #define REG_RD_ADDR_gio_r_intr 136 391 392 /* Register r_masked_intr, scope gio, type r */ 393 typedef struct { 394 unsigned int intr0 : 1; 395 unsigned int intr1 : 1; 396 unsigned int intr2 : 1; 397 unsigned int intr3 : 1; 398 unsigned int intr4 : 1; 399 unsigned int intr5 : 1; 400 unsigned int intr6 : 1; 401 unsigned int intr7 : 1; 402 unsigned int i2c0_done : 1; 403 unsigned int i2c1_done : 1; 404 unsigned int dummy1 : 22; 405 } reg_gio_r_masked_intr; 406 #define REG_RD_ADDR_gio_r_masked_intr 140 407 408 /* Register rw_i2c0_start, scope gio, type rw */ 409 typedef struct { 410 unsigned int run : 1; 411 unsigned int dummy1 : 31; 412 } reg_gio_rw_i2c0_start; 413 #define REG_RD_ADDR_gio_rw_i2c0_start 144 414 #define REG_WR_ADDR_gio_rw_i2c0_start 144 415 416 /* Register rw_i2c0_cfg, scope gio, type rw */ 417 typedef struct { 418 unsigned int en : 1; 419 unsigned int bit_order : 1; 420 unsigned int scl_io : 1; 421 unsigned int scl_inv : 1; 422 unsigned int sda_io : 1; 423 unsigned int sda_idle : 1; 424 unsigned int dummy1 : 26; 425 } reg_gio_rw_i2c0_cfg; 426 #define REG_RD_ADDR_gio_rw_i2c0_cfg 148 427 #define REG_WR_ADDR_gio_rw_i2c0_cfg 148 428 429 /* Register rw_i2c0_ctrl, scope gio, type rw */ 430 typedef struct { 431 unsigned int trf_bits : 6; 432 unsigned int switch_dir : 6; 433 unsigned int extra_start : 3; 434 unsigned int early_end : 1; 435 unsigned int start_stop : 1; 436 unsigned int ack_dir0 : 1; 437 unsigned int ack_dir1 : 1; 438 unsigned int ack_dir2 : 1; 439 unsigned int ack_dir3 : 1; 440 unsigned int ack_dir4 : 1; 441 unsigned int ack_dir5 : 1; 442 unsigned int ack_bit : 1; 443 unsigned int start_bit : 1; 444 unsigned int freq : 2; 445 unsigned int dummy1 : 5; 446 } reg_gio_rw_i2c0_ctrl; 447 #define REG_RD_ADDR_gio_rw_i2c0_ctrl 152 448 #define REG_WR_ADDR_gio_rw_i2c0_ctrl 152 449 450 /* Register rw_i2c0_data, scope gio, type rw */ 451 typedef struct { 452 unsigned int data0 : 8; 453 unsigned int data1 : 8; 454 unsigned int data2 : 8; 455 unsigned int data3 : 8; 456 } reg_gio_rw_i2c0_data; 457 #define REG_RD_ADDR_gio_rw_i2c0_data 156 458 #define REG_WR_ADDR_gio_rw_i2c0_data 156 459 460 /* Register rw_i2c0_data2, scope gio, type rw */ 461 typedef struct { 462 unsigned int data4 : 8; 463 unsigned int data5 : 8; 464 unsigned int start_val : 6; 465 unsigned int ack_val : 6; 466 unsigned int dummy1 : 4; 467 } reg_gio_rw_i2c0_data2; 468 #define REG_RD_ADDR_gio_rw_i2c0_data2 160 469 #define REG_WR_ADDR_gio_rw_i2c0_data2 160 470 471 /* Register rw_i2c1_start, scope gio, type rw */ 472 typedef struct { 473 unsigned int run : 1; 474 unsigned int dummy1 : 31; 475 } reg_gio_rw_i2c1_start; 476 #define REG_RD_ADDR_gio_rw_i2c1_start 164 477 #define REG_WR_ADDR_gio_rw_i2c1_start 164 478 479 /* Register rw_i2c1_cfg, scope gio, type rw */ 480 typedef struct { 481 unsigned int en : 1; 482 unsigned int bit_order : 1; 483 unsigned int scl_io : 1; 484 unsigned int scl_inv : 1; 485 unsigned int sda0_io : 1; 486 unsigned int sda0_idle : 1; 487 unsigned int sda1_io : 1; 488 unsigned int sda1_idle : 1; 489 unsigned int sda2_io : 1; 490 unsigned int sda2_idle : 1; 491 unsigned int sda3_io : 1; 492 unsigned int sda3_idle : 1; 493 unsigned int sda_sel : 2; 494 unsigned int sen_idle : 1; 495 unsigned int sen_inv : 1; 496 unsigned int sen_sel : 2; 497 unsigned int dummy1 : 14; 498 } reg_gio_rw_i2c1_cfg; 499 #define REG_RD_ADDR_gio_rw_i2c1_cfg 168 500 #define REG_WR_ADDR_gio_rw_i2c1_cfg 168 501 502 /* Register rw_i2c1_ctrl, scope gio, type rw */ 503 typedef struct { 504 unsigned int trf_bits : 6; 505 unsigned int switch_dir : 6; 506 unsigned int extra_start : 3; 507 unsigned int early_end : 1; 508 unsigned int start_stop : 1; 509 unsigned int ack_dir0 : 1; 510 unsigned int ack_dir1 : 1; 511 unsigned int ack_dir2 : 1; 512 unsigned int ack_dir3 : 1; 513 unsigned int ack_dir4 : 1; 514 unsigned int ack_dir5 : 1; 515 unsigned int ack_bit : 1; 516 unsigned int start_bit : 1; 517 unsigned int freq : 2; 518 unsigned int dummy1 : 5; 519 } reg_gio_rw_i2c1_ctrl; 520 #define REG_RD_ADDR_gio_rw_i2c1_ctrl 172 521 #define REG_WR_ADDR_gio_rw_i2c1_ctrl 172 522 523 /* Register rw_i2c1_data, scope gio, type rw */ 524 typedef struct { 525 unsigned int data0 : 8; 526 unsigned int data1 : 8; 527 unsigned int data2 : 8; 528 unsigned int data3 : 8; 529 } reg_gio_rw_i2c1_data; 530 #define REG_RD_ADDR_gio_rw_i2c1_data 176 531 #define REG_WR_ADDR_gio_rw_i2c1_data 176 532 533 /* Register rw_i2c1_data2, scope gio, type rw */ 534 typedef struct { 535 unsigned int data4 : 8; 536 unsigned int data5 : 8; 537 unsigned int start_val : 6; 538 unsigned int ack_val : 6; 539 unsigned int dummy1 : 4; 540 } reg_gio_rw_i2c1_data2; 541 #define REG_RD_ADDR_gio_rw_i2c1_data2 180 542 #define REG_WR_ADDR_gio_rw_i2c1_data2 180 543 544 /* Register r_ppwm_stat, scope gio, type r */ 545 typedef struct { 546 unsigned int freq : 2; 547 unsigned int dummy1 : 30; 548 } reg_gio_r_ppwm_stat; 549 #define REG_RD_ADDR_gio_r_ppwm_stat 184 550 551 /* Register rw_ppwm_data, scope gio, type rw */ 552 typedef struct { 553 unsigned int data : 8; 554 unsigned int dummy1 : 24; 555 } reg_gio_rw_ppwm_data; 556 #define REG_RD_ADDR_gio_rw_ppwm_data 188 557 #define REG_WR_ADDR_gio_rw_ppwm_data 188 558 559 /* Register rw_pwm0_ctrl, scope gio, type rw */ 560 typedef struct { 561 unsigned int mode : 2; 562 unsigned int ccd_override : 1; 563 unsigned int ccd_val : 1; 564 unsigned int dummy1 : 28; 565 } reg_gio_rw_pwm0_ctrl; 566 #define REG_RD_ADDR_gio_rw_pwm0_ctrl 192 567 #define REG_WR_ADDR_gio_rw_pwm0_ctrl 192 568 569 /* Register rw_pwm0_var, scope gio, type rw */ 570 typedef struct { 571 unsigned int lo : 13; 572 unsigned int hi : 13; 573 unsigned int dummy1 : 6; 574 } reg_gio_rw_pwm0_var; 575 #define REG_RD_ADDR_gio_rw_pwm0_var 196 576 #define REG_WR_ADDR_gio_rw_pwm0_var 196 577 578 /* Register rw_pwm0_data, scope gio, type rw */ 579 typedef struct { 580 unsigned int data : 8; 581 unsigned int dummy1 : 24; 582 } reg_gio_rw_pwm0_data; 583 #define REG_RD_ADDR_gio_rw_pwm0_data 200 584 #define REG_WR_ADDR_gio_rw_pwm0_data 200 585 586 /* Register rw_pwm1_ctrl, scope gio, type rw */ 587 typedef struct { 588 unsigned int mode : 2; 589 unsigned int ccd_override : 1; 590 unsigned int ccd_val : 1; 591 unsigned int dummy1 : 28; 592 } reg_gio_rw_pwm1_ctrl; 593 #define REG_RD_ADDR_gio_rw_pwm1_ctrl 204 594 #define REG_WR_ADDR_gio_rw_pwm1_ctrl 204 595 596 /* Register rw_pwm1_var, scope gio, type rw */ 597 typedef struct { 598 unsigned int lo : 13; 599 unsigned int hi : 13; 600 unsigned int dummy1 : 6; 601 } reg_gio_rw_pwm1_var; 602 #define REG_RD_ADDR_gio_rw_pwm1_var 208 603 #define REG_WR_ADDR_gio_rw_pwm1_var 208 604 605 /* Register rw_pwm1_data, scope gio, type rw */ 606 typedef struct { 607 unsigned int data : 8; 608 unsigned int dummy1 : 24; 609 } reg_gio_rw_pwm1_data; 610 #define REG_RD_ADDR_gio_rw_pwm1_data 212 611 #define REG_WR_ADDR_gio_rw_pwm1_data 212 612 613 /* Register rw_pwm2_ctrl, scope gio, type rw */ 614 typedef struct { 615 unsigned int mode : 2; 616 unsigned int ccd_override : 1; 617 unsigned int ccd_val : 1; 618 unsigned int dummy1 : 28; 619 } reg_gio_rw_pwm2_ctrl; 620 #define REG_RD_ADDR_gio_rw_pwm2_ctrl 216 621 #define REG_WR_ADDR_gio_rw_pwm2_ctrl 216 622 623 /* Register rw_pwm2_var, scope gio, type rw */ 624 typedef struct { 625 unsigned int lo : 13; 626 unsigned int hi : 13; 627 unsigned int dummy1 : 6; 628 } reg_gio_rw_pwm2_var; 629 #define REG_RD_ADDR_gio_rw_pwm2_var 220 630 #define REG_WR_ADDR_gio_rw_pwm2_var 220 631 632 /* Register rw_pwm2_data, scope gio, type rw */ 633 typedef struct { 634 unsigned int data : 8; 635 unsigned int dummy1 : 24; 636 } reg_gio_rw_pwm2_data; 637 #define REG_RD_ADDR_gio_rw_pwm2_data 224 638 #define REG_WR_ADDR_gio_rw_pwm2_data 224 639 640 /* Register rw_pwm_in_cfg, scope gio, type rw */ 641 typedef struct { 642 unsigned int pin : 3; 643 unsigned int dummy1 : 29; 644 } reg_gio_rw_pwm_in_cfg; 645 #define REG_RD_ADDR_gio_rw_pwm_in_cfg 228 646 #define REG_WR_ADDR_gio_rw_pwm_in_cfg 228 647 648 /* Register r_pwm_in_lo, scope gio, type r */ 649 typedef struct { 650 unsigned int data : 32; 651 } reg_gio_r_pwm_in_lo; 652 #define REG_RD_ADDR_gio_r_pwm_in_lo 232 653 654 /* Register r_pwm_in_hi, scope gio, type r */ 655 typedef struct { 656 unsigned int data : 32; 657 } reg_gio_r_pwm_in_hi; 658 #define REG_RD_ADDR_gio_r_pwm_in_hi 236 659 660 /* Register r_pwm_in_cnt, scope gio, type r */ 661 typedef struct { 662 unsigned int data : 32; 663 } reg_gio_r_pwm_in_cnt; 664 #define REG_RD_ADDR_gio_r_pwm_in_cnt 240 665 666 667 /* Constants */ 668 enum { 669 regk_gio_anyedge = 0x00000007, 670 regk_gio_f100k = 0x00000000, 671 regk_gio_f1562 = 0x00000000, 672 regk_gio_f195 = 0x00000003, 673 regk_gio_f1m = 0x00000002, 674 regk_gio_f390 = 0x00000002, 675 regk_gio_f400k = 0x00000001, 676 regk_gio_f5m = 0x00000003, 677 regk_gio_f781 = 0x00000001, 678 regk_gio_hi = 0x00000001, 679 regk_gio_in = 0x00000000, 680 regk_gio_intr_pa0 = 0x00000000, 681 regk_gio_intr_pa1 = 0x00000000, 682 regk_gio_intr_pa10 = 0x00000001, 683 regk_gio_intr_pa11 = 0x00000001, 684 regk_gio_intr_pa12 = 0x00000001, 685 regk_gio_intr_pa13 = 0x00000001, 686 regk_gio_intr_pa14 = 0x00000001, 687 regk_gio_intr_pa15 = 0x00000001, 688 regk_gio_intr_pa16 = 0x00000002, 689 regk_gio_intr_pa17 = 0x00000002, 690 regk_gio_intr_pa18 = 0x00000002, 691 regk_gio_intr_pa19 = 0x00000002, 692 regk_gio_intr_pa2 = 0x00000000, 693 regk_gio_intr_pa20 = 0x00000002, 694 regk_gio_intr_pa21 = 0x00000002, 695 regk_gio_intr_pa22 = 0x00000002, 696 regk_gio_intr_pa23 = 0x00000002, 697 regk_gio_intr_pa24 = 0x00000003, 698 regk_gio_intr_pa25 = 0x00000003, 699 regk_gio_intr_pa26 = 0x00000003, 700 regk_gio_intr_pa27 = 0x00000003, 701 regk_gio_intr_pa28 = 0x00000003, 702 regk_gio_intr_pa29 = 0x00000003, 703 regk_gio_intr_pa3 = 0x00000000, 704 regk_gio_intr_pa30 = 0x00000003, 705 regk_gio_intr_pa31 = 0x00000003, 706 regk_gio_intr_pa4 = 0x00000000, 707 regk_gio_intr_pa5 = 0x00000000, 708 regk_gio_intr_pa6 = 0x00000000, 709 regk_gio_intr_pa7 = 0x00000000, 710 regk_gio_intr_pa8 = 0x00000001, 711 regk_gio_intr_pa9 = 0x00000001, 712 regk_gio_intr_pb0 = 0x00000004, 713 regk_gio_intr_pb1 = 0x00000004, 714 regk_gio_intr_pb10 = 0x00000005, 715 regk_gio_intr_pb11 = 0x00000005, 716 regk_gio_intr_pb12 = 0x00000005, 717 regk_gio_intr_pb13 = 0x00000005, 718 regk_gio_intr_pb14 = 0x00000005, 719 regk_gio_intr_pb15 = 0x00000005, 720 regk_gio_intr_pb16 = 0x00000006, 721 regk_gio_intr_pb17 = 0x00000006, 722 regk_gio_intr_pb18 = 0x00000006, 723 regk_gio_intr_pb19 = 0x00000006, 724 regk_gio_intr_pb2 = 0x00000004, 725 regk_gio_intr_pb20 = 0x00000006, 726 regk_gio_intr_pb21 = 0x00000006, 727 regk_gio_intr_pb22 = 0x00000006, 728 regk_gio_intr_pb23 = 0x00000006, 729 regk_gio_intr_pb24 = 0x00000007, 730 regk_gio_intr_pb25 = 0x00000007, 731 regk_gio_intr_pb26 = 0x00000007, 732 regk_gio_intr_pb27 = 0x00000007, 733 regk_gio_intr_pb28 = 0x00000007, 734 regk_gio_intr_pb29 = 0x00000007, 735 regk_gio_intr_pb3 = 0x00000004, 736 regk_gio_intr_pb30 = 0x00000007, 737 regk_gio_intr_pb31 = 0x00000007, 738 regk_gio_intr_pb4 = 0x00000004, 739 regk_gio_intr_pb5 = 0x00000004, 740 regk_gio_intr_pb6 = 0x00000004, 741 regk_gio_intr_pb7 = 0x00000004, 742 regk_gio_intr_pb8 = 0x00000005, 743 regk_gio_intr_pb9 = 0x00000005, 744 regk_gio_intr_pc0 = 0x00000008, 745 regk_gio_intr_pc1 = 0x00000008, 746 regk_gio_intr_pc10 = 0x00000009, 747 regk_gio_intr_pc11 = 0x00000009, 748 regk_gio_intr_pc12 = 0x00000009, 749 regk_gio_intr_pc13 = 0x00000009, 750 regk_gio_intr_pc14 = 0x00000009, 751 regk_gio_intr_pc15 = 0x00000009, 752 regk_gio_intr_pc2 = 0x00000008, 753 regk_gio_intr_pc3 = 0x00000008, 754 regk_gio_intr_pc4 = 0x00000008, 755 regk_gio_intr_pc5 = 0x00000008, 756 regk_gio_intr_pc6 = 0x00000008, 757 regk_gio_intr_pc7 = 0x00000008, 758 regk_gio_intr_pc8 = 0x00000009, 759 regk_gio_intr_pc9 = 0x00000009, 760 regk_gio_intr_pd0 = 0x0000000c, 761 regk_gio_intr_pd1 = 0x0000000c, 762 regk_gio_intr_pd10 = 0x0000000d, 763 regk_gio_intr_pd11 = 0x0000000d, 764 regk_gio_intr_pd12 = 0x0000000d, 765 regk_gio_intr_pd13 = 0x0000000d, 766 regk_gio_intr_pd14 = 0x0000000d, 767 regk_gio_intr_pd15 = 0x0000000d, 768 regk_gio_intr_pd16 = 0x0000000e, 769 regk_gio_intr_pd17 = 0x0000000e, 770 regk_gio_intr_pd18 = 0x0000000e, 771 regk_gio_intr_pd19 = 0x0000000e, 772 regk_gio_intr_pd2 = 0x0000000c, 773 regk_gio_intr_pd20 = 0x0000000e, 774 regk_gio_intr_pd21 = 0x0000000e, 775 regk_gio_intr_pd22 = 0x0000000e, 776 regk_gio_intr_pd23 = 0x0000000e, 777 regk_gio_intr_pd24 = 0x0000000f, 778 regk_gio_intr_pd25 = 0x0000000f, 779 regk_gio_intr_pd26 = 0x0000000f, 780 regk_gio_intr_pd27 = 0x0000000f, 781 regk_gio_intr_pd28 = 0x0000000f, 782 regk_gio_intr_pd29 = 0x0000000f, 783 regk_gio_intr_pd3 = 0x0000000c, 784 regk_gio_intr_pd30 = 0x0000000f, 785 regk_gio_intr_pd31 = 0x0000000f, 786 regk_gio_intr_pd4 = 0x0000000c, 787 regk_gio_intr_pd5 = 0x0000000c, 788 regk_gio_intr_pd6 = 0x0000000c, 789 regk_gio_intr_pd7 = 0x0000000c, 790 regk_gio_intr_pd8 = 0x0000000d, 791 regk_gio_intr_pd9 = 0x0000000d, 792 regk_gio_lo = 0x00000002, 793 regk_gio_lsb = 0x00000000, 794 regk_gio_msb = 0x00000001, 795 regk_gio_negedge = 0x00000006, 796 regk_gio_no = 0x00000000, 797 regk_gio_no_switch = 0x0000003f, 798 regk_gio_none = 0x00000007, 799 regk_gio_off = 0x00000000, 800 regk_gio_opendrain = 0x00000000, 801 regk_gio_out = 0x00000001, 802 regk_gio_posedge = 0x00000005, 803 regk_gio_pwm_hfp = 0x00000002, 804 regk_gio_pwm_pa0 = 0x00000001, 805 regk_gio_pwm_pa19 = 0x00000004, 806 regk_gio_pwm_pa6 = 0x00000002, 807 regk_gio_pwm_pa7 = 0x00000003, 808 regk_gio_pwm_pb26 = 0x00000005, 809 regk_gio_pwm_pd23 = 0x00000006, 810 regk_gio_pwm_pd31 = 0x00000007, 811 regk_gio_pwm_std = 0x00000001, 812 regk_gio_pwm_var = 0x00000003, 813 regk_gio_rw_i2c0_cfg_default = 0x00000020, 814 regk_gio_rw_i2c0_ctrl_default = 0x00010000, 815 regk_gio_rw_i2c0_start_default = 0x00000000, 816 regk_gio_rw_i2c1_cfg_default = 0x00000aa0, 817 regk_gio_rw_i2c1_ctrl_default = 0x00010000, 818 regk_gio_rw_i2c1_start_default = 0x00000000, 819 regk_gio_rw_intr_cfg_default = 0x00000000, 820 regk_gio_rw_intr_mask_default = 0x00000000, 821 regk_gio_rw_pa_oe_default = 0x00000000, 822 regk_gio_rw_pb_oe_default = 0x00000000, 823 regk_gio_rw_pc_oe_default = 0x00000000, 824 regk_gio_rw_ppwm_data_default = 0x00000000, 825 regk_gio_rw_pwm0_ctrl_default = 0x00000000, 826 regk_gio_rw_pwm1_ctrl_default = 0x00000000, 827 regk_gio_rw_pwm2_ctrl_default = 0x00000000, 828 regk_gio_rw_pwm_in_cfg_default = 0x00000000, 829 regk_gio_sda0 = 0x00000000, 830 regk_gio_sda1 = 0x00000001, 831 regk_gio_sda2 = 0x00000002, 832 regk_gio_sda3 = 0x00000003, 833 regk_gio_sen = 0x00000000, 834 regk_gio_set = 0x00000003, 835 regk_gio_yes = 0x00000001 836 }; 837 #endif /* __gio_defs_h */ 838