Home
last modified time | relevance | path

Searched refs:rsr (Results 1 – 11 of 11) sorted by relevance

/arch/xtensa/variants/dc232b/include/variant/
Dtie-asm.h41 rsr \at1, ACCLO // MAC16 accumulator
42 rsr \at2, ACCHI
49 rsr \at1, M0 // MAC16 registers
50 rsr \at2, M1
53 rsr \at1, M2
54 rsr \at2, M3
61 rsr \at1, SCOMPARE1 // conditional store option
/arch/xtensa/variants/de212/include/variant/
Dtie-asm.h81 rsr.ACCLO \at1 // MAC16 option
83 rsr.ACCHI \at1 // MAC16 option
93 rsr.SCOMPARE1 \at1 // conditional store option
95 rsr.M0 \at1 // MAC16 option
97 rsr.M1 \at1 // MAC16 option
99 rsr.M2 \at1 // MAC16 option
101 rsr.M3 \at1 // MAC16 option
/arch/xtensa/kernel/
Dentry.S81 rsr \flags, ps
88 rsr \flags, ps
133 rsr a0, depc
146 rsr a3, sar
159 rsr a2, windowbase
160 rsr a3, windowstart
231 rsr a2, sar # original WINDOWBASE
279 rsr a0, depc # get a2
291 rsr a3, sar
299 rsr a2, windowbase # don't need to save these, we only
[all …]
Dvectors.S77 rsr a0, exccause # retrieve exception cause
104 rsr a0, exccause # retrieve exception cause
219 rsr a2, ps
259 rsr a0, ps
269 rsr a0, exccause
286 rsr a3, exccause
305 rsr a3, excsave1
339 rsr a0, exccause
425 rsr a0, ps
427 rsr a2, windowbase
[all …]
Dalign.S174 rsr a0, depc
178 rsr a3, excsave1
184 rsr a0, sar
185 rsr a8, excvaddr # load unaligned memory address
204 rsr a7, epc1 # load exception address
325 rsr a3, excsave1
338 rsr a0, ps
413 rsr a4, lend # check if we reached LEND
415 rsr a4, lcount # and LCOUNT != 0
418 rsr a7, lbeg # set PC to LBEGIN
[all …]
Dcoprocessor.S249 rsr a3, sar
253 rsr a2, depc
266 rsr a3, exccause
273 rsr a0, cpenable
309 2: rsr a3, exccause
Dhead.S90 rsr a2, excsave1
213 rsr a2, prid
329 rsr a0, prid
/arch/xtensa/variants/dc233c/include/variant/
Dtie-asm.h92 rsr \at1, ACCLO // MAC16 option
94 rsr \at1, ACCHI // MAC16 option
104 rsr \at1, M0 // MAC16 option
106 rsr \at1, M1 // MAC16 option
108 rsr \at1, M2 // MAC16 option
110 rsr \at1, M3 // MAC16 option
112 rsr \at1, SCOMPARE1 // conditional store option
/arch/powerpc/include/asm/
Dmpc5121.h17 u32 rsr; /* Reset Status Register */ member
/arch/xtensa/boot/boot-redboot/
Dbootstrap.S57 rsr a5, windowbase
/arch/blackfin/include/asm/
Dbfin_serial.h229 u32 rsr; member