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/arch/unicore32/kernel/
Ddebug-macro.S17 .macro put_word_ocd, rd, rx=r16 argument
18 1001: movc \rx, p1.c0, #0
19 cand.a \rx, #2
26 .macro addruart, rx argument
29 .macro senduart, rd, rx argument
30 put_word_ocd \rd, \rx
33 .macro busyuart, rd, rx argument
36 .macro waituart, rd, rx argument
47 .macro addruart,rx argument
48 mrc p0, #0, \rx, c1, c0
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/arch/arm/include/debug/
Dicedcc.S19 .macro senduart, rd, rx argument
23 .macro busyuart, rd, rx argument
25 mrc p14, 0, \rx, c0, c1, 0
26 tst \rx, #0x20000000
30 .macro waituart, rd, rx argument
35 mrc p14, 0, \rx, c0, c1, 0
36 tst \rx, #0x20000000
43 .macro senduart, rd, rx argument
47 .macro busyuart, rd, rx argument
49 mrc p14, 0, \rx, c14, c0, 0
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Dsamsung.S16 .macro fifo_level_s5pv210 rd, rx argument
17 ldr \rd, [\rx, # S3C2410_UFSTAT]
21 .macro fifo_full_s5pv210 rd, rx argument
22 ldr \rd, [\rx, # S3C2410_UFSTAT]
29 .macro fifo_level_s3c2440 rd, rx argument
30 ldr \rd, [\rx, # S3C2410_UFSTAT]
38 .macro fifo_full_s3c2440 rd, rx argument
39 ldr \rd, [\rx, # S3C2410_UFSTAT]
47 .macro senduart,rd,rx argument
48 strb \rd, [\rx, # S3C2410_UTXH]
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D8250.S18 .macro store, rd, rx:vararg
20 str \rd, \rx
24 .macro load, rd, rx:vararg
25 ldr \rd, \rx
29 .macro store, rd, rx:vararg
30 strb \rd, \rx
33 .macro load, rd, rx:vararg
34 ldrb \rd, \rx
40 .macro senduart,rd,rx argument
41 store \rd, [\rx, #UART_TX << UART_SHIFT]
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Defm32.S19 .macro addruart, rx, tmp, tmp2
20 ldr \rx, =(CONFIG_DEBUG_UART_PHYS)
28 str \tmp, [\rx, #UARTn_CMD]
31 .macro senduart,rd,rx argument
32 strb \rd, [\rx, #UARTn_TXDATA]
35 .macro waituart,rd,rx argument
36 1001: ldr \rd, [\rx, #UARTn_STATUS]
41 .macro busyuart,rd,rx argument
42 1001: ldr \rd, [\rx, UARTn_STATUS]
Drenesas-scif.S35 .macro waituart, rd, rx argument
36 1001: ldrh \rd, [\rx, #FSR]
41 .macro senduart, rd, rx argument
42 strb \rd, [\rx, #FTDR]
43 ldrh \rd, [\rx, #FSR]
45 strh \rd, [\rx, #FSR]
48 .macro busyuart, rd, rx argument
49 1001: ldrh \rd, [\rx, #FSR]
Dmsm.S23 .macro senduart, rd, rx argument
26 str \rd, [\rx, #0x70]
29 .macro waituart, rd, rx argument
31 ldr \rd, [\rx, #0x08]
36 1001: ldr \rd, [\rx, #0x14]
44 str \rd, [\rx, #0x10]
48 str \rd, [\rx, #0x40]
50 ldr \rd, [\rx, #0x08]
53 .macro busyuart, rd, rx argument
Dbcm63xx.S18 .macro senduart, rd, rx argument
20 strb \rd, [\rx, #UART_FIFO_REG]
23 .macro waituart, rd, rx argument
24 1001: ldr \rd, [\rx, #UART_IR_REG]
29 .macro busyuart, rd, rx argument
30 1002: ldr \rd, [\rx, #UART_IR_REG]
Dnetx.S22 .macro senduart,rd,rx argument
23 str \rd, [\rx, #UART_DATA]
26 .macro busyuart,rd,rx argument
27 1002: ldr \rd, [\rx, #UART_FLAG]
32 .macro waituart,rd,rx argument
33 1001: ldr \rd, [\rx, #UART_FLAG]
Dmeson.S21 .macro senduart,rd,rx argument
22 str \rd, [\rx, #MESON_AO_UART_WFIFO]
25 .macro busyuart,rd,rx argument
26 1002: ldr \rd, [\rx, #MESON_AO_UART_STATUS]
31 .macro waituart,rd,rx argument
32 1001: ldr \rd, [\rx, #MESON_AO_UART_STATUS]
Dpl01x.S29 .macro senduart,rd,rx argument
30 strb \rd, [\rx, #UART01x_DR]
33 .macro waituart,rd,rx argument
34 1001: ldr \rd, [\rx, #UART01x_FR]
40 .macro busyuart,rd,rx argument
41 1001: ldr \rd, [\rx, #UART01x_FR]
Dasm9260.S18 .macro waituart,rd,rx argument
21 .macro senduart,rd,rx argument
22 str \rd, [\rx, #0x50] @ TXDATA
25 .macro busyuart,rd,rx argument
26 1002: ldr \rd, [\rx, #0x60] @ STAT
Ddigicolor.S24 .macro senduart,rd,rx argument
25 strb \rd, [\rx, #UA0_EMI_REC]
28 .macro waituart,rd,rx argument
31 .macro busyuart,rd,rx argument
32 1001: ldrb \rd, [\rx, #UA0_STATUS]
Dvt8500.S24 .macro senduart,rd,rx argument
25 strb \rd, [\rx, #0]
28 .macro busyuart,rd,rx argument
29 1001: ldr \rd, [\rx, #0x1c]
34 .macro waituart,rd,rx argument
Dclps711x.S27 .macro waituart,rd,rx argument
30 .macro senduart,rd,rx argument
31 str \rd, [\rx, #UARTDR]
34 .macro busyuart,rd,rx argument
35 1001: ldr \rd, [\rx, #SYSFLG]
Dsirf.S26 .macro senduart,rd,rx argument
27 str \rd, [\rx, #SIRF_LLUART_TXFIFO_DATA]
30 .macro busyuart,rd,rx argument
33 .macro waituart,rd,rx argument
34 1001: ldr \rd, [\rx, #SIRF_LLUART_TXFIFO_STATUS]
Dks8695.S26 .macro senduart, rd, rx argument
27 str \rd, [\rx, #KS8695_URTH] @ Write to Transmit Holding Register
30 .macro busyuart, rd, rx argument
31 1001: ldr \rd, [\rx, #KS8695_URLS] @ Read Line Status Register
36 .macro waituart, rd, rx argument
37 1001: ldr \rd, [\rx, #KS8695_URLS] @ Read Line Status Register
Dsti.S47 .macro senduart,rd,rx argument
48 strb \rd, [\rx, #ASC_TX_BUF_OFF]
51 .macro waituart,rd,rx argument
52 1001: ldr \rd, [\rx, #ASC_STA_OFF]
57 .macro busyuart,rd,rx argument
58 1001: ldr \rd, [\rx, #ASC_STA_OFF]
Dzynq.S40 .macro senduart,rd,rx argument
41 strb \rd, [\rx, #UART_FIFO_OFFSET] @ TXDATA
44 .macro waituart,rd,rx argument
45 1001: ldr \rd, [\rx, #UART_SR_OFFSET]
51 .macro busyuart,rd,rx argument
52 1002: ldr \rd, [\rx, #UART_SR_OFFSET] @ get status register
Dimx.S36 .macro senduart,rd,rx argument
37 str \rd, [\rx, #0x40] @ TXDATA
40 .macro waituart,rd,rx argument
43 .macro busyuart,rd,rx argument
44 1002: ldr \rd, [\rx, #0x98] @ SR2
Dat91.S30 .macro senduart,rd,rx argument
31 strb \rd, [\rx, #(AT91_DBGU_THR)] @ Write to Transmitter Holding Register
34 .macro waituart,rd,rx argument
35 1001: ldr \rd, [\rx, #(AT91_DBGU_SR)] @ Read Status Register
40 .macro busyuart,rd,rx argument
41 1001: ldr \rd, [\rx, #(AT91_DBGU_SR)] @ Read Status Register
Dvf.S26 .macro senduart, rd, rx argument
27 strb \rd, [\rx, #0x7] @ Data Register
30 .macro busyuart, rd, rx argument
31 1001: ldrb \rd, [\rx, #0x4] @ Status Register 1
36 .macro waituart,rd,rx argument
Ds3c24xx.S24 .macro fifo_full_s3c2410 rd, rx argument
25 ldr \rd, [\rx, # S3C2410_UFSTAT]
29 .macro fifo_level_s3c2410 rd, rx argument
30 ldr \rd, [\rx, # S3C2410_UFSTAT]
/arch/arm/mach-footbridge/include/mach/
Ddebug-macro.S31 .macro senduart,rd,rx argument
32 str \rd, [\rx, #0x160] @ UARTDR
35 .macro busyuart,rd,rx argument
36 1001: ldr \rd, [\rx, #0x178] @ UARTFLG
41 .macro waituart,rd,rx argument
/arch/s390/kernel/
Duprobes.c268 union split_register *rx; in handle_insn_ril() local
275 rx = (union split_register *) &regs->gprs[insn->reg]; in handle_insn_ril()
283 rx->u64 = (unsigned long)uptr; in handle_insn_ril()
290 rc = emu_load_ril((u16 __user *)uptr, &rx->u32[1]); in handle_insn_ril()
293 rc = emu_load_ril((s16 __user *)uptr, &rx->u64); in handle_insn_ril()
296 rc = emu_load_ril((s16 __user *)uptr, &rx->u32[1]); in handle_insn_ril()
299 rc = emu_load_ril((u16 __user *)uptr, &rx->u64); in handle_insn_ril()
302 rc = emu_load_ril((u64 __user *)uptr, &rx->u64); in handle_insn_ril()
305 rc = emu_load_ril((s32 __user *)uptr, &rx->u64); in handle_insn_ril()
308 rc = emu_load_ril((u32 __user *)uptr, &rx->u32[1]); in handle_insn_ril()
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