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/arch/m68k/ifpsp060/
DMISC34 freal.s : 2.4
36 x_fovfl.s : 2.16
37 x_funfl.s : 2.19
38 x_funsupp.s : 2.27
39 x_effadd.s : 2.21
40 x_foperr.s : 2.9
41 x_fsnan.s : 2.12
42 x_finex.s : 2.14
43 x_fdz.s : 2.5
44 x_fline.s : 2.5
[all …]
/arch/mips/cavium-octeon/executive/
Dcvmx-interrupt-decodes.c59 gmx_rx_int_en.s.hg2cc = 1; in __cvmx_interrupt_gmxx_rxx_int_en_enable()
60 gmx_rx_int_en.s.hg2fld = 1; in __cvmx_interrupt_gmxx_rxx_int_en_enable()
61 gmx_rx_int_en.s.undat = 1; in __cvmx_interrupt_gmxx_rxx_int_en_enable()
62 gmx_rx_int_en.s.uneop = 1; in __cvmx_interrupt_gmxx_rxx_int_en_enable()
63 gmx_rx_int_en.s.unsop = 1; in __cvmx_interrupt_gmxx_rxx_int_en_enable()
64 gmx_rx_int_en.s.bad_term = 1; in __cvmx_interrupt_gmxx_rxx_int_en_enable()
65 gmx_rx_int_en.s.bad_seq = 1; in __cvmx_interrupt_gmxx_rxx_int_en_enable()
66 gmx_rx_int_en.s.rem_fault = 1; in __cvmx_interrupt_gmxx_rxx_int_en_enable()
67 gmx_rx_int_en.s.loc_fault = 1; in __cvmx_interrupt_gmxx_rxx_int_en_enable()
68 gmx_rx_int_en.s.pause_drp = 1; in __cvmx_interrupt_gmxx_rxx_int_en_enable()
[all …]
Dcvmx-helper-board.c251 result.s.link_up = 1; in __cvmx_helper_board_link_get()
252 result.s.full_duplex = 1; in __cvmx_helper_board_link_get()
253 result.s.speed = 1000; in __cvmx_helper_board_link_get()
261 result.s.link_up = 1; in __cvmx_helper_board_link_get()
262 result.s.full_duplex = 1; in __cvmx_helper_board_link_get()
263 result.s.speed = 1000; in __cvmx_helper_board_link_get()
271 result.s.link_up = 1; in __cvmx_helper_board_link_get()
272 result.s.full_duplex = 1; in __cvmx_helper_board_link_get()
273 result.s.speed = 1000; in __cvmx_helper_board_link_get()
286 result.s.link_up = 1; in __cvmx_helper_board_link_get()
[all …]
Dcvmx-helper-util.c101 cvmx_dprintf(" Buffers: %u\n", work->word2.s.bufs); in cvmx_helper_dump_packet()
103 if (work->word2.s.bufs == 0) { in cvmx_helper_dump_packet()
107 buffer_ptr.s.pool = wqe_pool.s.wqe_pool; in cvmx_helper_dump_packet()
108 buffer_ptr.s.size = 128; in cvmx_helper_dump_packet()
109 buffer_ptr.s.addr = cvmx_ptr_to_phys(work->packet_data); in cvmx_helper_dump_packet()
110 if (likely(!work->word2.s.not_IP)) { in cvmx_helper_dump_packet()
113 buffer_ptr.s.addr += in cvmx_helper_dump_packet()
114 (pip_ip_offset.s.offset << 3) - in cvmx_helper_dump_packet()
115 work->word2.s.ip_offset; in cvmx_helper_dump_packet()
116 buffer_ptr.s.addr += (work->word2.s.is_v6 ^ 1) << 2; in cvmx_helper_dump_packet()
[all …]
Dcvmx-helper-sgmii.c65 gmxx_prtx_cfg.s.en = 0; in __cvmx_helper_sgmii_hardware_init_one_time()
77 if (pcs_misc_ctl_reg.s.mode) { in __cvmx_helper_sgmii_hardware_init_one_time()
79 pcsx_linkx_timer_count_reg.s.count = in __cvmx_helper_sgmii_hardware_init_one_time()
83 pcsx_linkx_timer_count_reg.s.count = in __cvmx_helper_sgmii_hardware_init_one_time()
98 if (pcs_misc_ctl_reg.s.mode) { in __cvmx_helper_sgmii_hardware_init_one_time()
103 pcsx_anx_adv_reg.s.rem_flt = 0; in __cvmx_helper_sgmii_hardware_init_one_time()
104 pcsx_anx_adv_reg.s.pause = 3; in __cvmx_helper_sgmii_hardware_init_one_time()
105 pcsx_anx_adv_reg.s.hfd = 1; in __cvmx_helper_sgmii_hardware_init_one_time()
106 pcsx_anx_adv_reg.s.fd = 1; in __cvmx_helper_sgmii_hardware_init_one_time()
113 if (pcsx_miscx_ctl_reg.s.mac_phy) { in __cvmx_helper_sgmii_hardware_init_one_time()
[all …]
Dcvmx-spi.c216 spxx_clk_ctl.s.runbist = 1; in cvmx_spi_reset_cb()
220 if (spxx_bist_stat.s.stat0) in cvmx_spi_reset_cb()
224 if (spxx_bist_stat.s.stat1) in cvmx_spi_reset_cb()
227 if (spxx_bist_stat.s.stat2) in cvmx_spi_reset_cb()
237 srxx_spi4_calx.s.oddpar = 1; in cvmx_spi_reset_cb()
242 stxx_spi4_calx.s.oddpar = 1; in cvmx_spi_reset_cb()
257 spxx_clk_ctl.s.seetrn = 0; in cvmx_spi_reset_cb()
258 spxx_clk_ctl.s.clkdly = 0x10; in cvmx_spi_reset_cb()
259 spxx_clk_ctl.s.runbist = 0; in cvmx_spi_reset_cb()
260 spxx_clk_ctl.s.statdrv = 0; in cvmx_spi_reset_cb()
[all …]
Dcvmx-pko.c82 config.s.index = queue; in __cvmx_pko_iport_config()
83 config.s.qid = base_queue + queue; in __cvmx_pko_iport_config()
84 config.s.ipid = pko_port; in __cvmx_pko_iport_config()
85 config.s.tail = (queue == (num_queues - 1)); in __cvmx_pko_iport_config()
86 config.s.s_tail = (queue == static_priority_end); in __cvmx_pko_iport_config()
87 config.s.static_p = (static_priority_base >= 0); in __cvmx_pko_iport_config()
88 config.s.static_q = (queue <= static_priority_end); in __cvmx_pko_iport_config()
89 config.s.qos_mask = 0xff; in __cvmx_pko_iport_config()
105 config.s.buf_ptr = cvmx_ptr_to_phys(buf_ptr) >> 7; in __cvmx_pko_iport_config()
130 config.s.eid = 31; /* Invalid */ in __cvmx_pko_port_map_o68()
[all …]
/arch/x86/kvm/
Di8259.c42 static void pic_lock(struct kvm_pic *s) in pic_lock() argument
43 __acquires(&s->lock) in pic_lock()
45 spin_lock(&s->lock); in pic_lock()
48 static void pic_unlock(struct kvm_pic *s) in pic_unlock() argument
49 __releases(&s->lock) in pic_unlock()
51 bool wakeup = s->wakeup_needed; in pic_unlock()
55 s->wakeup_needed = false; in pic_unlock()
57 spin_unlock(&s->lock); in pic_unlock()
60 kvm_for_each_vcpu(i, vcpu, s->kvm) { in pic_unlock()
75 static void pic_clear_isr(struct kvm_kpic_state *s, int irq) in pic_clear_isr() argument
[all …]
/arch/alpha/lib/
Dmemcpy.c25 #define ALIGN_DEST_TO8_UP(d,s,n) \ argument
29 *(char *) d = *(char *) s; \
30 d++; s++; \
32 #define ALIGN_DEST_TO8_DN(d,s,n) \ argument
36 d--; s--; \
37 *(char *) d = *(char *) s; \
44 #define DO_REST_UP(d,s,n) \ argument
47 *(char *) d = *(char *) s; \
48 d++; s++; \
50 #define DO_REST_DN(d,s,n) \ argument
[all …]
/arch/arm/boot/compressed/
Dstring.c12 unsigned char *d = (unsigned char *)__dest, *s = (unsigned char *)__src; in memcpy() local
15 *d++ = *s++; in memcpy()
16 *d++ = *s++; in memcpy()
17 *d++ = *s++; in memcpy()
18 *d++ = *s++; in memcpy()
19 *d++ = *s++; in memcpy()
20 *d++ = *s++; in memcpy()
21 *d++ = *s++; in memcpy()
22 *d++ = *s++; in memcpy()
26 *d++ = *s++; in memcpy()
[all …]
/arch/mips/include/asm/netlogic/xlr/
Dfmn.h144 #define nlm_read_c2_cc0(s) __read_32bit_c2_register($16, s) argument
145 #define nlm_read_c2_cc1(s) __read_32bit_c2_register($17, s) argument
146 #define nlm_read_c2_cc2(s) __read_32bit_c2_register($18, s) argument
147 #define nlm_read_c2_cc3(s) __read_32bit_c2_register($19, s) argument
148 #define nlm_read_c2_cc4(s) __read_32bit_c2_register($20, s) argument
149 #define nlm_read_c2_cc5(s) __read_32bit_c2_register($21, s) argument
150 #define nlm_read_c2_cc6(s) __read_32bit_c2_register($22, s) argument
151 #define nlm_read_c2_cc7(s) __read_32bit_c2_register($23, s) argument
152 #define nlm_read_c2_cc8(s) __read_32bit_c2_register($24, s) argument
153 #define nlm_read_c2_cc9(s) __read_32bit_c2_register($25, s) argument
[all …]
/arch/mips/include/asm/octeon/
Dcvmx-ipd.h93 first_skip.s.skip_sz = first_mbuff_skip; in cvmx_ipd_config()
97 not_first_skip.s.skip_sz = not_first_mbuff_skip; in cvmx_ipd_config()
101 size.s.mb_size = mbuff_size; in cvmx_ipd_config()
105 first_back_struct.s.back = first_back; in cvmx_ipd_config()
109 second_back_struct.s.back = second_back; in cvmx_ipd_config()
113 wqe_pool.s.wqe_pool = wqe_fpa_pool; in cvmx_ipd_config()
117 ipd_ctl_reg.s.opc_mode = cache_mode; in cvmx_ipd_config()
118 ipd_ctl_reg.s.pbp_en = back_pres_enable_flag; in cvmx_ipd_config()
132 if (ipd_reg.s.ipd_en) { in cvmx_ipd_enable()
136 ipd_reg.s.ipd_en = 1; in cvmx_ipd_enable()
[all …]
Dcvmx-mdio.h59 } s; member
86 } s; member
97 } s; member
110 } s; member
132 } s; member
154 } s; member
171 } s; member
188 } s; member
206 } s; member
221 } s; member
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/arch/xtensa/variants/de212/include/variant/
Dtie.h89 #define XCHAL_NCP_SA_LIST(s) \ argument
90 XCHAL_SA_REG(s,1,0,0,1, acclo, 4, 4, 4,0x0210, sr,16 , 32,0,0,0) \
91 XCHAL_SA_REG(s,1,0,0,1, acchi, 4, 4, 4,0x0211, sr,17 , 8,0,0,0) \
92 XCHAL_SA_REG(s,0,0,0,1, scompare1, 4, 4, 4,0x020C, sr,12 , 32,0,0,0) \
93 XCHAL_SA_REG(s,0,0,0,1, m0, 4, 4, 4,0x0220, sr,32 , 32,0,0,0) \
94 XCHAL_SA_REG(s,0,0,0,1, m1, 4, 4, 4,0x0221, sr,33 , 32,0,0,0) \
95 XCHAL_SA_REG(s,0,0,0,1, m2, 4, 4, 4,0x0222, sr,34 , 32,0,0,0) \
96 XCHAL_SA_REG(s,0,0,0,1, m3, 4, 4, 4,0x0223, sr,35 , 32,0,0,0)
99 #define XCHAL_CP0_SA_LIST(s) /* empty */ argument
102 #define XCHAL_CP1_SA_LIST(s) /* empty */ argument
[all …]
/arch/arm64/crypto/
Dsha2-ce-core.S35 add t1.4s, v\s0\().4s, \rc\().4s
36 sha256h dg0q, dg1q, t0.4s
37 sha256h2 dg1q, dg2q, t0.4s
40 add t0.4s, v\s0\().4s, \rc\().4s
42 sha256h dg0q, dg1q, t1.4s
43 sha256h2 dg1q, dg2q, t1.4s
48 sha256su0 v\s0\().4s, v\s1\().4s
50 sha256su1 v\s0\().4s, v\s2\().4s, v\s3\().4s
82 ld1 { v0.4s- v3.4s}, [x8], #64
83 ld1 { v4.4s- v7.4s}, [x8], #64
[all …]
/arch/xtensa/variants/dc232b/include/variant/
Dtie.h93 #define XCHAL_NCP_SA_LIST(s) \ argument
94 XCHAL_SA_REG(s,1,0,0,1, acclo, 4, 4, 4,0x0210, sr,16 , 32,0,0,0) \
95 XCHAL_SA_REG(s,1,0,0,1, acchi, 4, 4, 4,0x0211, sr,17 , 8,0,0,0) \
96 XCHAL_SA_REG(s,0,0,0,1, m0, 4, 4, 4,0x0220, sr,32 , 32,0,0,0) \
97 XCHAL_SA_REG(s,0,0,0,1, m1, 4, 4, 4,0x0221, sr,33 , 32,0,0,0) \
98 XCHAL_SA_REG(s,0,0,0,1, m2, 4, 4, 4,0x0222, sr,34 , 32,0,0,0) \
99 XCHAL_SA_REG(s,0,0,0,1, m3, 4, 4, 4,0x0223, sr,35 , 32,0,0,0) \
100 XCHAL_SA_REG(s,0,0,0,1, scompare1, 4, 4, 4,0x020C, sr,12 , 32,0,0,0) \
101 XCHAL_SA_REG(s,1,2,1,1, threadptr, 4, 4, 4,0x03E7, ur,231, 32,0,0,0)
104 #define XCHAL_CP0_SA_LIST(s) /* empty */ argument
[all …]
/arch/xtensa/variants/dc233c/include/variant/
Dtie.h112 #define XCHAL_NCP_SA_LIST(s) \ argument
113 XCHAL_SA_REG(s,1,2,1,1, threadptr, 4, 4, 4,0x03E7, ur,231, 32,0,0,0) \
114 XCHAL_SA_REG(s,1,0,0,1, acclo, 4, 4, 4,0x0210, sr,16 , 32,0,0,0) \
115 XCHAL_SA_REG(s,1,0,0,1, acchi, 4, 4, 4,0x0211, sr,17 , 8,0,0,0) \
116 XCHAL_SA_REG(s,0,0,0,1, m0, 4, 4, 4,0x0220, sr,32 , 32,0,0,0) \
117 XCHAL_SA_REG(s,0,0,0,1, m1, 4, 4, 4,0x0221, sr,33 , 32,0,0,0) \
118 XCHAL_SA_REG(s,0,0,0,1, m2, 4, 4, 4,0x0222, sr,34 , 32,0,0,0) \
119 XCHAL_SA_REG(s,0,0,0,1, m3, 4, 4, 4,0x0223, sr,35 , 32,0,0,0) \
120 XCHAL_SA_REG(s,0,0,0,1, scompare1, 4, 4, 4,0x020C, sr,12 , 32,0,0,0)
123 #define XCHAL_CP0_SA_LIST(s) /* empty */ argument
[all …]
/arch/mips/pci/
Dpci-octeon.c59 } s; member
266 pci_addr.s.upper = 2; in octeon_read_config()
267 pci_addr.s.io = 1; in octeon_read_config()
268 pci_addr.s.did = 3; in octeon_read_config()
269 pci_addr.s.subdid = 1; in octeon_read_config()
270 pci_addr.s.endian_swap = 1; in octeon_read_config()
271 pci_addr.s.bus = bus->number; in octeon_read_config()
272 pci_addr.s.dev = devfn >> 3; in octeon_read_config()
273 pci_addr.s.func = devfn & 0x7; in octeon_read_config()
274 pci_addr.s.reg = reg; in octeon_read_config()
[all …]
/arch/powerpc/platforms/cell/
Dspu_callbacks.c53 long spu_sys_callback(struct spu_syscall_block *s) in spu_sys_callback() argument
57 if (s->nr_ret >= ARRAY_SIZE(spu_syscall_table)) { in spu_sys_callback()
58 pr_debug("%s: invalid syscall #%lld", __func__, s->nr_ret); in spu_sys_callback()
62 syscall = spu_syscall_table[s->nr_ret]; in spu_sys_callback()
67 s->nr_ret, in spu_sys_callback()
68 s->parm[0], s->parm[1], s->parm[2], in spu_sys_callback()
69 s->parm[3], s->parm[4], s->parm[5]); in spu_sys_callback()
71 return syscall(s->parm[0], s->parm[1], s->parm[2], in spu_sys_callback()
72 s->parm[3], s->parm[4], s->parm[5]); in spu_sys_callback()
/arch/mips/lasat/
Dinterrupt.c57 int b = 31, s; in ls1bit32() local
59 s = 16; if (x << 16 == 0) s = 0; b -= s; x <<= s; in ls1bit32()
60 s = 8; if (x << 8 == 0) s = 0; b -= s; x <<= s; in ls1bit32()
61 s = 4; if (x << 4 == 0) s = 0; b -= s; x <<= s; in ls1bit32()
62 s = 2; if (x << 2 == 0) s = 0; b -= s; x <<= s; in ls1bit32()
63 s = 1; if (x << 1 == 0) s = 0; b -= s; in ls1bit32()
/arch/x86/include/asm/
Dstring_32.h27 extern char *strchr(const char *s, int c);
30 extern size_t strlen(const char *s);
207 static inline void *__memset_generic(void *s, char c, size_t count) in __memset_generic() argument
213 : "a" (c), "1" (s), "0" (count) in __memset_generic()
215 return s; in __memset_generic()
219 #define __constant_count_memset(s, c, count) __memset_generic((s), (c), (count)) argument
227 void *__constant_c_memset(void *s, unsigned long c, size_t count) in __constant_c_memset() argument
239 : "a" (c), "q" (count), "0" (count/4), "1" ((long)s) in __constant_c_memset()
241 return s; in __constant_c_memset()
246 extern size_t strnlen(const char *s, size_t count);
[all …]
/arch/unicore32/boot/compressed/
Dmisc.c46 unsigned char *d = (unsigned char *)dest, *s = (unsigned char *)src; in memcpy() local
49 *d++ = *s++; in memcpy()
50 *d++ = *s++; in memcpy()
51 *d++ = *s++; in memcpy()
52 *d++ = *s++; in memcpy()
53 *d++ = *s++; in memcpy()
54 *d++ = *s++; in memcpy()
55 *d++ = *s++; in memcpy()
56 *d++ = *s++; in memcpy()
60 *d++ = *s++; in memcpy()
[all …]
/arch/mips/include/asm/
Dcompat-signal.h14 const sigset_t *s) in __copy_conv_sigset_to_user() argument
18 BUG_ON(sizeof(*d) != sizeof(*s)); in __copy_conv_sigset_to_user()
21 err = __put_user(s->sig[0], &d->sig[0]); in __copy_conv_sigset_to_user()
22 err |= __put_user(s->sig[0] >> 32, &d->sig[1]); in __copy_conv_sigset_to_user()
23 err |= __put_user(s->sig[1], &d->sig[2]); in __copy_conv_sigset_to_user()
24 err |= __put_user(s->sig[1] >> 32, &d->sig[3]); in __copy_conv_sigset_to_user()
30 const compat_sigset_t __user *s) in __copy_conv_sigset_from_user() argument
34 sigset_t s; in __copy_conv_sigset_from_user() member
38 BUG_ON(sizeof(*d) != sizeof(*s)); in __copy_conv_sigset_from_user()
42 err = __get_user(u->c.sig[1], &s->sig[0]); in __copy_conv_sigset_from_user()
[all …]
/arch/m68k/lib/
Dmemset.c10 void *memset(void *s, int c, size_t count) in memset() argument
12 void *xs = s; in memset()
20 if ((long)s & 1) { in memset()
21 char *cs = s; in memset()
23 s = cs; in memset()
26 if (count > 2 && (long)s & 2) { in memset()
27 short *ss = s; in memset()
29 s = ss; in memset()
34 long *ls = s; in memset()
61 s = ls; in memset()
[all …]
/arch/mips/mti-sead3/
Dsead3-init.c26 char *s; in console_config() local
29 s = fw_getenv("modetty0"); in console_config()
30 if (s) { in console_config()
31 while (*s >= '0' && *s <= '9') in console_config()
32 baud = baud*10 + *s++ - '0'; in console_config()
33 if (*s == ',') in console_config()
34 s++; in console_config()
35 if (*s) in console_config()
36 parity = *s++; in console_config()
37 if (*s == ',') in console_config()
[all …]

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