1 /* arch/arm/plat-samsung/include/plat/cpu-freq-core.h
2 *
3 * Copyright (c) 2006-2009 Simtec Electronics
4 * http://armlinux.simtec.co.uk/
5 * Ben Dooks <ben@simtec.co.uk>
6 *
7 * S3C CPU frequency scaling support - core support
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14 #include <plat/cpu-freq.h>
15
16 struct seq_file;
17
18 #define MAX_BANKS (8)
19 #define S3C2412_MAX_IO (8)
20
21 /**
22 * struct s3c2410_iobank_timing - IO bank timings for S3C2410 style timings
23 * @bankcon: The cached version of settings in this structure.
24 * @tacp:
25 * @tacs: Time from address valid to nCS asserted.
26 * @tcos: Time from nCS asserted to nOE or nWE asserted.
27 * @tacc: Time that nOE or nWE is asserted.
28 * @tcoh: Time nCS is held after nOE or nWE are released.
29 * @tcah: Time address is held for after
30 * @nwait_en: Whether nWAIT is enabled for this bank.
31 *
32 * This structure represents the IO timings for a S3C2410 style IO bank
33 * used by the CPU frequency support if it needs to change the settings
34 * of the IO.
35 */
36 struct s3c2410_iobank_timing {
37 unsigned long bankcon;
38 unsigned int tacp;
39 unsigned int tacs;
40 unsigned int tcos;
41 unsigned int tacc;
42 unsigned int tcoh; /* nCS hold afrer nOE/nWE */
43 unsigned int tcah; /* Address hold after nCS */
44 unsigned char nwait_en; /* nWait enabled for bank. */
45 };
46
47 /**
48 * struct s3c2412_iobank_timing - io timings for PL092 (S3C2412) style IO
49 * @idcy: The idle cycle time between transactions.
50 * @wstrd: nCS release to end of read cycle.
51 * @wstwr: nCS release to end of write cycle.
52 * @wstoen: nCS assertion to nOE assertion time.
53 * @wstwen: nCS assertion to nWE assertion time.
54 * @wstbrd: Burst ready delay.
55 * @smbidcyr: Register cache for smbidcyr value.
56 * @smbwstrd: Register cache for smbwstrd value.
57 * @smbwstwr: Register cache for smbwstwr value.
58 * @smbwstoen: Register cache for smbwstoen value.
59 * @smbwstwen: Register cache for smbwstwen value.
60 * @smbwstbrd: Register cache for smbwstbrd value.
61 *
62 * Timing information for a IO bank on an S3C2412 or similar system which
63 * uses a PL093 block.
64 */
65 struct s3c2412_iobank_timing {
66 unsigned int idcy;
67 unsigned int wstrd;
68 unsigned int wstwr;
69 unsigned int wstoen;
70 unsigned int wstwen;
71 unsigned int wstbrd;
72
73 /* register cache */
74 unsigned char smbidcyr;
75 unsigned char smbwstrd;
76 unsigned char smbwstwr;
77 unsigned char smbwstoen;
78 unsigned char smbwstwen;
79 unsigned char smbwstbrd;
80 };
81
82 union s3c_iobank {
83 struct s3c2410_iobank_timing *io_2410;
84 struct s3c2412_iobank_timing *io_2412;
85 };
86
87 /**
88 * struct s3c_iotimings - Chip IO timings holder
89 * @bank: The timings for each IO bank.
90 */
91 struct s3c_iotimings {
92 union s3c_iobank bank[MAX_BANKS];
93 };
94
95 /**
96 * struct s3c_plltab - PLL table information.
97 * @vals: List of PLL values.
98 * @size: Size of the PLL table @vals.
99 */
100 struct s3c_plltab {
101 struct s3c_pllval *vals;
102 int size;
103 };
104
105 /**
106 * struct s3c_cpufreq_config - current cpu frequency configuration
107 * @freq: The current settings for the core clocks.
108 * @max: Maxium settings, derived from core, board and user settings.
109 * @pll: The PLL table entry for the current PLL settings.
110 * @divs: The divisor settings for the core clocks.
111 * @info: The current core driver information.
112 * @board: The information for the board we are running on.
113 * @lock_pll: Set if the PLL settings cannot be changed.
114 *
115 * This is for the core drivers that need to know information about
116 * the current settings and values. It should not be needed by any
117 * device drivers.
118 */
119 struct s3c_cpufreq_config {
120 struct s3c_freq freq;
121 struct s3c_freq max;
122 struct clk *mpll;
123 struct cpufreq_frequency_table pll;
124 struct s3c_clkdivs divs;
125 struct s3c_cpufreq_info *info; /* for core, not drivers */
126 struct s3c_cpufreq_board *board;
127
128 unsigned int lock_pll:1;
129 };
130
131 /**
132 * struct s3c_cpufreq_info - Information for the CPU frequency driver.
133 * @name: The name of this implementation.
134 * @max: The maximum frequencies for the system.
135 * @latency: Transition latency to give to cpufreq.
136 * @locktime_m: The lock-time in uS for the MPLL.
137 * @locktime_u: The lock-time in uS for the UPLL.
138 * @locttime_bits: The number of bits each LOCKTIME field.
139 * @need_pll: Set if this driver needs to change the PLL values to achieve
140 * any frequency changes. This is really only need by devices like the
141 * S3C2410 where there is no or limited divider between the PLL and the
142 * ARMCLK.
143 * @get_iotiming: Get the current IO timing data, mainly for use at start.
144 * @set_iotiming: Update the IO timings from the cached copies calculated
145 * from the @calc_iotiming entry when changing the frequency.
146 * @calc_iotiming: Calculate and update the cached copies of the IO timings
147 * from the newly calculated frequencies.
148 * @calc_freqtable: Calculate (fill in) the given frequency table from the
149 * current frequency configuration. If the table passed in is NULL,
150 * then the return is the number of elements to be filled for allocation
151 * of the table.
152 * @set_refresh: Set the memory refresh configuration.
153 * @set_fvco: Set the PLL frequencies.
154 * @set_divs: Update the clock divisors.
155 * @calc_divs: Calculate the clock divisors.
156 */
157 struct s3c_cpufreq_info {
158 const char *name;
159 struct s3c_freq max;
160
161 unsigned int latency;
162
163 unsigned int locktime_m;
164 unsigned int locktime_u;
165 unsigned char locktime_bits;
166
167 unsigned int need_pll:1;
168
169 /* driver routines */
170
171 int (*get_iotiming)(struct s3c_cpufreq_config *cfg,
172 struct s3c_iotimings *timings);
173
174 void (*set_iotiming)(struct s3c_cpufreq_config *cfg,
175 struct s3c_iotimings *timings);
176
177 int (*calc_iotiming)(struct s3c_cpufreq_config *cfg,
178 struct s3c_iotimings *timings);
179
180 int (*calc_freqtable)(struct s3c_cpufreq_config *cfg,
181 struct cpufreq_frequency_table *t,
182 size_t table_size);
183
184 void (*debug_io_show)(struct seq_file *seq,
185 struct s3c_cpufreq_config *cfg,
186 union s3c_iobank *iob);
187
188 void (*set_refresh)(struct s3c_cpufreq_config *cfg);
189 void (*set_fvco)(struct s3c_cpufreq_config *cfg);
190 void (*set_divs)(struct s3c_cpufreq_config *cfg);
191 int (*calc_divs)(struct s3c_cpufreq_config *cfg);
192 };
193
194 extern int s3c_cpufreq_register(struct s3c_cpufreq_info *info);
195
196 extern int s3c_plltab_register(struct cpufreq_frequency_table *plls,
197 unsigned int plls_no);
198
199 /* exports and utilities for debugfs */
200 extern struct s3c_cpufreq_config *s3c_cpufreq_getconfig(void);
201 extern struct s3c_iotimings *s3c_cpufreq_getiotimings(void);
202
203 #ifdef CONFIG_ARM_S3C24XX_CPUFREQ_DEBUGFS
204 #define s3c_cpufreq_debugfs_call(x) x
205 #else
206 #define s3c_cpufreq_debugfs_call(x) NULL
207 #endif
208
209 /* Useful utility functions. */
210
211 extern struct clk *s3c_cpufreq_clk_get(struct device *, const char *);
212
213 /* S3C2410 and compatible exported functions */
214
215 extern void s3c2410_cpufreq_setrefresh(struct s3c_cpufreq_config *cfg);
216 extern void s3c2410_set_fvco(struct s3c_cpufreq_config *cfg);
217
218 #ifdef CONFIG_S3C2410_IOTIMING
219 extern void s3c2410_iotiming_debugfs(struct seq_file *seq,
220 struct s3c_cpufreq_config *cfg,
221 union s3c_iobank *iob);
222
223 extern int s3c2410_iotiming_calc(struct s3c_cpufreq_config *cfg,
224 struct s3c_iotimings *iot);
225
226 extern int s3c2410_iotiming_get(struct s3c_cpufreq_config *cfg,
227 struct s3c_iotimings *timings);
228
229 extern void s3c2410_iotiming_set(struct s3c_cpufreq_config *cfg,
230 struct s3c_iotimings *iot);
231 #else
232 #define s3c2410_iotiming_debugfs NULL
233 #define s3c2410_iotiming_calc NULL
234 #define s3c2410_iotiming_get NULL
235 #define s3c2410_iotiming_set NULL
236 #endif /* CONFIG_S3C2410_IOTIMING */
237
238 /* S3C2412 compatible routines */
239
240 #ifdef CONFIG_S3C2412_IOTIMING
241 extern void s3c2412_iotiming_debugfs(struct seq_file *seq,
242 struct s3c_cpufreq_config *cfg,
243 union s3c_iobank *iob);
244
245 extern int s3c2412_iotiming_get(struct s3c_cpufreq_config *cfg,
246 struct s3c_iotimings *timings);
247
248 extern int s3c2412_iotiming_calc(struct s3c_cpufreq_config *cfg,
249 struct s3c_iotimings *iot);
250
251 extern void s3c2412_iotiming_set(struct s3c_cpufreq_config *cfg,
252 struct s3c_iotimings *iot);
253 #else
254 #define s3c2412_iotiming_debugfs NULL
255 #define s3c2412_iotiming_calc NULL
256 #define s3c2412_iotiming_get NULL
257 #define s3c2412_iotiming_set NULL
258 #endif /* CONFIG_S3C2412_IOTIMING */
259
260 #ifdef CONFIG_ARM_S3C24XX_CPUFREQ_DEBUG
261 #define s3c_freq_dbg(x...) printk(KERN_INFO x)
262 #else
263 #define s3c_freq_dbg(x...) do { if (0) printk(x); } while (0)
264 #endif /* CONFIG_ARM_S3C24XX_CPUFREQ_DEBUG */
265
266 #ifdef CONFIG_ARM_S3C24XX_CPUFREQ_IODEBUG
267 #define s3c_freq_iodbg(x...) printk(KERN_INFO x)
268 #else
269 #define s3c_freq_iodbg(x...) do { if (0) printk(x); } while (0)
270 #endif /* CONFIG_ARM_S3C24XX_CPUFREQ_IODEBUG */
271
s3c_cpufreq_addfreq(struct cpufreq_frequency_table * table,int index,size_t table_size,unsigned int freq)272 static inline int s3c_cpufreq_addfreq(struct cpufreq_frequency_table *table,
273 int index, size_t table_size,
274 unsigned int freq)
275 {
276 if (index < 0)
277 return index;
278
279 if (table) {
280 if (index >= table_size)
281 return -ENOMEM;
282
283 s3c_freq_dbg("%s: { %d = %u kHz }\n",
284 __func__, index, freq);
285
286 table[index].driver_data = index;
287 table[index].frequency = freq;
288 }
289
290 return index + 1;
291 }
292