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Searched refs:sg_pci (Results 1 – 16 of 16) sorted by relevance

/arch/alpha/kernel/
Dcore_titan.c321 hose->sg_pci = iommu_arena_new(hose, 0xc0000000, 0x40000000, 0); in titan_init_one_pachip_port()
322 hose->sg_pci->align_entry = 4; /* Titan caches 4 PTEs at a time */ in titan_init_one_pachip_port()
332 port->wsba[2].csr = hose->sg_pci->dma_base | 3; in titan_init_one_pachip_port()
333 port->wsm[2].csr = (hose->sg_pci->size - 1) & 0xfff00000; in titan_init_one_pachip_port()
334 port->tba[2].csr = virt_to_phys(hose->sg_pci->ptes); in titan_init_one_pachip_port()
493 if (hose->sg_pci && in titan_ioremap()
494 baddr >= (unsigned long)hose->sg_pci->dma_base && in titan_ioremap()
495 last < (unsigned long)hose->sg_pci->dma_base + hose->sg_pci->size){ in titan_ioremap()
500 baddr -= hose->sg_pci->dma_base; in titan_ioremap()
501 last -= hose->sg_pci->dma_base; in titan_ioremap()
[all …]
Dcore_marvel.c303 hose->sg_pci = iommu_arena_new_node(marvel_cpuid_to_nid(io7->pe), in io7_init_hose()
305 hose->sg_pci->align_entry = 8; /* cache line boundary */ in io7_init_hose()
307 hose->sg_pci->dma_base | wbase_m_ena | wbase_m_sg; in io7_init_hose()
308 csrs->POx_WMASK[2].csr = (hose->sg_pci->size - 1) & wbase_m_addr; in io7_init_hose()
309 csrs->POx_TBASE[2].csr = virt_to_phys(hose->sg_pci->ptes); in io7_init_hose()
721 if (hose->sg_pci && in marvel_ioremap()
722 baddr >= (unsigned long)hose->sg_pci->dma_base && in marvel_ioremap()
723 last < (unsigned long)hose->sg_pci->dma_base + hose->sg_pci->size) { in marvel_ioremap()
728 baddr -= hose->sg_pci->dma_base; in marvel_ioremap()
729 last -= hose->sg_pci->dma_base; in marvel_ioremap()
[all …]
Dcore_tsunami.c325 hose->sg_pci = iommu_arena_new(hose, 0x40000000, in tsunami_init_one_pchip()
327 hose->sg_pci->align_entry = 4; /* Tsunami caches 4 PTEs at a time */ in tsunami_init_one_pchip()
336 pchip->wsba[1].csr = hose->sg_pci->dma_base | 3; in tsunami_init_one_pchip()
337 pchip->wsm[1].csr = (hose->sg_pci->size - 1) & 0xfff00000; in tsunami_init_one_pchip()
338 pchip->tba[1].csr = virt_to_phys(hose->sg_pci->ptes); in tsunami_init_one_pchip()
Dpci.c98 struct pci_iommu_arena *pci = hose->sg_pci; in quirk_cypress()
324 sg_base = hose->sg_pci ? hose->sg_pci->dma_base : ~0; in common_init_pci()
Dcore_mcpcia.c367 hose->sg_pci = iommu_arena_new(hose, 0x40000000, in mcpcia_startup_hose()
377 *(vuip)MCPCIA_W1_BASE(mid) = hose->sg_pci->dma_base | 3; in mcpcia_startup_hose()
378 *(vuip)MCPCIA_W1_MASK(mid) = (hose->sg_pci->size - 1) & 0xfff00000; in mcpcia_startup_hose()
379 *(vuip)MCPCIA_T1_BASE(mid) = virt_to_phys(hose->sg_pci->ptes) >> 8; in mcpcia_startup_hose()
Dcore_polaris.c172 hose->sg_isa = hose->sg_pci = NULL; in polaris_init_arch()
Dpci_iommu.c296 arena = hose->sg_pci; in pci_map_single_1()
398 arena = hose->sg_pci; in alpha_pci_unmap_page()
686 arena = hose->sg_pci; in alpha_pci_map_sg()
749 arena = hose->sg_pci; in alpha_pci_unmap_sg()
828 arena = hose->sg_pci; in alpha_pci_supported()
Dcore_wildfire.c114 hose->sg_pci = iommu_arena_new(hose, 0xc0000000, 0x08000000, 0); in wildfire_init_hose()
130 pci->pci_window[3].wbase.csr = hose->sg_pci->dma_base | 3; in wildfire_init_hose()
131 pci->pci_window[3].wmask.csr = (hose->sg_pci->size - 1) & 0xfff00000; in wildfire_init_hose()
132 pci->pci_window[3].tbase.csr = virt_to_phys(hose->sg_pci->ptes); in wildfire_init_hose()
Dsys_jensen.c205 hose->sg_isa = hose->sg_pci = NULL; in jensen_init_arch()
Dcore_apecs.c349 hose->sg_pci = NULL; in apecs_init_arch()
Dcore_irongate.c294 hose->sg_isa = hose->sg_pci = NULL; in irongate_init_arch()
Dcore_lca.c278 hose->sg_pci = NULL; in lca_init_arch()
Dsys_dp264.c535 hose_head->sg_pci->align_entry = 4; in webbrick_init_arch()
Dcore_t2.c354 hose->sg_pci = NULL; in t2_sg_map_window2()
Dcore_cia.c725 hose->sg_pci = NULL; in do_init_arch()
/arch/alpha/include/asm/
Dpci.h46 struct pci_iommu_arena *sg_pci; member