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Searched refs:spu_chnldata_RW (Results 1 – 6 of 6) sorted by relevance

/arch/powerpc/platforms/cell/spufs/
Dbacking_ops.c54 ch0_data = ctx->csa.spu_chnldata_RW[0]; in gen_spu_event()
55 ch1_data = ctx->csa.spu_chnldata_RW[1]; in gen_spu_event()
56 ctx->csa.spu_chnldata_RW[0] |= event; in gen_spu_event()
185 return ctx->csa.spu_chnldata_RW[3]; in spu_backing_signal1_read()
192 ctx->csa.spu_chnldata_RW[3] |= data; in spu_backing_signal1_write()
194 ctx->csa.spu_chnldata_RW[3] = data; in spu_backing_signal1_write()
202 return ctx->csa.spu_chnldata_RW[4]; in spu_backing_signal2_read()
209 ctx->csa.spu_chnldata_RW[4] |= data; in spu_backing_signal2_write()
211 ctx->csa.spu_chnldata_RW[4] = data; in spu_backing_signal2_write()
Dswitch.c640 csa->spu_chnldata_RW[1] = in_be64(&priv2->spu_chnldata_RW); in save_ch_part1()
647 csa->spu_chnldata_RW[idx] = in_be64(&priv2->spu_chnldata_RW); in save_ch_part1()
649 out_be64(&priv2->spu_chnldata_RW, 0UL); in save_ch_part1()
667 csa->spu_mailbox_data[i] = in_be64(&priv2->spu_chnldata_RW); in save_spu_mb()
1091 out_be64(&priv2->spu_chnldata_RW, 0UL); in reset_ch_part1()
1098 out_be64(&priv2->spu_chnldata_RW, 0UL); in reset_ch_part1()
1544 ch0_data = csa->spu_chnldata_RW[0]; in set_llr_event()
1545 ch1_data = csa->spu_chnldata_RW[1]; in set_llr_event()
1546 csa->spu_chnldata_RW[0] |= MFC_LLR_LOST_EVENT; in set_llr_event()
1564 (csa->spu_chnldata_RW[1] & 0x20) && in restore_decr_wrapped()
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Dfile.c1018 data = ctx->csa.spu_chnldata_RW[3]; in __spufs_signal1_read()
1155 data = ctx->csa.spu_chnldata_RW[4]; in __spufs_signal2_read()
1932 return state->spu_chnldata_RW[0]; in spufs_event_status_get()
2180 info->dma_info_status = ctx->csa.spu_chnldata_RW[24]; in spufs_get_dma_info()
2181 info->dma_info_stall_and_notify = ctx->csa.spu_chnldata_RW[25]; in spufs_get_dma_info()
2182 info->dma_info_atomic_command_status = ctx->csa.spu_chnldata_RW[27]; in spufs_get_dma_info()
/arch/powerpc/include/asm/
Dspu_csa.h213 u64 spu_chnldata_RW; member
248 u64 spu_chnldata_RW[32]; member
Dspu.h468 u64 spu_chnldata_RW; /* 0x4070 */ member
/arch/powerpc/platforms/cell/
Dspu_base.c475 out_be64(&priv2->spu_chnldata_RW, 0); in spu_init_channels()