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1/*
2 * rtrap.S: Preparing for return from trap on Sparc V9.
3 *
4 * Copyright (C) 1997,1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
5 * Copyright (C) 1997 David S. Miller (davem@caip.rutgers.edu)
6 */
7
8
9#include <asm/asi.h>
10#include <asm/pstate.h>
11#include <asm/ptrace.h>
12#include <asm/spitfire.h>
13#include <asm/head.h>
14#include <asm/visasm.h>
15#include <asm/processor.h>
16
17#ifdef CONFIG_CONTEXT_TRACKING
18# define SCHEDULE_USER schedule_user
19#else
20# define SCHEDULE_USER schedule
21#endif
22
23		.text
24		.align			32
25__handle_preemption:
26		call			SCHEDULE_USER
27		 wrpr			%g0, RTRAP_PSTATE, %pstate
28		ba,pt			%xcc, __handle_preemption_continue
29		 wrpr			%g0, RTRAP_PSTATE_IRQOFF, %pstate
30
31__handle_user_windows:
32		call			fault_in_user_windows
33		 wrpr			%g0, RTRAP_PSTATE, %pstate
34		ba,pt			%xcc, __handle_preemption_continue
35		 wrpr			%g0, RTRAP_PSTATE_IRQOFF, %pstate
36
37__handle_userfpu:
38		rd			%fprs, %l5
39		andcc			%l5, FPRS_FEF, %g0
40		sethi			%hi(TSTATE_PEF), %o0
41		be,a,pn			%icc, __handle_userfpu_continue
42		 andn			%l1, %o0, %l1
43		ba,a,pt			%xcc, __handle_userfpu_continue
44
45__handle_signal:
46		mov			%l5, %o1
47		add			%sp, PTREGS_OFF, %o0
48		mov			%l0, %o2
49		call			do_notify_resume
50		 wrpr			%g0, RTRAP_PSTATE, %pstate
51		wrpr			%g0, RTRAP_PSTATE_IRQOFF, %pstate
52
53		/* Signal delivery can modify pt_regs tstate, so we must
54		 * reload it.
55		 */
56		ldx			[%sp + PTREGS_OFF + PT_V9_TSTATE], %l1
57		sethi			%hi(0xf << 20), %l4
58		and			%l1, %l4, %l4
59		ba,pt			%xcc, __handle_preemption_continue
60		 andn			%l1, %l4, %l1
61
62		/* When returning from a NMI (%pil==15) interrupt we want to
63		 * avoid running softirqs, doing IRQ tracing, preempting, etc.
64		 */
65		.globl			rtrap_nmi
66rtrap_nmi:	ldx			[%sp + PTREGS_OFF + PT_V9_TSTATE], %l1
67		sethi			%hi(0xf << 20), %l4
68		and			%l1, %l4, %l4
69		andn			%l1, %l4, %l1
70		srl			%l4, 20, %l4
71		ba,pt			%xcc, rtrap_no_irq_enable
72		nop
73		/* Do not actually set the %pil here.  We will do that
74		 * below after we clear PSTATE_IE in the %pstate register.
75		 * If we re-enable interrupts here, we can recurse down
76		 * the hardirq stack potentially endlessly, causing a
77		 * stack overflow.
78		 */
79
80		.align			64
81		.globl			rtrap_irq, rtrap, irqsz_patchme, rtrap_xcall
82rtrap_irq:
83rtrap:
84		/* mm/ultra.S:xcall_report_regs KNOWS about this load. */
85		ldx			[%sp + PTREGS_OFF + PT_V9_TSTATE], %l1
86rtrap_xcall:
87		sethi			%hi(0xf << 20), %l4
88		and			%l1, %l4, %l4
89		andn			%l1, %l4, %l1
90		srl			%l4, 20, %l4
91#ifdef CONFIG_TRACE_IRQFLAGS
92		brnz,pn			%l4, rtrap_no_irq_enable
93		 nop
94		call			trace_hardirqs_on
95		 nop
96		/* Do not actually set the %pil here.  We will do that
97		 * below after we clear PSTATE_IE in the %pstate register.
98		 * If we re-enable interrupts here, we can recurse down
99		 * the hardirq stack potentially endlessly, causing a
100		 * stack overflow.
101		 *
102		 * It is tempting to put this test and trace_hardirqs_on
103		 * call at the 'rt_continue' label, but that will not work
104		 * as that path hits unconditionally and we do not want to
105		 * execute this in NMI return paths, for example.
106		 */
107#endif
108rtrap_no_irq_enable:
109		andcc			%l1, TSTATE_PRIV, %l3
110		bne,pn			%icc, to_kernel
111		 nop
112
113		/* We must hold IRQs off and atomically test schedule+signal
114		 * state, then hold them off all the way back to userspace.
115		 * If we are returning to kernel, none of this matters.  Note
116		 * that we are disabling interrupts via PSTATE_IE, not using
117		 * %pil.
118		 *
119		 * If we do not do this, there is a window where we would do
120		 * the tests, later the signal/resched event arrives but we do
121		 * not process it since we are still in kernel mode.  It would
122		 * take until the next local IRQ before the signal/resched
123		 * event would be handled.
124		 *
125		 * This also means that if we have to deal with user
126		 * windows, we have to redo all of these sched+signal checks
127		 * with IRQs disabled.
128		 */
129to_user:	wrpr			%g0, RTRAP_PSTATE_IRQOFF, %pstate
130		wrpr			0, %pil
131__handle_preemption_continue:
132		ldx			[%g6 + TI_FLAGS], %l0
133		sethi			%hi(_TIF_USER_WORK_MASK), %o0
134		or			%o0, %lo(_TIF_USER_WORK_MASK), %o0
135		andcc			%l0, %o0, %g0
136		sethi			%hi(TSTATE_PEF), %o0
137		be,pt			%xcc, user_nowork
138		 andcc			%l1, %o0, %g0
139		andcc			%l0, _TIF_NEED_RESCHED, %g0
140		bne,pn			%xcc, __handle_preemption
141		 andcc			%l0, _TIF_DO_NOTIFY_RESUME_MASK, %g0
142		bne,pn			%xcc, __handle_signal
143		 ldub			[%g6 + TI_WSAVED], %o2
144		brnz,pn			%o2, __handle_user_windows
145		 nop
146		sethi			%hi(TSTATE_PEF), %o0
147		andcc			%l1, %o0, %g0
148
149		/* This fpdepth clear is necessary for non-syscall rtraps only */
150user_nowork:
151		bne,pn			%xcc, __handle_userfpu
152		 stb			%g0, [%g6 + TI_FPDEPTH]
153__handle_userfpu_continue:
154
155rt_continue:	ldx			[%sp + PTREGS_OFF + PT_V9_G1], %g1
156		ldx			[%sp + PTREGS_OFF + PT_V9_G2], %g2
157
158		ldx			[%sp + PTREGS_OFF + PT_V9_G3], %g3
159		ldx			[%sp + PTREGS_OFF + PT_V9_G4], %g4
160		ldx			[%sp + PTREGS_OFF + PT_V9_G5], %g5
161		brz,pt			%l3, 1f
162		mov			%g6, %l2
163
164		/* Must do this before thread reg is clobbered below.  */
165		LOAD_PER_CPU_BASE(%g5, %g6, %i0, %i1, %i2)
1661:
167		ldx			[%sp + PTREGS_OFF + PT_V9_G6], %g6
168		ldx			[%sp + PTREGS_OFF + PT_V9_G7], %g7
169
170		/* Normal globals are restored, go to trap globals.  */
171661:		wrpr			%g0, RTRAP_PSTATE_AG_IRQOFF, %pstate
172		nop
173		.section		.sun4v_2insn_patch, "ax"
174		.word			661b
175		wrpr			%g0, RTRAP_PSTATE_IRQOFF, %pstate
176		SET_GL(1)
177		.previous
178
179		mov			%l2, %g6
180
181		ldx			[%sp + PTREGS_OFF + PT_V9_I0], %i0
182		ldx			[%sp + PTREGS_OFF + PT_V9_I1], %i1
183
184		ldx			[%sp + PTREGS_OFF + PT_V9_I2], %i2
185		ldx			[%sp + PTREGS_OFF + PT_V9_I3], %i3
186		ldx			[%sp + PTREGS_OFF + PT_V9_I4], %i4
187		ldx			[%sp + PTREGS_OFF + PT_V9_I5], %i5
188		ldx			[%sp + PTREGS_OFF + PT_V9_I6], %i6
189		ldx			[%sp + PTREGS_OFF + PT_V9_I7], %i7
190		ldx			[%sp + PTREGS_OFF + PT_V9_TPC], %l2
191		ldx			[%sp + PTREGS_OFF + PT_V9_TNPC], %o2
192
193		ld			[%sp + PTREGS_OFF + PT_V9_Y], %o3
194		wr			%o3, %g0, %y
195		wrpr			%l4, 0x0, %pil
196		wrpr			%g0, 0x1, %tl
197		andn			%l1, TSTATE_SYSCALL, %l1
198		wrpr			%l1, %g0, %tstate
199		wrpr			%l2, %g0, %tpc
200		wrpr			%o2, %g0, %tnpc
201
202		brnz,pn			%l3, kern_rtt
203		 mov			PRIMARY_CONTEXT, %l7
204
205661:		ldxa			[%l7 + %l7] ASI_DMMU, %l0
206		.section		.sun4v_1insn_patch, "ax"
207		.word			661b
208		ldxa			[%l7 + %l7] ASI_MMU, %l0
209		.previous
210
211		sethi			%hi(sparc64_kern_pri_nuc_bits), %l1
212		ldx			[%l1 + %lo(sparc64_kern_pri_nuc_bits)], %l1
213		or			%l0, %l1, %l0
214
215661:		stxa			%l0, [%l7] ASI_DMMU
216		.section		.sun4v_1insn_patch, "ax"
217		.word			661b
218		stxa			%l0, [%l7] ASI_MMU
219		.previous
220
221		sethi			%hi(KERNBASE), %l7
222		flush			%l7
223		rdpr			%wstate, %l1
224		rdpr			%otherwin, %l2
225		srl			%l1, 3, %l1
226
227		wrpr			%l2, %g0, %canrestore
228		wrpr			%l1, %g0, %wstate
229		brnz,pt			%l2, user_rtt_restore
230		 wrpr			%g0, %g0, %otherwin
231
232		ldx			[%g6 + TI_FLAGS], %g3
233		wr			%g0, ASI_AIUP, %asi
234		rdpr			%cwp, %g1
235		andcc			%g3, _TIF_32BIT, %g0
236		sub			%g1, 1, %g1
237		bne,pt			%xcc, user_rtt_fill_32bit
238		 wrpr			%g1, %cwp
239		ba,a,pt			%xcc, user_rtt_fill_64bit
240
241user_rtt_fill_fixup_dax:
242		ba,pt	%xcc, user_rtt_fill_fixup_common
243		 mov	1, %g3
244
245user_rtt_fill_fixup_mna:
246		ba,pt	%xcc, user_rtt_fill_fixup_common
247		 mov	2, %g3
248
249user_rtt_fill_fixup:
250		ba,pt	%xcc, user_rtt_fill_fixup_common
251		 clr	%g3
252
253user_rtt_pre_restore:
254		add			%g1, 1, %g1
255		wrpr			%g1, 0x0, %cwp
256
257user_rtt_restore:
258		restore
259		rdpr			%canrestore, %g1
260		wrpr			%g1, 0x0, %cleanwin
261		retry
262		nop
263
264kern_rtt:	rdpr			%canrestore, %g1
265		brz,pn			%g1, kern_rtt_fill
266		 nop
267kern_rtt_restore:
268		stw			%g0, [%sp + PTREGS_OFF + PT_V9_MAGIC]
269		restore
270		retry
271
272to_kernel:
273#ifdef CONFIG_PREEMPT
274		ldsw			[%g6 + TI_PRE_COUNT], %l5
275		brnz			%l5, kern_fpucheck
276		 ldx			[%g6 + TI_FLAGS], %l5
277		andcc			%l5, _TIF_NEED_RESCHED, %g0
278		be,pt			%xcc, kern_fpucheck
279		 nop
280		cmp			%l4, 0
281		bne,pn			%xcc, kern_fpucheck
282		 nop
283		call			preempt_schedule_irq
284		 nop
285		ba,pt			%xcc, rtrap
286#endif
287kern_fpucheck:	ldub			[%g6 + TI_FPDEPTH], %l5
288		brz,pt			%l5, rt_continue
289		 srl			%l5, 1, %o0
290		add			%g6, TI_FPSAVED, %l6
291		ldub			[%l6 + %o0], %l2
292		sub			%l5, 2, %l5
293
294		add			%g6, TI_GSR, %o1
295		andcc			%l2, (FPRS_FEF|FPRS_DU), %g0
296		be,pt			%icc, 2f
297		 and			%l2, FPRS_DL, %l6
298		andcc			%l2, FPRS_FEF, %g0
299		be,pn			%icc, 5f
300		 sll			%o0, 3, %o5
301		rd			%fprs, %g1
302
303		wr			%g1, FPRS_FEF, %fprs
304		ldx			[%o1 + %o5], %g1
305		add			%g6, TI_XFSR, %o1
306		sll			%o0, 8, %o2
307		add			%g6, TI_FPREGS, %o3
308		brz,pn			%l6, 1f
309		 add			%g6, TI_FPREGS+0x40, %o4
310
311		membar			#Sync
312		ldda			[%o3 + %o2] ASI_BLK_P, %f0
313		ldda			[%o4 + %o2] ASI_BLK_P, %f16
314		membar			#Sync
3151:		andcc			%l2, FPRS_DU, %g0
316		be,pn			%icc, 1f
317		 wr			%g1, 0, %gsr
318		add			%o2, 0x80, %o2
319		membar			#Sync
320		ldda			[%o3 + %o2] ASI_BLK_P, %f32
321		ldda			[%o4 + %o2] ASI_BLK_P, %f48
3221:		membar			#Sync
323		ldx			[%o1 + %o5], %fsr
3242:		stb			%l5, [%g6 + TI_FPDEPTH]
325		ba,pt			%xcc, rt_continue
326		 nop
3275:		wr			%g0, FPRS_FEF, %fprs
328		sll			%o0, 8, %o2
329
330		add			%g6, TI_FPREGS+0x80, %o3
331		add			%g6, TI_FPREGS+0xc0, %o4
332		membar			#Sync
333		ldda			[%o3 + %o2] ASI_BLK_P, %f32
334		ldda			[%o4 + %o2] ASI_BLK_P, %f48
335		membar			#Sync
336		wr			%g0, FPRS_DU, %fprs
337		ba,pt			%xcc, rt_continue
338		 stb			%l5, [%g6 + TI_FPDEPTH]
339