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1 /*
2  * This file is subject to the terms and conditions of the GNU General Public
3  * License.  See the file "COPYING" in the main directory of this archive
4  * for more details.
5  *
6  * SGI UV architectural definitions
7  *
8  * Copyright (C) 2007-2014 Silicon Graphics, Inc. All rights reserved.
9  */
10 
11 #ifndef _ASM_X86_UV_UV_HUB_H
12 #define _ASM_X86_UV_UV_HUB_H
13 
14 #ifdef CONFIG_X86_64
15 #include <linux/numa.h>
16 #include <linux/percpu.h>
17 #include <linux/timer.h>
18 #include <linux/io.h>
19 #include <asm/types.h>
20 #include <asm/percpu.h>
21 #include <asm/uv/uv_mmrs.h>
22 #include <asm/irq_vectors.h>
23 #include <asm/io_apic.h>
24 
25 
26 /*
27  * Addressing Terminology
28  *
29  *	M       - The low M bits of a physical address represent the offset
30  *		  into the blade local memory. RAM memory on a blade is physically
31  *		  contiguous (although various IO spaces may punch holes in
32  *		  it)..
33  *
34  *	N	- Number of bits in the node portion of a socket physical
35  *		  address.
36  *
37  *	NASID   - network ID of a router, Mbrick or Cbrick. Nasid values of
38  *		  routers always have low bit of 1, C/MBricks have low bit
39  *		  equal to 0. Most addressing macros that target UV hub chips
40  *		  right shift the NASID by 1 to exclude the always-zero bit.
41  *		  NASIDs contain up to 15 bits.
42  *
43  *	GNODE   - NASID right shifted by 1 bit. Most mmrs contain gnodes instead
44  *		  of nasids.
45  *
46  *	PNODE   - the low N bits of the GNODE. The PNODE is the most useful variant
47  *		  of the nasid for socket usage.
48  *
49  *	GPA	- (global physical address) a socket physical address converted
50  *		  so that it can be used by the GRU as a global address. Socket
51  *		  physical addresses 1) need additional NASID (node) bits added
52  *		  to the high end of the address, and 2) unaliased if the
53  *		  partition does not have a physical address 0. In addition, on
54  *		  UV2 rev 1, GPAs need the gnode left shifted to bits 39 or 40.
55  *
56  *
57  *  NumaLink Global Physical Address Format:
58  *  +--------------------------------+---------------------+
59  *  |00..000|      GNODE             |      NodeOffset     |
60  *  +--------------------------------+---------------------+
61  *          |<-------53 - M bits --->|<--------M bits ----->
62  *
63  *	M - number of node offset bits (35 .. 40)
64  *
65  *
66  *  Memory/UV-HUB Processor Socket Address Format:
67  *  +----------------+---------------+---------------------+
68  *  |00..000000000000|   PNODE       |      NodeOffset     |
69  *  +----------------+---------------+---------------------+
70  *                   <--- N bits --->|<--------M bits ----->
71  *
72  *	M - number of node offset bits (35 .. 40)
73  *	N - number of PNODE bits (0 .. 10)
74  *
75  *		Note: M + N cannot currently exceed 44 (x86_64) or 46 (IA64).
76  *		The actual values are configuration dependent and are set at
77  *		boot time. M & N values are set by the hardware/BIOS at boot.
78  *
79  *
80  * APICID format
81  *	NOTE!!!!!! This is the current format of the APICID. However, code
82  *	should assume that this will change in the future. Use functions
83  *	in this file for all APICID bit manipulations and conversion.
84  *
85  *		1111110000000000
86  *		5432109876543210
87  *		pppppppppplc0cch	Nehalem-EX (12 bits in hdw reg)
88  *		ppppppppplcc0cch	Westmere-EX (12 bits in hdw reg)
89  *		pppppppppppcccch	SandyBridge (15 bits in hdw reg)
90  *		sssssssssss
91  *
92  *			p  = pnode bits
93  *			l =  socket number on board
94  *			c  = core
95  *			h  = hyperthread
96  *			s  = bits that are in the SOCKET_ID CSR
97  *
98  *	Note: Processor may support fewer bits in the APICID register. The ACPI
99  *	      tables hold all 16 bits. Software needs to be aware of this.
100  *
101  *	      Unless otherwise specified, all references to APICID refer to
102  *	      the FULL value contained in ACPI tables, not the subset in the
103  *	      processor APICID register.
104  */
105 
106 
107 /*
108  * Maximum number of bricks in all partitions and in all coherency domains.
109  * This is the total number of bricks accessible in the numalink fabric. It
110  * includes all C & M bricks. Routers are NOT included.
111  *
112  * This value is also the value of the maximum number of non-router NASIDs
113  * in the numalink fabric.
114  *
115  * NOTE: a brick may contain 1 or 2 OS nodes. Don't get these confused.
116  */
117 #define UV_MAX_NUMALINK_BLADES	16384
118 
119 /*
120  * Maximum number of C/Mbricks within a software SSI (hardware may support
121  * more).
122  */
123 #define UV_MAX_SSI_BLADES	256
124 
125 /*
126  * The largest possible NASID of a C or M brick (+ 2)
127  */
128 #define UV_MAX_NASID_VALUE	(UV_MAX_NUMALINK_BLADES * 2)
129 
130 struct uv_scir_s {
131 	struct timer_list timer;
132 	unsigned long	offset;
133 	unsigned long	last;
134 	unsigned long	idle_on;
135 	unsigned long	idle_off;
136 	unsigned char	state;
137 	unsigned char	enabled;
138 };
139 
140 /*
141  * The following defines attributes of the HUB chip. These attributes are
142  * frequently referenced and are kept in the per-cpu data areas of each cpu.
143  * They are kept together in a struct to minimize cache misses.
144  */
145 struct uv_hub_info_s {
146 	unsigned long		global_mmr_base;
147 	unsigned long		gpa_mask;
148 	unsigned int		gnode_extra;
149 	unsigned char		hub_revision;
150 	unsigned char		apic_pnode_shift;
151 	unsigned char		m_shift;
152 	unsigned char		n_lshift;
153 	unsigned long		gnode_upper;
154 	unsigned long		lowmem_remap_top;
155 	unsigned long		lowmem_remap_base;
156 	unsigned short		pnode;
157 	unsigned short		pnode_mask;
158 	unsigned short		coherency_domain_number;
159 	unsigned short		numa_blade_id;
160 	unsigned char		blade_processor_id;
161 	unsigned char		m_val;
162 	unsigned char		n_val;
163 	struct uv_scir_s	scir;
164 };
165 
166 DECLARE_PER_CPU(struct uv_hub_info_s, __uv_hub_info);
167 #define uv_hub_info		this_cpu_ptr(&__uv_hub_info)
168 #define uv_cpu_hub_info(cpu)	(&per_cpu(__uv_hub_info, cpu))
169 
170 /*
171  * Hub revisions less than UV2_HUB_REVISION_BASE are UV1 hubs. All UV2
172  * hubs have revision numbers greater than or equal to UV2_HUB_REVISION_BASE.
173  * This is a software convention - NOT the hardware revision numbers in
174  * the hub chip.
175  */
176 #define UV1_HUB_REVISION_BASE		1
177 #define UV2_HUB_REVISION_BASE		3
178 #define UV3_HUB_REVISION_BASE		5
179 
is_uv1_hub(void)180 static inline int is_uv1_hub(void)
181 {
182 	return uv_hub_info->hub_revision < UV2_HUB_REVISION_BASE;
183 }
184 
is_uv2_hub(void)185 static inline int is_uv2_hub(void)
186 {
187 	return ((uv_hub_info->hub_revision >= UV2_HUB_REVISION_BASE) &&
188 		(uv_hub_info->hub_revision < UV3_HUB_REVISION_BASE));
189 }
190 
is_uv3_hub(void)191 static inline int is_uv3_hub(void)
192 {
193 	return uv_hub_info->hub_revision >= UV3_HUB_REVISION_BASE;
194 }
195 
is_uv_hub(void)196 static inline int is_uv_hub(void)
197 {
198 	return uv_hub_info->hub_revision;
199 }
200 
201 /* code common to uv2 and uv3 only */
is_uvx_hub(void)202 static inline int is_uvx_hub(void)
203 {
204 	return uv_hub_info->hub_revision >= UV2_HUB_REVISION_BASE;
205 }
206 
207 union uvh_apicid {
208     unsigned long       v;
209     struct uvh_apicid_s {
210         unsigned long   local_apic_mask  : 24;
211         unsigned long   local_apic_shift :  5;
212         unsigned long   unused1          :  3;
213         unsigned long   pnode_mask       : 24;
214         unsigned long   pnode_shift      :  5;
215         unsigned long   unused2          :  3;
216     } s;
217 };
218 
219 /*
220  * Local & Global MMR space macros.
221  *	Note: macros are intended to be used ONLY by inline functions
222  *	in this file - not by other kernel code.
223  *		n -  NASID (full 15-bit global nasid)
224  *		g -  GNODE (full 15-bit global nasid, right shifted 1)
225  *		p -  PNODE (local part of nsids, right shifted 1)
226  */
227 #define UV_NASID_TO_PNODE(n)		(((n) >> 1) & uv_hub_info->pnode_mask)
228 #define UV_PNODE_TO_GNODE(p)		((p) |uv_hub_info->gnode_extra)
229 #define UV_PNODE_TO_NASID(p)		(UV_PNODE_TO_GNODE(p) << 1)
230 
231 #define UV1_LOCAL_MMR_BASE		0xf4000000UL
232 #define UV1_GLOBAL_MMR32_BASE		0xf8000000UL
233 #define UV1_LOCAL_MMR_SIZE		(64UL * 1024 * 1024)
234 #define UV1_GLOBAL_MMR32_SIZE		(64UL * 1024 * 1024)
235 
236 #define UV2_LOCAL_MMR_BASE		0xfa000000UL
237 #define UV2_GLOBAL_MMR32_BASE		0xfc000000UL
238 #define UV2_LOCAL_MMR_SIZE		(32UL * 1024 * 1024)
239 #define UV2_GLOBAL_MMR32_SIZE		(32UL * 1024 * 1024)
240 
241 #define UV3_LOCAL_MMR_BASE		0xfa000000UL
242 #define UV3_GLOBAL_MMR32_BASE		0xfc000000UL
243 #define UV3_LOCAL_MMR_SIZE		(32UL * 1024 * 1024)
244 #define UV3_GLOBAL_MMR32_SIZE		(32UL * 1024 * 1024)
245 
246 #define UV_LOCAL_MMR_BASE		(is_uv1_hub() ? UV1_LOCAL_MMR_BASE : \
247 					(is_uv2_hub() ? UV2_LOCAL_MMR_BASE : \
248 							UV3_LOCAL_MMR_BASE))
249 #define UV_GLOBAL_MMR32_BASE		(is_uv1_hub() ? UV1_GLOBAL_MMR32_BASE :\
250 					(is_uv2_hub() ? UV2_GLOBAL_MMR32_BASE :\
251 							UV3_GLOBAL_MMR32_BASE))
252 #define UV_LOCAL_MMR_SIZE		(is_uv1_hub() ? UV1_LOCAL_MMR_SIZE : \
253 					(is_uv2_hub() ? UV2_LOCAL_MMR_SIZE : \
254 							UV3_LOCAL_MMR_SIZE))
255 #define UV_GLOBAL_MMR32_SIZE		(is_uv1_hub() ? UV1_GLOBAL_MMR32_SIZE :\
256 					(is_uv2_hub() ? UV2_GLOBAL_MMR32_SIZE :\
257 							UV3_GLOBAL_MMR32_SIZE))
258 #define UV_GLOBAL_MMR64_BASE		(uv_hub_info->global_mmr_base)
259 
260 #define UV_GLOBAL_GRU_MMR_BASE		0x4000000
261 
262 #define UV_GLOBAL_MMR32_PNODE_SHIFT	15
263 #define UV_GLOBAL_MMR64_PNODE_SHIFT	26
264 
265 #define UV_GLOBAL_MMR32_PNODE_BITS(p)	((p) << (UV_GLOBAL_MMR32_PNODE_SHIFT))
266 
267 #define UV_GLOBAL_MMR64_PNODE_BITS(p)					\
268 	(((unsigned long)(p)) << UV_GLOBAL_MMR64_PNODE_SHIFT)
269 
270 #define UVH_APICID		0x002D0E00L
271 #define UV_APIC_PNODE_SHIFT	6
272 
273 #define UV_APICID_HIBIT_MASK	0xffff0000
274 
275 /* Local Bus from cpu's perspective */
276 #define LOCAL_BUS_BASE		0x1c00000
277 #define LOCAL_BUS_SIZE		(4 * 1024 * 1024)
278 
279 /*
280  * System Controller Interface Reg
281  *
282  * Note there are NO leds on a UV system.  This register is only
283  * used by the system controller to monitor system-wide operation.
284  * There are 64 regs per node.  With Nahelem cpus (2 cores per node,
285  * 8 cpus per core, 2 threads per cpu) there are 32 cpu threads on
286  * a node.
287  *
288  * The window is located at top of ACPI MMR space
289  */
290 #define SCIR_WINDOW_COUNT	64
291 #define SCIR_LOCAL_MMR_BASE	(LOCAL_BUS_BASE + \
292 				 LOCAL_BUS_SIZE - \
293 				 SCIR_WINDOW_COUNT)
294 
295 #define SCIR_CPU_HEARTBEAT	0x01	/* timer interrupt */
296 #define SCIR_CPU_ACTIVITY	0x02	/* not idle */
297 #define SCIR_CPU_HB_INTERVAL	(HZ)	/* once per second */
298 
299 /* Loop through all installed blades */
300 #define for_each_possible_blade(bid)		\
301 	for ((bid) = 0; (bid) < uv_num_possible_blades(); (bid)++)
302 
303 /*
304  * Macros for converting between kernel virtual addresses, socket local physical
305  * addresses, and UV global physical addresses.
306  *	Note: use the standard __pa() & __va() macros for converting
307  *	      between socket virtual and socket physical addresses.
308  */
309 
310 /* socket phys RAM --> UV global physical address */
uv_soc_phys_ram_to_gpa(unsigned long paddr)311 static inline unsigned long uv_soc_phys_ram_to_gpa(unsigned long paddr)
312 {
313 	if (paddr < uv_hub_info->lowmem_remap_top)
314 		paddr |= uv_hub_info->lowmem_remap_base;
315 	paddr |= uv_hub_info->gnode_upper;
316 	paddr = ((paddr << uv_hub_info->m_shift) >> uv_hub_info->m_shift) |
317 		((paddr >> uv_hub_info->m_val) << uv_hub_info->n_lshift);
318 	return paddr;
319 }
320 
321 
322 /* socket virtual --> UV global physical address */
uv_gpa(void * v)323 static inline unsigned long uv_gpa(void *v)
324 {
325 	return uv_soc_phys_ram_to_gpa(__pa(v));
326 }
327 
328 /* Top two bits indicate the requested address is in MMR space.  */
329 static inline int
uv_gpa_in_mmr_space(unsigned long gpa)330 uv_gpa_in_mmr_space(unsigned long gpa)
331 {
332 	return (gpa >> 62) == 0x3UL;
333 }
334 
335 /* UV global physical address --> socket phys RAM */
uv_gpa_to_soc_phys_ram(unsigned long gpa)336 static inline unsigned long uv_gpa_to_soc_phys_ram(unsigned long gpa)
337 {
338 	unsigned long paddr;
339 	unsigned long remap_base = uv_hub_info->lowmem_remap_base;
340 	unsigned long remap_top =  uv_hub_info->lowmem_remap_top;
341 
342 	gpa = ((gpa << uv_hub_info->m_shift) >> uv_hub_info->m_shift) |
343 		((gpa >> uv_hub_info->n_lshift) << uv_hub_info->m_val);
344 	paddr = gpa & uv_hub_info->gpa_mask;
345 	if (paddr >= remap_base && paddr < remap_base + remap_top)
346 		paddr -= remap_base;
347 	return paddr;
348 }
349 
350 
351 /* gpa -> pnode */
uv_gpa_to_gnode(unsigned long gpa)352 static inline unsigned long uv_gpa_to_gnode(unsigned long gpa)
353 {
354 	return gpa >> uv_hub_info->n_lshift;
355 }
356 
357 /* gpa -> pnode */
uv_gpa_to_pnode(unsigned long gpa)358 static inline int uv_gpa_to_pnode(unsigned long gpa)
359 {
360 	unsigned long n_mask = (1UL << uv_hub_info->n_val) - 1;
361 
362 	return uv_gpa_to_gnode(gpa) & n_mask;
363 }
364 
365 /* gpa -> node offset*/
uv_gpa_to_offset(unsigned long gpa)366 static inline unsigned long uv_gpa_to_offset(unsigned long gpa)
367 {
368 	return (gpa << uv_hub_info->m_shift) >> uv_hub_info->m_shift;
369 }
370 
371 /* pnode, offset --> socket virtual */
uv_pnode_offset_to_vaddr(int pnode,unsigned long offset)372 static inline void *uv_pnode_offset_to_vaddr(int pnode, unsigned long offset)
373 {
374 	return __va(((unsigned long)pnode << uv_hub_info->m_val) | offset);
375 }
376 
377 
378 /*
379  * Extract a PNODE from an APICID (full apicid, not processor subset)
380  */
uv_apicid_to_pnode(int apicid)381 static inline int uv_apicid_to_pnode(int apicid)
382 {
383 	return (apicid >> uv_hub_info->apic_pnode_shift);
384 }
385 
386 /*
387  * Convert an apicid to the socket number on the blade
388  */
uv_apicid_to_socket(int apicid)389 static inline int uv_apicid_to_socket(int apicid)
390 {
391 	if (is_uv1_hub())
392 		return (apicid >> (uv_hub_info->apic_pnode_shift - 1)) & 1;
393 	else
394 		return 0;
395 }
396 
397 /*
398  * Access global MMRs using the low memory MMR32 space. This region supports
399  * faster MMR access but not all MMRs are accessible in this space.
400  */
uv_global_mmr32_address(int pnode,unsigned long offset)401 static inline unsigned long *uv_global_mmr32_address(int pnode, unsigned long offset)
402 {
403 	return __va(UV_GLOBAL_MMR32_BASE |
404 		       UV_GLOBAL_MMR32_PNODE_BITS(pnode) | offset);
405 }
406 
uv_write_global_mmr32(int pnode,unsigned long offset,unsigned long val)407 static inline void uv_write_global_mmr32(int pnode, unsigned long offset, unsigned long val)
408 {
409 	writeq(val, uv_global_mmr32_address(pnode, offset));
410 }
411 
uv_read_global_mmr32(int pnode,unsigned long offset)412 static inline unsigned long uv_read_global_mmr32(int pnode, unsigned long offset)
413 {
414 	return readq(uv_global_mmr32_address(pnode, offset));
415 }
416 
417 /*
418  * Access Global MMR space using the MMR space located at the top of physical
419  * memory.
420  */
uv_global_mmr64_address(int pnode,unsigned long offset)421 static inline volatile void __iomem *uv_global_mmr64_address(int pnode, unsigned long offset)
422 {
423 	return __va(UV_GLOBAL_MMR64_BASE |
424 		    UV_GLOBAL_MMR64_PNODE_BITS(pnode) | offset);
425 }
426 
uv_write_global_mmr64(int pnode,unsigned long offset,unsigned long val)427 static inline void uv_write_global_mmr64(int pnode, unsigned long offset, unsigned long val)
428 {
429 	writeq(val, uv_global_mmr64_address(pnode, offset));
430 }
431 
uv_read_global_mmr64(int pnode,unsigned long offset)432 static inline unsigned long uv_read_global_mmr64(int pnode, unsigned long offset)
433 {
434 	return readq(uv_global_mmr64_address(pnode, offset));
435 }
436 
437 /*
438  * Global MMR space addresses when referenced by the GRU. (GRU does
439  * NOT use socket addressing).
440  */
uv_global_gru_mmr_address(int pnode,unsigned long offset)441 static inline unsigned long uv_global_gru_mmr_address(int pnode, unsigned long offset)
442 {
443 	return UV_GLOBAL_GRU_MMR_BASE | offset |
444 		((unsigned long)pnode << uv_hub_info->m_val);
445 }
446 
uv_write_global_mmr8(int pnode,unsigned long offset,unsigned char val)447 static inline void uv_write_global_mmr8(int pnode, unsigned long offset, unsigned char val)
448 {
449 	writeb(val, uv_global_mmr64_address(pnode, offset));
450 }
451 
uv_read_global_mmr8(int pnode,unsigned long offset)452 static inline unsigned char uv_read_global_mmr8(int pnode, unsigned long offset)
453 {
454 	return readb(uv_global_mmr64_address(pnode, offset));
455 }
456 
457 /*
458  * Access hub local MMRs. Faster than using global space but only local MMRs
459  * are accessible.
460  */
uv_local_mmr_address(unsigned long offset)461 static inline unsigned long *uv_local_mmr_address(unsigned long offset)
462 {
463 	return __va(UV_LOCAL_MMR_BASE | offset);
464 }
465 
uv_read_local_mmr(unsigned long offset)466 static inline unsigned long uv_read_local_mmr(unsigned long offset)
467 {
468 	return readq(uv_local_mmr_address(offset));
469 }
470 
uv_write_local_mmr(unsigned long offset,unsigned long val)471 static inline void uv_write_local_mmr(unsigned long offset, unsigned long val)
472 {
473 	writeq(val, uv_local_mmr_address(offset));
474 }
475 
uv_read_local_mmr8(unsigned long offset)476 static inline unsigned char uv_read_local_mmr8(unsigned long offset)
477 {
478 	return readb(uv_local_mmr_address(offset));
479 }
480 
uv_write_local_mmr8(unsigned long offset,unsigned char val)481 static inline void uv_write_local_mmr8(unsigned long offset, unsigned char val)
482 {
483 	writeb(val, uv_local_mmr_address(offset));
484 }
485 
486 /*
487  * Structures and definitions for converting between cpu, node, pnode, and blade
488  * numbers.
489  */
490 struct uv_blade_info {
491 	unsigned short	nr_possible_cpus;
492 	unsigned short	nr_online_cpus;
493 	unsigned short	pnode;
494 	short		memory_nid;
495 	spinlock_t	nmi_lock;	/* obsolete, see uv_hub_nmi */
496 	unsigned long	nmi_count;	/* obsolete, see uv_hub_nmi */
497 };
498 extern struct uv_blade_info *uv_blade_info;
499 extern short *uv_node_to_blade;
500 extern short *uv_cpu_to_blade;
501 extern short uv_possible_blades;
502 
503 /* Blade-local cpu number of current cpu. Numbered 0 .. <# cpus on the blade> */
uv_blade_processor_id(void)504 static inline int uv_blade_processor_id(void)
505 {
506 	return uv_hub_info->blade_processor_id;
507 }
508 
509 /* Blade number of current cpu. Numnbered 0 .. <#blades -1> */
uv_numa_blade_id(void)510 static inline int uv_numa_blade_id(void)
511 {
512 	return uv_hub_info->numa_blade_id;
513 }
514 
515 /* Convert a cpu number to the the UV blade number */
uv_cpu_to_blade_id(int cpu)516 static inline int uv_cpu_to_blade_id(int cpu)
517 {
518 	return uv_cpu_to_blade[cpu];
519 }
520 
521 /* Convert linux node number to the UV blade number */
uv_node_to_blade_id(int nid)522 static inline int uv_node_to_blade_id(int nid)
523 {
524 	return uv_node_to_blade[nid];
525 }
526 
527 /* Convert a blade id to the PNODE of the blade */
uv_blade_to_pnode(int bid)528 static inline int uv_blade_to_pnode(int bid)
529 {
530 	return uv_blade_info[bid].pnode;
531 }
532 
533 /* Nid of memory node on blade. -1 if no blade-local memory */
uv_blade_to_memory_nid(int bid)534 static inline int uv_blade_to_memory_nid(int bid)
535 {
536 	return uv_blade_info[bid].memory_nid;
537 }
538 
539 /* Determine the number of possible cpus on a blade */
uv_blade_nr_possible_cpus(int bid)540 static inline int uv_blade_nr_possible_cpus(int bid)
541 {
542 	return uv_blade_info[bid].nr_possible_cpus;
543 }
544 
545 /* Determine the number of online cpus on a blade */
uv_blade_nr_online_cpus(int bid)546 static inline int uv_blade_nr_online_cpus(int bid)
547 {
548 	return uv_blade_info[bid].nr_online_cpus;
549 }
550 
551 /* Convert a cpu id to the PNODE of the blade containing the cpu */
uv_cpu_to_pnode(int cpu)552 static inline int uv_cpu_to_pnode(int cpu)
553 {
554 	return uv_blade_info[uv_cpu_to_blade_id(cpu)].pnode;
555 }
556 
557 /* Convert a linux node number to the PNODE of the blade */
uv_node_to_pnode(int nid)558 static inline int uv_node_to_pnode(int nid)
559 {
560 	return uv_blade_info[uv_node_to_blade_id(nid)].pnode;
561 }
562 
563 /* Maximum possible number of blades */
uv_num_possible_blades(void)564 static inline int uv_num_possible_blades(void)
565 {
566 	return uv_possible_blades;
567 }
568 
569 /* Per Hub NMI support */
570 extern void uv_nmi_setup(void);
571 
572 /* BMC sets a bit this MMR non-zero before sending an NMI */
573 #define UVH_NMI_MMR		UVH_SCRATCH5
574 #define UVH_NMI_MMR_CLEAR	UVH_SCRATCH5_ALIAS
575 #define UVH_NMI_MMR_SHIFT	63
576 #define	UVH_NMI_MMR_TYPE	"SCRATCH5"
577 
578 /* Newer SMM NMI handler, not present in all systems */
579 #define UVH_NMI_MMRX		UVH_EVENT_OCCURRED0
580 #define UVH_NMI_MMRX_CLEAR	UVH_EVENT_OCCURRED0_ALIAS
581 #define UVH_NMI_MMRX_SHIFT	(is_uv1_hub() ? \
582 					UV1H_EVENT_OCCURRED0_EXTIO_INT0_SHFT :\
583 					UVXH_EVENT_OCCURRED0_EXTIO_INT0_SHFT)
584 #define	UVH_NMI_MMRX_TYPE	"EXTIO_INT0"
585 
586 /* Non-zero indicates newer SMM NMI handler present */
587 #define UVH_NMI_MMRX_SUPPORTED	UVH_EXTIO_INT0_BROADCAST
588 
589 /* Indicates to BIOS that we want to use the newer SMM NMI handler */
590 #define UVH_NMI_MMRX_REQ	UVH_SCRATCH5_ALIAS_2
591 #define UVH_NMI_MMRX_REQ_SHIFT	62
592 
593 struct uv_hub_nmi_s {
594 	raw_spinlock_t	nmi_lock;
595 	atomic_t	in_nmi;		/* flag this node in UV NMI IRQ */
596 	atomic_t	cpu_owner;	/* last locker of this struct */
597 	atomic_t	read_mmr_count;	/* count of MMR reads */
598 	atomic_t	nmi_count;	/* count of true UV NMIs */
599 	unsigned long	nmi_value;	/* last value read from NMI MMR */
600 };
601 
602 struct uv_cpu_nmi_s {
603 	struct uv_hub_nmi_s	*hub;
604 	int			state;
605 	int			pinging;
606 	int			queries;
607 	int			pings;
608 };
609 
610 DECLARE_PER_CPU(struct uv_cpu_nmi_s, uv_cpu_nmi);
611 
612 #define uv_hub_nmi			this_cpu_read(uv_cpu_nmi.hub)
613 #define uv_cpu_nmi_per(cpu)		(per_cpu(uv_cpu_nmi, cpu))
614 #define uv_hub_nmi_per(cpu)		(uv_cpu_nmi_per(cpu).hub)
615 
616 /* uv_cpu_nmi_states */
617 #define	UV_NMI_STATE_OUT		0
618 #define	UV_NMI_STATE_IN			1
619 #define	UV_NMI_STATE_DUMP		2
620 #define	UV_NMI_STATE_DUMP_DONE		3
621 
622 /* Update SCIR state */
uv_set_scir_bits(unsigned char value)623 static inline void uv_set_scir_bits(unsigned char value)
624 {
625 	if (uv_hub_info->scir.state != value) {
626 		uv_hub_info->scir.state = value;
627 		uv_write_local_mmr8(uv_hub_info->scir.offset, value);
628 	}
629 }
630 
uv_scir_offset(int apicid)631 static inline unsigned long uv_scir_offset(int apicid)
632 {
633 	return SCIR_LOCAL_MMR_BASE | (apicid & 0x3f);
634 }
635 
uv_set_cpu_scir_bits(int cpu,unsigned char value)636 static inline void uv_set_cpu_scir_bits(int cpu, unsigned char value)
637 {
638 	if (uv_cpu_hub_info(cpu)->scir.state != value) {
639 		uv_write_global_mmr8(uv_cpu_to_pnode(cpu),
640 				uv_cpu_hub_info(cpu)->scir.offset, value);
641 		uv_cpu_hub_info(cpu)->scir.state = value;
642 	}
643 }
644 
645 extern unsigned int uv_apicid_hibits;
uv_hub_ipi_value(int apicid,int vector,int mode)646 static unsigned long uv_hub_ipi_value(int apicid, int vector, int mode)
647 {
648 	apicid |= uv_apicid_hibits;
649 	return (1UL << UVH_IPI_INT_SEND_SHFT) |
650 			((apicid) << UVH_IPI_INT_APIC_ID_SHFT) |
651 			(mode << UVH_IPI_INT_DELIVERY_MODE_SHFT) |
652 			(vector << UVH_IPI_INT_VECTOR_SHFT);
653 }
654 
uv_hub_send_ipi(int pnode,int apicid,int vector)655 static inline void uv_hub_send_ipi(int pnode, int apicid, int vector)
656 {
657 	unsigned long val;
658 	unsigned long dmode = dest_Fixed;
659 
660 	if (vector == NMI_VECTOR)
661 		dmode = dest_NMI;
662 
663 	val = uv_hub_ipi_value(apicid, vector, dmode);
664 	uv_write_global_mmr64(pnode, UVH_IPI_INT, val);
665 }
666 
667 /*
668  * Get the minimum revision number of the hub chips within the partition.
669  *     1 - UV1 rev 1.0 initial silicon
670  *     2 - UV1 rev 2.0 production silicon
671  *     3 - UV2 rev 1.0 initial silicon
672  *     5 - UV3 rev 1.0 initial silicon
673  */
uv_get_min_hub_revision_id(void)674 static inline int uv_get_min_hub_revision_id(void)
675 {
676 	return uv_hub_info->hub_revision;
677 }
678 
679 #endif /* CONFIG_X86_64 */
680 #endif /* _ASM_X86_UV_UV_HUB_H */
681