| /arch/arm64/crypto/ |
| D | aes-ce-ccm-core.S | 23 ld1 {v0.16b}, [x0] /* load mac */
34 eor v0.16b, v0.16b, v1.16b
46 3: aese v0.16b, v4.16b
47 aesmc v0.16b, v0.16b
49 aese v0.16b, v5.16b
50 aesmc v0.16b, v0.16b
53 aese v0.16b, v3.16b
54 aesmc v0.16b, v0.16b
57 aese v0.16b, v4.16b
59 eor v0.16b, v0.16b, v5.16b /* final round */
[all …]
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| D | aes-modes.S | 43 encrypt_block2x v0, v1, w3, x2, x6, w7
48 decrypt_block2x v0, v1, w3, x2, x6, w7
55 encrypt_block4x v0, v1, v2, v3, w3, x2, x6, w7
60 decrypt_block4x v0, v1, v2, v3, w3, x2, x6, w7
89 encrypt_block2x v0, v1, w3, x2, x6, w7
93 decrypt_block2x v0, v1, w3, x2, x6, w7
97 encrypt_block4x v0, v1, v2, v3, w3, x2, x6, w7
101 decrypt_block4x v0, v1, v2, v3, w3, x2, x6, w7
124 ld1 {v0.16b-v1.16b}, [x1], #32 /* get 2 pt blocks */
126 st1 {v0.16b-v1.16b}, [x0], #32
[all …]
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| /arch/mips/include/asm/mach-cavium-octeon/ |
| D | kernel-entry-init.h | 30 dmfc0 v0, CP0_CVMMEMCTL_REG
32 dins v0, $0, 0, 6
33 ori v0, CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE
34 dmtc0 v0, CP0_CVMMEMCTL_REG # Write the cavium mem control register
35 dmfc0 v0, CP0_CVMCTL_REG # Read the cavium control register
38 or v0, v0, 0x5001
39 xor v0, v0, 0x1001
43 and v0, v0, v1
44 ori v0, v0, (6 << 7)
64 or v0, v0, 0x2000 # Set IPREF bit.
[all …]
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| /arch/mips/lib/ |
| D | strncpy_user.S | 33 LONG_L v0, TI_ADDR_LIMIT($28) # pointer ok?
34 and v0, a1
35 bnez v0, .Lfault\@
41 1: EX(lbu, v0, (v1), .Lfault\@)
43 1: EX(lbue, v0, (v1), .Lfault\@)
47 sb v0, (a0)
48 beqz v0, 2f
52 2: PTR_ADDU v0, a1, t0
53 xor v0, a1
54 bltz v0, .Lfault\@
[all …]
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| D | strnlen_user.S | 30 LONG_L v0, TI_ADDR_LIMIT($28) # pointer ok?
31 and v0, a0
32 bnez v0, .Lfault\@
35 move v0, a0
42 beq v0, a1, 1f # limit reached?
44 EX(lb, t0, (v0), .Lfault\@)
46 EX(lbe, t0, (v0), .Lfault\@)
52 PTR_ADDIU v0, 1
54 PTR_ADDU v0, AT
58 PTR_SUBU v0, a0
[all …]
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| D | strlen_user.S | 27 LONG_L v0, TI_ADDR_LIMIT($28) # pointer ok?
28 and v0, a0
29 bnez v0, .Lfault\@
31 move v0, a0
33 1: EX(lbu, v1, (v0), .Lfault\@)
35 1: EX(lbue, v1, (v0), .Lfault\@)
37 PTR_ADDIU v0, 1
39 PTR_SUBU v0, a0
43 .Lfault\@: move v0, zero
|
| /arch/ia64/include/asm/sn/ |
| D | sn_sal.h | 185 ret_stuff.v0 = 0; in ia64_sn_get_console_nasid()
194 return ret_stuff.v0; in ia64_sn_get_console_nasid()
207 ret_stuff.v0 = 0; in ia64_sn_get_master_baseio_nasid()
216 return ret_stuff.v0; in ia64_sn_get_master_baseio_nasid()
225 ret_stuff.v0 = 0; in ia64_sn_get_klconfig_addr()
229 return ret_stuff.v0 ? __va(ret_stuff.v0) : NULL; in ia64_sn_get_klconfig_addr()
241 ret_stuff.v0 = 0; in ia64_sn_console_getc()
247 *ch = (int)ret_stuff.v0; in ia64_sn_console_getc()
263 ret_stuff.v0 = 0; in ia64_sn_console_readc()
269 return ret_stuff.v0; in ia64_sn_console_readc()
[all …]
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| /arch/mips/include/asm/mach-malta/ |
| D | kernel-entry-init.h | 113 PTR_LA v0, 0x9fc00534 /* YAMON print */
114 lw v0, (v0)
117 jal v0
119 PTR_LA v0, 0x9fc00520 /* YAMON exit */
120 lw v0, (v0)
122 jal v0
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| /arch/alpha/include/asm/ |
| D | pal.h | 122 register unsigned long v0 __asm__("$0"); in qemu_get_walltime()
126 : "=r"(v0), "+r"(a0) in qemu_get_walltime()
130 return v0; in qemu_get_walltime()
136 register unsigned long v0 __asm__("$0"); in qemu_get_alarm()
140 : "=r"(v0), "+r"(a0) in qemu_get_alarm()
144 return v0; in qemu_get_alarm()
174 register unsigned long v0 __asm__("$0"); in qemu_get_vmtime()
178 : "=r"(v0), "+r"(a0) in qemu_get_vmtime()
182 return v0; in qemu_get_vmtime()
|
| /arch/alpha/lib/ |
| D | strchr.S | 24 andnot a0, 7, v0 # .. e1 : align our loop pointer
40 $loop: ldq t0, 8(v0) # e0 :
41 addq v0, 8, v0 # .. e1 :
62 addq v0, t4, v0 # .. e1 :
63 addq v0, t2, v0 # e0 :
67 mov zero, v0 # e0 :
|
| D | strrchr.S | 28 andnot a0, 7, v0 # .. e1 : align source addr
44 ldq t0, 8(v0) # e0 : load next quadword
45 cmovne t3, v0, t6 # .. e1 : save previous comparisons match
47 addq v0, 8, v0 # .. e1 :
62 cmovne t3, v0, t6 # e0 :
79 addq t6, t0, v0 # .. e1 : add our aligned base ptr to the mix
80 addq v0, t1, v0 # e0 :
84 mov zero, v0 # e0 :
|
| D | ev67-strchr.S | 38 andnot a0, 7, v0 # E : align our loop pointer
68 $loop: ldq t0, 8(v0) # L : Latency=3
69 addq v0, 8, v0 # E :
81 addq v0, a2, v0 # E : Add in the bit number from above
83 cmoveq t1, $31, v0 # E : Two mapping slots, latency = 2
|
| D | ev67-strrchr.S | 44 andnot a0, 7, v0 # E : align source addr
66 ldq t0, 8(v0) # L : load next quadword
67 cmovne t3, v0, t6 # E : save previous comparisons match
73 addq v0, 8, v0 # E :
93 cmovne t3, v0, t6 # E :
104 addq t6, t5, v0 # E : and add to quadword address
|
| /arch/ia64/include/asm/ |
| D | pal.h | 780 u64 v0; member
888 features_avail->pal_bus_features_val = iprv.v0; in ia64_pal_bus_get_features()
915 conf->pcci_info_1.pcci1_data = iprv.v0; in ia64_pal_cache_config_info()
933 prot->pcp_info[0].pcpi_data = iprv.v0 & 0xffffffff; in ia64_pal_cache_prot_info()
934 prot->pcp_info[1].pcpi_data = iprv.v0 >> 32; in ia64_pal_cache_prot_info()
953 *vector = iprv.v0; in ia64_pal_cache_flush()
998 *cache_levels = iprv.v0; in ia64_pal_cache_summary()
1023 *buffer_size = iprv.v0; in ia64_pal_copy_info()
1036 *pal_proc_offset = iprv.v0; in ia64_pal_copy_pal()
1047 *inst_regs = iprv.v0; in ia64_pal_debug_info()
[all …]
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| /arch/mips/netlogic/common/ |
| D | reset.S | 106 sll v0, t2, 5
108 ori v1, v0, 0x3 /* way0 | write_enable | write_active */
116 ori v1, v0, 0x7 /* way1 | write_enable | write_active */
234 mfc0 v0, CP0_EBASE
235 andi v0, 0x3ff /* v0 <- node/core */
241 andi v1, v0, 0x3 /* v1 <- thread id */
257 beqz v0, 4f /* boot cpu (cpuid == 0)? */
272 sll v1, v0, 2
|
| /arch/powerpc/lib/ |
| D | memcpy_power7.S | 331 lvx v0,r4,r9
334 stvx v0,r3,r9
341 lvx v0,r4,r11
346 stvx v0,r3,r11
376 lvx v0,r4,r16
385 stvx v0,r3,r16
402 lvx v0,r4,r11
407 stvx v0,r3,r11
412 lvx v0,r4,r9
415 stvx v0,r3,r9
[all …]
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| D | copyuser_power7.S | 398 err3; lvx v0,r4,r9
401 err3; stvx v0,r3,r9
408 err3; lvx v0,r4,r11
413 err3; stvx v0,r3,r11
443 err4; lvx v0,r4,r16
452 err4; stvx v0,r3,r16
469 err3; lvx v0,r4,r11
474 err3; stvx v0,r3,r11
479 err3; lvx v0,r4,r9
482 err3; stvx v0,r3,r9
[all …]
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| /arch/mips/kernel/ |
| D | scall32-o32.S | 91 subu v0, v0, __NR_O32_Linux # check syscall number
92 sltiu t0, v0, __NR_O32_Linux_syscalls + 1
95 sll t0, v0, 2
105 sltu t0, t0, v0
110 negu v0 # error
112 1: sw v0, PT_R2(sp) # result
127 move a1, v0
128 subu t2, v0, __NR_O32_Linux
134 bltz v0, 1f # seccomp failed? Skip syscall
137 lw v0, PT_R2(sp) # Restore syscall (maybe modified)
[all …]
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| D | scall64-o32.S | 36 dsubu t0, v0, __NR_O32_Linux # check syscall number
43 move a1, v0
88 dsll t0, v0, 3 # offset into table
94 sltu t0, t0, v0
99 dnegu v0 # error
101 1: sd v0, PT_R2(sp) # result
125 subu t1, v0, __NR_O32_Linux
126 move a1, v0
133 bltz v0, 1f # seccomp failed? Skip syscall
136 ld v0, PT_R2(sp) # Restore syscall (maybe modified)
[all …]
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| D | octeon_switch.S | 87 move v0, a0
148 mfc0 v0, $15,0 /* Get the processor ID register */
153 beq v0, v1, 2f
161 subu v1, v0, v1 /* prid - lowest OCTEON III PrId */
316 li v0, 0x000d0000 /* This is the processor ID of Octeon Pass1 */
318 bne v0, t3, 3f /* Skip the next stuff for non-pass1 */
346 ori v0, v0, 0x9500 /* lowest OCTEON III PrId*/
400 subu v0, t3, v0 /* prid - lowest OCTEON III PrId */
402 bltz v0, done_restore
505 ld v0, PT_MPL(sp) /* MPL0 */
[all …]
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| /arch/mips/vdso/ |
| D | sigreturn.S | 28 li v0, __NR_rt_sigreturn
43 li v0, __NR_sigreturn
|
| /arch/ia64/sn/pci/pcibr/ |
| D | pcibr_provider.c | 34 ret_stuff.v0 = 0; in sal_pcibr_slot_enable()
42 return (int)ret_stuff.v0; in sal_pcibr_slot_enable()
54 ret_stuff.v0 = 0; in sal_pcibr_slot_disable()
62 return (int)ret_stuff.v0; in sal_pcibr_slot_disable()
71 ret_stuff.v0 = 0; in sal_pcibr_error_interrupt()
79 return (int)ret_stuff.v0; in sal_pcibr_error_interrupt()
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| /arch/mips/kvm/ |
| D | locore.S | 98 mflo v0
99 LONG_S v0, PT_LO(k1)
104 mfc0 v0, CP0_STATUS
105 LONG_S v0, PT_STATUS(k1)
149 andi v0, v0, ST0_IM
150 or k0, k0, v0
341 mfc0 v0, CP0_STATUS
344 or k0, v0, ST0_BEV
358 and v1, v0, ST0_CU1
391 and v0, v0, ~(ST0_EXL | KSU_USER | ST0_IE)
[all …]
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| /arch/powerpc/kernel/ |
| D | vector.S | 27 lvx v0,r10,r3
28 mtvscr v0
55 lvx v0,r4,r3
56 mtvscr v0
66 mfvscr v0
68 stvx v0, r4, r3
107 mfvscr v0
109 stvx v0,r10,r6
145 lvx v0,r10,r6
146 mtvscr v0
[all …]
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| /arch/ia64/sn/kernel/ |
| D | io_init.c | 38 ret_stuff.v0 = 0; in sal_get_hubdev_info()
43 return ret_stuff.v0; in sal_get_hubdev_info()
53 ret_stuff.v0 = 0; in sal_get_pcibus_info()
58 return ret_stuff.v0; in sal_get_pcibus_info()
70 ret_stuff.v0 = 0; in sal_get_pcidev_info()
77 return ret_stuff.v0; in sal_get_pcidev_info()
|