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Searched refs:wrmsrl_safe (Results 1 – 12 of 12) sorted by relevance

/arch/x86/kernel/cpu/
Dperf_event_p6.c163 (void)wrmsrl_safe(hwc->config_base, val); in p6_pmu_disable_event()
180 (void)wrmsrl_safe(hwc->config_base, val); in p6_pmu_enable_event()
Dperf_event_knc.c184 (void)wrmsrl_safe(hwc->config_base + hwc->idx, val); in knc_pmu_disable_event()
195 (void)wrmsrl_safe(hwc->config_base + hwc->idx, val); in knc_pmu_enable_event()
Dperf_event_p4.c912 (void)wrmsrl_safe(hwc->config_base, in p4_pmu_disable_event()
945 (void)wrmsrl_safe(MSR_IA32_PEBS_ENABLE, (u64)bind->metric_pebs); in p4_pmu_enable_pebs()
946 (void)wrmsrl_safe(MSR_P4_PEBS_MATRIX_VERT, (u64)bind->metric_vert); in p4_pmu_enable_pebs()
980 (void)wrmsrl_safe(escr_addr, escr_conf); in p4_pmu_enable_event()
981 (void)wrmsrl_safe(hwc->config_base, in p4_pmu_enable_event()
1372 wrmsrl_safe(reg, 0ULL); in p4_pmu_init()
Dcommon.c1524 wrmsrl_safe(MSR_IA32_SYSENTER_CS, (u64)__KERNEL_CS); in syscall_init()
1525 wrmsrl_safe(MSR_IA32_SYSENTER_ESP, 0ULL); in syscall_init()
1526 wrmsrl_safe(MSR_IA32_SYSENTER_EIP, (u64)entry_SYSENTER_compat); in syscall_init()
1529 wrmsrl_safe(MSR_IA32_SYSENTER_CS, (u64)GDT_ENTRY_INVALID_SEG); in syscall_init()
1530 wrmsrl_safe(MSR_IA32_SYSENTER_ESP, 0ULL); in syscall_init()
1531 wrmsrl_safe(MSR_IA32_SYSENTER_EIP, 0ULL); in syscall_init()
Damd.c769 wrmsrl_safe(0xc0011021, value); in init_amd_bd()
Dperf_event_intel.c1766 wrmsrl_safe(x86_pmu_config_addr(idx), 0ull); in intel_pmu_reset()
1767 wrmsrl_safe(x86_pmu_event_addr(idx), 0ull); in intel_pmu_reset()
1770 wrmsrl_safe(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, 0ull); in intel_pmu_reset()
3111 if (wrmsrl_safe(msr, val_tmp) || in check_msr()
Dperf_event.c249 ret = wrmsrl_safe(reg, val); in check_hw_exists()
/arch/x86/lib/
Dmsr.c55 return wrmsrl_safe(msr, m->q); in msr_write()
/arch/x86/include/asm/
Dmsr.h243 static inline int wrmsrl_safe(u32 msr, u64 val) in wrmsrl_safe() function
316 return wrmsrl_safe(msr_no, q); in wrmsrl_safe_on_cpu()
/arch/x86/kernel/
Dprocess_64.c530 ret = wrmsrl_safe(MSR_KERNEL_GS_BASE, addr); in do_arch_prctl()
558 ret = wrmsrl_safe(MSR_FS_BASE, addr); in do_arch_prctl()
/arch/x86/kernel/cpu/mcheck/
Dtherm_throt.c389 wrmsrl_safe(MSR_HWP_STATUS, 0); in intel_thermal_interrupt()
/arch/x86/kvm/
Dx86.c267 err = wrmsrl_safe(shared_msrs_global.msrs[slot], value); in kvm_set_shared_msr()