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Searched refs:ADDR_SURF_BANK_WIDTH_4 (Results 1 – 25 of 25) sorted by relevance

/drivers/gpu/drm/amd/amdgpu/
Dgfx_v8_0.c1517 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) | in gfx_v8_0_tiling_mode_table_init()
1523 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) | in gfx_v8_0_tiling_mode_table_init()
1559 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) | in gfx_v8_0_tiling_mode_table_init()
1565 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) | in gfx_v8_0_tiling_mode_table_init()
2407 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) | in gfx_v8_0_tiling_mode_table_init()
2413 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) | in gfx_v8_0_tiling_mode_table_init()
2675 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) | in gfx_v8_0_tiling_mode_table_init()
2681 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) | in gfx_v8_0_tiling_mode_table_init()
Dgfx_v7_0.c1804 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) | in gfx_v7_0_tiling_mode_table_init()
1810 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) | in gfx_v7_0_tiling_mode_table_init()
/drivers/gpu/drm/amd/include/asic_reg/bif/
Dbif_5_1_enum.h960 ADDR_SURF_BANK_WIDTH_4 = 0x2, enumerator
Dbif_5_0_enum.h1090 ADDR_SURF_BANK_WIDTH_4 = 0x2, enumerator
/drivers/gpu/drm/amd/include/asic_reg/gmc/
Dgmc_8_2_enum.h960 ADDR_SURF_BANK_WIDTH_4 = 0x2, enumerator
Dgmc_8_1_enum.h1090 ADDR_SURF_BANK_WIDTH_4 = 0x2, enumerator
/drivers/gpu/drm/amd/include/asic_reg/smu/
Dsmu_8_0_enum.h960 ADDR_SURF_BANK_WIDTH_4 = 0x2, enumerator
Dsmu_7_1_0_enum.h1119 ADDR_SURF_BANK_WIDTH_4 = 0x2, enumerator
Dsmu_7_1_3_enum.h1174 ADDR_SURF_BANK_WIDTH_4 = 0x2, enumerator
Dsmu_7_1_1_enum.h1120 ADDR_SURF_BANK_WIDTH_4 = 0x2, enumerator
Dsmu_7_1_2_enum.h1138 ADDR_SURF_BANK_WIDTH_4 = 0x2, enumerator
/drivers/gpu/drm/amd/include/asic_reg/uvd/
Duvd_6_0_enum.h973 ADDR_SURF_BANK_WIDTH_4 = 0x2, enumerator
Duvd_5_0_enum.h1103 ADDR_SURF_BANK_WIDTH_4 = 0x2, enumerator
/drivers/gpu/drm/amd/include/asic_reg/oss/
Doss_2_4_enum.h1255 ADDR_SURF_BANK_WIDTH_4 = 0x2, enumerator
Doss_3_0_enum.h1389 ADDR_SURF_BANK_WIDTH_4 = 0x2, enumerator
Doss_3_0_1_enum.h1356 ADDR_SURF_BANK_WIDTH_4 = 0x2, enumerator
/drivers/gpu/drm/amd/include/asic_reg/dce/
Ddce_10_0_enum.h1665 ADDR_SURF_BANK_WIDTH_4 = 0x2, enumerator
Ddce_11_0_enum.h5532 ADDR_SURF_BANK_WIDTH_4 = 0x2, enumerator
/drivers/gpu/drm/radeon/
Dsid.h1208 # define ADDR_SURF_BANK_WIDTH_4 2 macro
Dcikd.h1265 # define ADDR_SURF_BANK_WIDTH_4 2 macro
Devergreend.h2175 # define ADDR_SURF_BANK_WIDTH_4 2 macro
Dcik.c3346 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) | in cik_tiling_mode_table_init()
3352 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) | in cik_tiling_mode_table_init()
/drivers/gpu/drm/amd/include/asic_reg/gca/
Dgfx_7_2_enum.h6202 ADDR_SURF_BANK_WIDTH_4 = 0x2, enumerator
Dgfx_8_0_enum.h6750 ADDR_SURF_BANK_WIDTH_4 = 0x2, enumerator
Dgfx_8_1_enum.h6700 ADDR_SURF_BANK_WIDTH_4 = 0x2, enumerator