Searched refs:AR_PHY_TIMING_CTRL4 (Results 1 – 7 of 7) sorted by relevance
| /drivers/net/wireless/ath/ath9k/ |
| D | ar9002_calib.c | 54 REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4(0), in ar9002_hw_setup_calibration()
74 REG_SET_BIT(ah, AR_PHY_TIMING_CTRL4(0), in ar9002_hw_setup_calibration()
87 if (!(REG_READ(ah, AR_PHY_TIMING_CTRL4(0)) & in ar9002_hw_per_calibration()
244 REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4(i), in ar9002_hw_iqcalibrate()
247 REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4(i), in ar9002_hw_iqcalibrate()
256 REG_SET_BIT(ah, AR_PHY_TIMING_CTRL4(0), in ar9002_hw_iqcalibrate()
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| D | ar9002_phy.c | 224 tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0)); in ar9002_hw_spur_mitigate()
232 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), newVal); in ar9002_hw_spur_mitigate()
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| D | ar9002_phy.h | 187 #define AR_PHY_TIMING_CTRL4(_i) (0x9920 + ((_i) << 12)) macro
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| D | eeprom_9287.c | 926 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0) + regChainOffset, in ath9k_hw_ar9287_set_board_values()
927 (REG_READ(ah, AR_PHY_TIMING_CTRL4(0) + regChainOffset) in ath9k_hw_ar9287_set_board_values()
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| D | ar5008_phy.c | 449 tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0)); in ar5008_hw_spur_mitigate()
455 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), new); in ar5008_hw_spur_mitigate()
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| D | eeprom_def.c | 541 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0) + regChainOffset, in ath9k_hw_def_set_board_values()
542 (REG_READ(ah, AR_PHY_TIMING_CTRL4(0) + regChainOffset) & in ath9k_hw_def_set_board_values()
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| D | eeprom_4k.c | 779 REG_RMW(ah, AR_PHY_TIMING_CTRL4(0), in ath9k_hw_4k_set_gain()
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