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Searched refs:BIT0 (Results 1 – 25 of 28) sorted by relevance

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/drivers/net/wireless/realtek/rtlwifi/rtl8821ae/
Dpwrseq.h60 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0 \
63 PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT0, 0},
73 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0 \
118 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x01, BIT0 \
177 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x01, BIT0 \
203 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0 \
269 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0 \
316 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1|BIT0, BIT1|BIT0 \
393 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0 \
411 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0 , BIT0 \
[all …]
/drivers/video/fbdev/via/
Ddvi.c59 viafb_write_reg_mask(SR2A, VIASR, 0x03, BIT0 + BIT1); in viafb_tmds_trasmitter_identify()
66 viafb_write_reg_mask(SR2A, VIASR, 0x03, BIT0 + BIT1); in viafb_tmds_trasmitter_identify()
349 BIT0 + BIT1 + BIT2); in dvi_patch_skew_dvp0()
352 BIT0 + BIT1 + BIT2); in dvi_patch_skew_dvp0()
359 BIT0 + BIT1 + BIT2 + BIT3); in dvi_patch_skew_dvp0()
377 viafb_write_reg_mask(CR99, VIACR, 0x03, BIT0 + BIT1); in dvi_patch_skew_dvp_low()
384 BIT0 + BIT1 + BIT2 + BIT3); in dvi_patch_skew_dvp_low()
391 BIT0 + BIT1 + BIT2 + BIT3); in dvi_patch_skew_dvp_low()
409 viafb_write_reg_mask(CR6B, VIACR, 0x01, BIT0); in viafb_dvi_enable()
410 viafb_write_reg_mask(CR6C, VIACR, 0x21, BIT0 + BIT5); in viafb_dvi_enable()
[all …]
Dlcd.c359 viafb_write_reg_mask(CR79, VIACR, 0x07, BIT0 + BIT1 + BIT2); in load_lcd_scaling()
534 BIT0 + BIT1 + BIT2 + BIT3); in lcd_patch_skew()
577 BIT0 + BIT1 + BIT2); in viafb_lcd_set_mode()
599 viafb_write_reg_mask(CR6A, VIACR, 0x01, BIT0); in viafb_lcd_set_mode()
666 viafb_write_reg_mask(CRD2, VIACR, 0x00, BIT0 + BIT1); in integrated_lvds_enable()
668 viafb_write_reg_mask(CRD2, VIACR, 0x03, BIT0 + BIT1); in integrated_lvds_enable()
675 viafb_write_reg_mask(CR91, VIACR, 0, BIT0); in integrated_lvds_enable()
684 viafb_write_reg_mask(CRD3, VIACR, 0, BIT0); in integrated_lvds_enable()
760 BIT7 + BIT2 + BIT1 + BIT0); in set_lcd_output_path()
859 bdithering = BIT0; in fill_lcd_format()
[all …]
Dvia_utility.c166 viafb_write_reg_mask(SR1A, VIASR, 0x0, BIT0); in viafb_set_gamma_table()
183 viafb_write_reg_mask(SR1A, VIASR, 0x01, BIT0); in viafb_set_gamma_table()
221 viafb_write_reg_mask(SR1A, VIASR, 0x0, BIT0); in viafb_get_gamma_table()
Dhw.c487 viafb_write_reg_mask(CR47, VIACR, 0, BIT0); in viafb_unlock_crt()
964 viafb_write_reg_mask(CR33, VIACR, 0x06, BIT0 + BIT1 + BIT2); in load_fix_bit_crtc_reg()
1001 reg_mask = reg_mask | (BIT0 << j); in viafb_load_reg()
1002 get_bit = (timing_value & (BIT0 << bit_num)); in viafb_load_reg()
1682 viafb_write_reg_mask(SR1A, VIASR, 0x00, BIT0); in viafb_init_dac()
1696 viafb_write_reg_mask(SR1A, VIASR, 0x01, BIT0); in viafb_init_dac()
1703 viafb_write_reg_mask(SR1A, VIASR, 0x00, BIT0); in viafb_init_dac()
Dshare.h28 #define BIT0 0x01 macro
/drivers/scsi/
Ddc395x.h75 #define BIT0 0x00000001 macro
78 #define UNIT_ALLOCATED BIT0
84 #define DASD_SUPPORT BIT0
120 #define RESET_DEV BIT0
125 #define ABORT_DEV_ BIT0
128 #define SRB_OK BIT0
142 #define AUTO_REQSENSE BIT0
173 #define SYNC_NEGO_ENABLE BIT0
629 #define MORE2_DRV BIT0
/drivers/staging/rtl8192e/rtl8192e/
Dr8192E_hw.h140 #define RCR_FILTER_MASK (BIT0 | BIT1 | BIT2 | BIT3 | BIT5 | BIT12 | \
159 #define RCR_AAP BIT0
211 #define SCR_TxUseDK BIT0
238 #define IMR_ROK BIT0
241 #define TPPoll_BKQ BIT0
281 #define AcmHw_HwEn BIT0
289 #define AcmFw_BeqStatus BIT0
342 #define BW_OPMODE_11J BIT0
371 #define RRSR_1M BIT0
/drivers/net/wireless/realtek/rtlwifi/btcoexist/
Dhalbtc8821a2ant.c344 h2c_parameter[0] |= BIT0; /* trigger */ in halbtc8821a2ant_query_bt_info()
628 h2c_parameter[1] |= BIT0; in btc8821a2ant_set_fw_bt_lna_constr()
710 h2c_parameter[0] |= BIT0; in halbtc8821a2ant_set_bt_auto_report()
827 h2c_parameter[1] |= BIT0; in btc8821a2ant_SetSwPenTxRateAdapt()
1028 h2c_parameter[0] |= BIT0;/* function enable */ in halbtc8821a2ant_set_fw_ignore_wlan_act()
2573 if (bt_info_ext&BIT0) { in halbtc8821a2ant_action_a2dp_pan_hs()
2596 if (bt_info_ext&BIT0) { in halbtc8821a2ant_action_a2dp_pan_hs()
2808 if (bt_info_ext&BIT0) { in halbtc8821a2ant_action_pan_edr_a2dp()
2818 if (bt_info_ext&BIT0) { in halbtc8821a2ant_action_pan_edr_a2dp()
2846 if (bt_info_ext&BIT0) { in halbtc8821a2ant_action_pan_edr_a2dp()
[all …]
Dhalbtc8723b1ant.h37 #define BT_INFO_8723B_1ANT_B_CONNECTION BIT0
40 (((_BT_INFO_EXT_&BIT0)) ? true : false)
Dhalbtc8821a1ant.h39 #define BT_INFO_8821A_1ANT_B_CONNECTION BIT0
42 (((_BT_INFO_EXT_&BIT0)) ? true : false)
Dhalbtcoutsrc.h97 #define INTF_INIT BIT0
101 #define ALGO_BT_RSSI_STATE BIT0
113 #define WIFI_STA_CONNECTED BIT0
Dhalbt_precomp.h48 #define BIT0 0x00000001 macro
Dhalbtc8723b2ant.h40 #define BT_INFO_8723B_2ANT_B_CONNECTION BIT0
Dhalbtc8821a2ant.h37 #define BT_INFO_8821A_2ANT_B_CONNECTION BIT0
Dhalbtc8192e2ant.h37 #define BT_INFO_8192E_2ANT_B_CONNECTION BIT0
Dhalbtc8821a1ant.c432 h2c_parameter[0] |= BIT0; /* trigger*/ in halbtc8821a1ant_query_bt_info()
671 h2c_parameter[0] |= BIT0; in halbtc8821a1ant_set_bt_auto_report()
713 h2c_parameter[1] |= BIT0; in btc8821a1ant_set_sw_pen_tx_rate()
840 h2c_parameter[0] |= BIT0; /* function enable*/ in btc8821a1ant_set_fw_ignore_wlan_act()
2363 (bt_info_ext&BIT0) ? in ex_halbtc8821a1ant_display_coex_info()
Dhalbtc8723b1ant.c436 h2c_parameter[0] |= BIT0; /* trigger*/ in halbtc8723b1ant_query_bt_info()
712 h2c_parameter[1] |= BIT0; in btc8723b1ant_set_sw_pen_tx_rate_adapt()
840 h2c_parameter[0] |= BIT0; /* function enable */ in halbtc8723b1ant_SetFwIgnoreWlanAct()
2335 if (u32tmp & BIT0) { in halbtc8723b1ant_init_hw_config()
2523 (bt_info_ext & BIT0) ? "Basic rate" : "EDR rate"); in ex_halbtc8723b1ant_display_coex_info()
/drivers/tty/
Dsynclink_gt.c215 …a).status = cpu_to_le16((b) ? (le16_to_cpu((a).status) | BIT0) : (le16_to_cpu((a).status) & ~BIT0))
222 #define desc_abort(a) (le16_to_cpu((a).status) & BIT0)
383 #define MASK_FRAMING BIT0
425 #define IRQ_MASTER BIT0
1868 status = *(p + 1) & (BIT1 + BIT0); in rx_async()
1872 else if (status & BIT0) in rx_async()
1879 else if (status & BIT0) in rx_async()
2092 if (status & BIT0) { in ri_change()
3898 if (!(rd_reg32(info, RDCSR) & BIT0)) in rdma_reset()
3911 if (!(rd_reg32(info, TDCSR) & BIT0)) in tdma_reset()
[all …]
Dsynclinkmp.c418 #define RXRDYE BIT0
430 #define BRKE BIT0
431 #define IDLD BIT0
2168 while((status = read_reg(info,CST0)) & BIT0) in isr_rxrdy()
2579 if (status & BIT0 << shift) in synclinkmp_interrupt()
2588 if (dmastatus & BIT0 << shift) in synclinkmp_interrupt()
4029 write_reg(info, MD2, (unsigned char)(read_reg(info, MD2) | (BIT1 + BIT0))); in enable_loopback()
4032 info->port_array[0]->ctrlreg_value |= (BIT0 << (info->port_num * 2)); in enable_loopback()
4047 write_reg(info, MD2, (unsigned char)(read_reg(info, MD2) & ~(BIT1 + BIT0))); in enable_loopback()
4417 RegValue |= BIT0; in async_mode()
[all …]
Dsynclink.c496 #define MISC BIT0
515 #define RXSTATUS_DATA_AVAILABLE BIT0
553 #define TXSTATUS_FIFO_EMPTY BIT0
573 #define MISCSTATUS_BRG0_ZERO BIT0
599 #define SICR_BRG0_ZERO BIT0
633 #define TXSTATUS_FIFO_EMPTY BIT0
636 #define DICR_TRANSMIT BIT0
1642 usc_OutDmaReg(info, CDIR, BIT8 | BIT0 ); in mgsl_isr_transmit_dma()
5240 usc_OutReg( info, HCR, (u16)((usc_InReg( info, HCR ) & ~BIT1) | BIT0) ); in usc_enable_loopback()
5303 usc_OutReg( info, HCR, (u16)((usc_InReg( info, HCR ) & ~BIT1) | BIT0) ); in usc_enable_aux_clock()
[all …]
/drivers/staging/rtl8192e/
Drtl819x_Qos.h18 #define BIT0 0x00000001 macro
/drivers/net/ethernet/cirrus/
Dcs89x0.h463 #define BIT0 1 macro
/drivers/char/pcmcia/
Dsynclink_cs.c303 #define IRQ_RXFIFO BIT0 // receive pool full
311 #define PVR_DTR BIT0
684 #define CMD_TXRESET BIT0 // transmit reset
1185 if (gis & (BIT1 | BIT0)) { in mgslpc_isr()
3023 val = read_reg(info, CHA + CCR1) | (BIT2 | BIT1 | BIT0); in loopback_enable()
3037 val = read_reg(info, CHA + MODE) | BIT0; in loopback_enable()
3090 val |= BIT0; in hdlc_mode()
3160 val |= BIT0; in hdlc_mode()
3436 val |= BIT0; in async_mode()
3514 val |= BIT0; /* 7 bits */ in async_mode()
/drivers/net/wireless/realtek/rtlwifi/rtl8192de/
Dreg.h384 #define RRSR_1M BIT0
519 #define WOW_PMEN BIT0 /* Power management Enable. */

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