Searched refs:BIT10 (Results 1 – 10 of 10) sorted by relevance
77 #define BIT10 0x00000400 macro102 #define INT_SEL BIT10161 #define EP2_INT BIT10188 #define EP2_EN BIT10229 #define EP0_IN_DATA BIT10282 #define EPn_OPIDCLR BIT10314 #define EPn_IPID BIT10 /* R */345 #define EPn_DEND_SET BIT10
228 #define IMR_RXCMDOK BIT10251 #define TPPoll_StopBE BIT10381 #define RRSR_48M BIT10
58 #define BIT10 0x00000400 macro
28 #define BIT10 0x00000400 macro
65 #define BIT10 0x00000400 macro
416 #define IRQ_RXDATA BIT102129 if (count == info->rbuf_fill_level || (reg & BIT10)) { in isr_rxdata()4303 case HDLC_ENCODING_NRZB: val |= BIT10; break; in sync_mode()4305 case HDLC_ENCODING_NRZI: val |= BIT11 + BIT10; break; in sync_mode()4307 case HDLC_ENCODING_BIPHASE_SPACE: val |= BIT12 + BIT10; break; in sync_mode()4309 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: val |= BIT12 + BIT11 + BIT10; break; in sync_mode()4376 case HDLC_ENCODING_NRZB: val |= BIT10; break; in sync_mode()4378 case HDLC_ENCODING_NRZI: val |= BIT11 + BIT10; break; in sync_mode()4380 case HDLC_ENCODING_BIPHASE_SPACE: val |= BIT12 + BIT10; break; in sync_mode()4382 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: val |= BIT12 + BIT11 + BIT10; break; in sync_mode()
563 #define MISCSTATUS_RI BIT10585 #define SICR_RI_INACTIVE BIT10586 #define SICR_RI (BIT11|BIT10)1707 else if ( (DmaVector&(BIT10|BIT9)) == BIT10) in mgsl_interrupt()4763 RegValue |= ( BIT12 | BIT10 | BIT9 ); in usc_set_sdlc_mode()4838 RegValue |= ( BIT12 | BIT10 | BIT9 | BIT8); in usc_set_sdlc_mode()4962 RegValue |= BIT10; in usc_set_sdlc_mode()5163 case HDLC_PREAMBLE_LENGTH_16BITS: RegValue |= BIT10; break; in usc_set_sdlc_mode()5165 case HDLC_PREAMBLE_LENGTH_64BITS: RegValue |= BIT11 | BIT10; break; in usc_set_sdlc_mode()
394 #define RRSR_48M BIT10
684 #define LPFC_SLI4_INTR10 BIT10
295 #define IRQ_CTS BIT10 // CTS status change