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Searched refs:BIT_1 (Results 1 – 25 of 33) sorted by relevance

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/drivers/scsi/qla2xxx/
Dqla_fw.h26 #define PDO_FORCE_ADISC BIT_1
38 #define PDF_HARD_ADDR BIT_1
408 #define BD_READ_DATA BIT_1
447 #define CF_READ_DATA BIT_1
489 #define TMF_READ_DATA BIT_1
855 #define TCF_TARGET_RESET BIT_1
972 #define CSRX_FLASH_ENABLE BIT_1 /* Flash BIOS Read/Write enable. */
1042 #define GPDX_DATA_INOUT (BIT_1|BIT_0)
1050 #define GPEX_ENABLE (BIT_1|BIT_0)
1173 #define MDBS_ID_ACQUIRED BIT_1
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Dqla_def.h62 #define BIT_1 0x2 macro
146 #define IDC_PEG_HALT_STATUS_CHANGE BIT_1
166 #define QLA83XX_IDC_GRACEFUL_RESET BIT_1
320 #define SRB_LOGIN_COND_PLOGI BIT_1
338 #define SRB_FXDISC_RESP_DMA_VALID BIT_1
440 #define CSR_FLASH_ENABLE BIT_1 /* Flash BIOS Read/Write enable */
458 #define NVR_SELECT BIT_1
715 #define MBX_DMA_OUT BIT_1
728 #define MBX_DMA_OUT BIT_1
840 #define FO1_AE_ALL_LIP_RESET BIT_1
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Dqla_init.c1992 swing = ha->fw_seriallink_options[2] & (BIT_2 | BIT_1 | BIT_0); in qla2x00_update_fw_options()
1996 (BIT_3 | BIT_2 | BIT_1 | BIT_0); in qla2x00_update_fw_options()
2006 ((rx_sens & (BIT_1 | BIT_0)) << 2) | in qla2x00_update_fw_options()
2007 (tx_sens & (BIT_1 | BIT_0)); in qla2x00_update_fw_options()
2012 emphasis = ha->fw_seriallink_options[3] & (BIT_1 | BIT_0); in qla2x00_update_fw_options()
2014 (BIT_3 | BIT_2 | BIT_1 | BIT_0); in qla2x00_update_fw_options()
2024 ((rx_sens & (BIT_1 | BIT_0)) << 2) | in qla2x00_update_fw_options()
2025 (tx_sens & (BIT_1 | BIT_0)); in qla2x00_update_fw_options()
2249 mid_init_cb->options = cpu_to_le16(BIT_1); in qla2x00_init_rings()
2660 nv->firmware_options[0] = BIT_2 | BIT_1; in qla2x00_nvram_config()
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Dqla_target.h159 #define NOTIFY24XX_FLAGS_GLOBAL_TPRLO BIT_1
303 #define ATIO_EXEC_READ BIT_1
524 #define CTIO7_FLAGS_DATA_IN BIT_1 /* data to initiator */
Dqla_tmpl.h59 #define CAPTURE_FLAG_PHYS_VIRT BIT_1
Dqla_mbx.c1343 mc.mb[1] = BIT_1 | BIT_3; in qla2x00_get_node_name_list()
1771 mcp->mb[1] = BIT_1; in qla2x00_lip_reset()
1905 if (opt & BIT_1) in qla24xx_login_fabric()
1965 mb[1] |= BIT_1; in qla24xx_login_fabric()
1974 mb[10] |= BIT_1; /* Class 3. */ in qla24xx_login_fabric()
3318 mcp->mb[3] = port_speed & (BIT_5|BIT_4|BIT_3|BIT_2|BIT_1|BIT_0); in qla2x00_set_idma_speed()
3630 rval = BIT_1; in qla2x00_send_change_request()
3633 rval = BIT_1; in qla2x00_send_change_request()
4806 mcp->mb[2] = BIT_1; in qla24xx_set_fcp_prio()
Dqla_isr.c1304 else if (le16_to_cpu(mbx->mb1) & BIT_1) in qla2x00_mbx_iocb_entry()
2096 if (unlikely((state_flags & BIT_1) && (sp->type == SRB_BIDI_CMD))) { in qla2x00_status_entry()
Dqla_target.c3558 cmd->cmd_flags |= BIT_1; in __qlt_do_work()
6104 ct_req->req.rff_id.fc4_feature = BIT_0 | BIT_1; in qlt_rff_id()
6108 ct_req->req.rff_id.fc4_feature = BIT_1; in qlt_rff_id()
/drivers/scsi/
Dqla1280.h27 #define BIT_1 0x2 macro
130 #define ISP_CFG0_1020A BIT_1 /* ISP1020A */
144 #define ISP_EN_INT BIT_1 /* ISP enable interrupts. */
151 #define PCI_INT BIT_1 /* PCI interrupt */
156 #define NV_SELECT BIT_1
168 #define CDMA_CONF_BENAB BIT_1 /* Bus burst enable */
185 #define DDMA_CONF_BENAB BIT_1 /* Bus burst enable */
575 #define RF_FULL BIT_1 /* Full */
973 #define OF_ENABLE_TAG BIT_1 /* Tagged queue action enable */
Dqla1280.c1152 mr = BIT_3 | BIT_2 | BIT_1 | BIT_0; in qla1280_set_target_parameters()
1728 err = qla1280_mailbox_command(ha, BIT_0 | BIT_1 | BIT_2, mb); in qla1280_load_firmware_pio()
1800 BIT_1 | BIT_0, mb); in qla1280_load_firmware_dma()
1817 BIT_1 | BIT_0, mb); in qla1280_load_firmware_dma()
1862 err = qla1280_mailbox_command(ha, BIT_1 | BIT_0, mb); in qla1280_start_firmware()
1872 err = qla1280_mailbox_command(ha, BIT_1 | BIT_0, &mb[0]); in qla1280_start_firmware()
1939 BIT_3 | BIT_2 | BIT_1 | BIT_0, in qla1280_init_rings()
1953 BIT_3 | BIT_2 | BIT_1 | BIT_0, in qla1280_init_rings()
2173 status = qla1280_mailbox_command(ha, BIT_1 | BIT_0, &mb[0]); in qla1280_config_bus()
2247 BIT_7 | BIT_3 | BIT_2 | BIT_1 | BIT_0); in qla1280_nvram_config()
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/drivers/net/ethernet/qlogic/qlcnic/
Dqlcnic_hw.h141 #define QLCNIC_GET_OWNER(val) ((val) & (BIT_0 | BIT_1))
Dqlcnic_hdr.h197 #define BIT_1 0x2 macro
494 #define TA_CTL_ENABLE BIT_1
Dqlcnic_ctx.c1345 arg2 |= (BIT_0 | BIT_1); in qlcnic_config_switch_port()
1357 arg2 &= ~(BIT_1 | BIT_2 | BIT_3); in qlcnic_config_switch_port()
1358 if (!(esw_cfg->offload_flags & BIT_1)) in qlcnic_config_switch_port()
Dqlcnic_83xx_hw.h532 #define QLC_REGISTER_DCB_AEN BIT_1
Dqlcnic.h916 #define QLCNIC_FW_CAPABILITY_TSO BIT_1
932 #define QLCNIC_83XX_FW_CAPAB_ENCAP_TX_OFFLOAD BIT_1
1323 #define QLCNIC_SWITCH_ENABLE BIT_1
Dqlcnic_hw.c827 #define QLCNIC_ENABLE_IPV6_LRO (BIT_1 | BIT_9)
1051 if (!(offload_flags & BIT_1)) in qlcnic_process_flags()
Dqlcnic_minidump.c25 #define QLCNIC_DUMP_RWCRB BIT_1
754 if (dma_sts & BIT_1) in qlcnic_start_pex_dma()
Dqlcnic_sriov_pf.c391 cmd.req.arg[1] = ((func & 0xf) << 2) | BIT_6 | BIT_1; in qlcnic_sriov_pf_cfg_eswitch()
704 cmd.req.arg[2] |= BIT_1 | BIT_3 | BIT_8; in qlcnic_sriov_set_vf_acl()
Dqlcnic_83xx_hw.c2022 lro_bit_mask = (mode ? (BIT_0 | BIT_1 | BIT_2 | BIT_3) : 0); in qlcnic_83xx_config_hw_lro()
3499 cmd.req.arg[1] = BIT_1 | (adapter->tx_ring->ctx_id << 16); in qlcnic_83xx_get_stats()
3530 #define QLCNIC_83XX_ADD_PORT1 BIT_1
Dqlcnic_83xx_init.c1024 #define QLC_83XX_ENCAP_TYPE_VXLAN BIT_1
Dqlcnic_sriov_common.c375 if (status & BIT_1) in qlcnic_sriov_get_vf_vport_info()
Dqlcnic_io.c365 #define QLCNIC_ENCAP_OUTER_L3_IP6 BIT_1
/drivers/scsi/qla4xxx/
Dql4_def.h83 #define BIT_1 0x2 macro
Dql4_os.c3515 sess->erl |= BIT_1; in qla4xxx_copy_from_fwddb_param()
3528 conn->tcp_timer_scale |= BIT_1; in qla4xxx_copy_from_fwddb_param()
3646 SET_BITVAL(sess->erl & BIT_1, options, BIT_1); in qla4xxx_copy_to_fwddb_param()
3655 SET_BITVAL(conn->tcp_timer_scale & BIT_1, options, BIT_2); in qla4xxx_copy_to_fwddb_param()
3656 SET_BITVAL(conn->tcp_timer_scale & BIT_0, options, BIT_1); in qla4xxx_copy_to_fwddb_param()
3752 sess->erl |= BIT_1; in qla4xxx_copy_to_sess_conn_params()
3765 conn->tcp_timer_scale |= BIT_1; in qla4xxx_copy_to_sess_conn_params()
8900 if (PCI_FUNC(ha->pdev->devfn) & BIT_1) in qla4xxx_prevent_other_port_reinit()
Dql4_fw.h62 #define HSRX_RISC_IOCB_INT BIT_1 /* RISC to Host IOCB interrupt */

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