1 #ifndef __MARVELL_CESA_H__
2 #define __MARVELL_CESA_H__
3
4 #include <crypto/algapi.h>
5 #include <crypto/hash.h>
6 #include <crypto/internal/hash.h>
7
8 #include <linux/crypto.h>
9 #include <linux/dmapool.h>
10
11 #define CESA_ENGINE_OFF(i) (((i) * 0x2000))
12
13 #define CESA_TDMA_BYTE_CNT 0x800
14 #define CESA_TDMA_SRC_ADDR 0x810
15 #define CESA_TDMA_DST_ADDR 0x820
16 #define CESA_TDMA_NEXT_ADDR 0x830
17
18 #define CESA_TDMA_CONTROL 0x840
19 #define CESA_TDMA_DST_BURST GENMASK(2, 0)
20 #define CESA_TDMA_DST_BURST_32B 3
21 #define CESA_TDMA_DST_BURST_128B 4
22 #define CESA_TDMA_OUT_RD_EN BIT(4)
23 #define CESA_TDMA_SRC_BURST GENMASK(8, 6)
24 #define CESA_TDMA_SRC_BURST_32B (3 << 6)
25 #define CESA_TDMA_SRC_BURST_128B (4 << 6)
26 #define CESA_TDMA_CHAIN BIT(9)
27 #define CESA_TDMA_BYTE_SWAP BIT(11)
28 #define CESA_TDMA_NO_BYTE_SWAP BIT(11)
29 #define CESA_TDMA_EN BIT(12)
30 #define CESA_TDMA_FETCH_ND BIT(13)
31 #define CESA_TDMA_ACT BIT(14)
32
33 #define CESA_TDMA_CUR 0x870
34 #define CESA_TDMA_ERROR_CAUSE 0x8c8
35 #define CESA_TDMA_ERROR_MSK 0x8cc
36
37 #define CESA_TDMA_WINDOW_BASE(x) (((x) * 0x8) + 0xa00)
38 #define CESA_TDMA_WINDOW_CTRL(x) (((x) * 0x8) + 0xa04)
39
40 #define CESA_IVDIG(x) (0xdd00 + ((x) * 4) + \
41 (((x) < 5) ? 0 : 0x14))
42
43 #define CESA_SA_CMD 0xde00
44 #define CESA_SA_CMD_EN_CESA_SA_ACCL0 BIT(0)
45 #define CESA_SA_CMD_EN_CESA_SA_ACCL1 BIT(1)
46 #define CESA_SA_CMD_DISABLE_SEC BIT(2)
47
48 #define CESA_SA_DESC_P0 0xde04
49
50 #define CESA_SA_DESC_P1 0xde14
51
52 #define CESA_SA_CFG 0xde08
53 #define CESA_SA_CFG_STOP_DIG_ERR GENMASK(1, 0)
54 #define CESA_SA_CFG_DIG_ERR_CONT 0
55 #define CESA_SA_CFG_DIG_ERR_SKIP 1
56 #define CESA_SA_CFG_DIG_ERR_STOP 3
57 #define CESA_SA_CFG_CH0_W_IDMA BIT(7)
58 #define CESA_SA_CFG_CH1_W_IDMA BIT(8)
59 #define CESA_SA_CFG_ACT_CH0_IDMA BIT(9)
60 #define CESA_SA_CFG_ACT_CH1_IDMA BIT(10)
61 #define CESA_SA_CFG_MULTI_PKT BIT(11)
62 #define CESA_SA_CFG_PARA_DIS BIT(13)
63
64 #define CESA_SA_ACCEL_STATUS 0xde0c
65 #define CESA_SA_ST_ACT_0 BIT(0)
66 #define CESA_SA_ST_ACT_1 BIT(1)
67
68 /*
69 * CESA_SA_FPGA_INT_STATUS looks like a FPGA leftover and is documented only
70 * in Errata 4.12. It looks like that it was part of an IRQ-controller in FPGA
71 * and someone forgot to remove it while switching to the core and moving to
72 * CESA_SA_INT_STATUS.
73 */
74 #define CESA_SA_FPGA_INT_STATUS 0xdd68
75 #define CESA_SA_INT_STATUS 0xde20
76 #define CESA_SA_INT_AUTH_DONE BIT(0)
77 #define CESA_SA_INT_DES_E_DONE BIT(1)
78 #define CESA_SA_INT_AES_E_DONE BIT(2)
79 #define CESA_SA_INT_AES_D_DONE BIT(3)
80 #define CESA_SA_INT_ENC_DONE BIT(4)
81 #define CESA_SA_INT_ACCEL0_DONE BIT(5)
82 #define CESA_SA_INT_ACCEL1_DONE BIT(6)
83 #define CESA_SA_INT_ACC0_IDMA_DONE BIT(7)
84 #define CESA_SA_INT_ACC1_IDMA_DONE BIT(8)
85 #define CESA_SA_INT_IDMA_DONE BIT(9)
86 #define CESA_SA_INT_IDMA_OWN_ERR BIT(10)
87
88 #define CESA_SA_INT_MSK 0xde24
89
90 #define CESA_SA_DESC_CFG_OP_MAC_ONLY 0
91 #define CESA_SA_DESC_CFG_OP_CRYPT_ONLY 1
92 #define CESA_SA_DESC_CFG_OP_MAC_CRYPT 2
93 #define CESA_SA_DESC_CFG_OP_CRYPT_MAC 3
94 #define CESA_SA_DESC_CFG_OP_MSK GENMASK(1, 0)
95 #define CESA_SA_DESC_CFG_MACM_SHA256 (1 << 4)
96 #define CESA_SA_DESC_CFG_MACM_HMAC_SHA256 (3 << 4)
97 #define CESA_SA_DESC_CFG_MACM_MD5 (4 << 4)
98 #define CESA_SA_DESC_CFG_MACM_SHA1 (5 << 4)
99 #define CESA_SA_DESC_CFG_MACM_HMAC_MD5 (6 << 4)
100 #define CESA_SA_DESC_CFG_MACM_HMAC_SHA1 (7 << 4)
101 #define CESA_SA_DESC_CFG_MACM_MSK GENMASK(6, 4)
102 #define CESA_SA_DESC_CFG_CRYPTM_DES (1 << 8)
103 #define CESA_SA_DESC_CFG_CRYPTM_3DES (2 << 8)
104 #define CESA_SA_DESC_CFG_CRYPTM_AES (3 << 8)
105 #define CESA_SA_DESC_CFG_CRYPTM_MSK GENMASK(9, 8)
106 #define CESA_SA_DESC_CFG_DIR_ENC (0 << 12)
107 #define CESA_SA_DESC_CFG_DIR_DEC (1 << 12)
108 #define CESA_SA_DESC_CFG_CRYPTCM_ECB (0 << 16)
109 #define CESA_SA_DESC_CFG_CRYPTCM_CBC (1 << 16)
110 #define CESA_SA_DESC_CFG_CRYPTCM_MSK BIT(16)
111 #define CESA_SA_DESC_CFG_3DES_EEE (0 << 20)
112 #define CESA_SA_DESC_CFG_3DES_EDE (1 << 20)
113 #define CESA_SA_DESC_CFG_AES_LEN_128 (0 << 24)
114 #define CESA_SA_DESC_CFG_AES_LEN_192 (1 << 24)
115 #define CESA_SA_DESC_CFG_AES_LEN_256 (2 << 24)
116 #define CESA_SA_DESC_CFG_AES_LEN_MSK GENMASK(25, 24)
117 #define CESA_SA_DESC_CFG_NOT_FRAG (0 << 30)
118 #define CESA_SA_DESC_CFG_FIRST_FRAG (1 << 30)
119 #define CESA_SA_DESC_CFG_LAST_FRAG (2 << 30)
120 #define CESA_SA_DESC_CFG_MID_FRAG (3 << 30)
121 #define CESA_SA_DESC_CFG_FRAG_MSK GENMASK(31, 30)
122
123 /*
124 * /-----------\ 0
125 * | ACCEL CFG | 4 * 8
126 * |-----------| 0x20
127 * | CRYPT KEY | 8 * 4
128 * |-----------| 0x40
129 * | IV IN | 4 * 4
130 * |-----------| 0x40 (inplace)
131 * | IV BUF | 4 * 4
132 * |-----------| 0x80
133 * | DATA IN | 16 * x (max ->max_req_size)
134 * |-----------| 0x80 (inplace operation)
135 * | DATA OUT | 16 * x (max ->max_req_size)
136 * \-----------/ SRAM size
137 */
138
139 /*
140 * Hashing memory map:
141 * /-----------\ 0
142 * | ACCEL CFG | 4 * 8
143 * |-----------| 0x20
144 * | Inner IV | 8 * 4
145 * |-----------| 0x40
146 * | Outer IV | 8 * 4
147 * |-----------| 0x60
148 * | Output BUF| 8 * 4
149 * |-----------| 0x80
150 * | DATA IN | 64 * x (max ->max_req_size)
151 * \-----------/ SRAM size
152 */
153
154 #define CESA_SA_CFG_SRAM_OFFSET 0x00
155 #define CESA_SA_DATA_SRAM_OFFSET 0x80
156
157 #define CESA_SA_CRYPT_KEY_SRAM_OFFSET 0x20
158 #define CESA_SA_CRYPT_IV_SRAM_OFFSET 0x40
159
160 #define CESA_SA_MAC_IIV_SRAM_OFFSET 0x20
161 #define CESA_SA_MAC_OIV_SRAM_OFFSET 0x40
162 #define CESA_SA_MAC_DIG_SRAM_OFFSET 0x60
163
164 #define CESA_SA_DESC_CRYPT_DATA(offset) \
165 cpu_to_le32((CESA_SA_DATA_SRAM_OFFSET + (offset)) | \
166 ((CESA_SA_DATA_SRAM_OFFSET + (offset)) << 16))
167
168 #define CESA_SA_DESC_CRYPT_IV(offset) \
169 cpu_to_le32((CESA_SA_CRYPT_IV_SRAM_OFFSET + (offset)) | \
170 ((CESA_SA_CRYPT_IV_SRAM_OFFSET + (offset)) << 16))
171
172 #define CESA_SA_DESC_CRYPT_KEY(offset) \
173 cpu_to_le32(CESA_SA_CRYPT_KEY_SRAM_OFFSET + (offset))
174
175 #define CESA_SA_DESC_MAC_DATA(offset) \
176 cpu_to_le32(CESA_SA_DATA_SRAM_OFFSET + (offset))
177 #define CESA_SA_DESC_MAC_DATA_MSK cpu_to_le32(GENMASK(15, 0))
178
179 #define CESA_SA_DESC_MAC_TOTAL_LEN(total_len) cpu_to_le32((total_len) << 16)
180 #define CESA_SA_DESC_MAC_TOTAL_LEN_MSK cpu_to_le32(GENMASK(31, 16))
181
182 #define CESA_SA_DESC_MAC_SRC_TOTAL_LEN_MAX 0xffff
183
184 #define CESA_SA_DESC_MAC_DIGEST(offset) \
185 cpu_to_le32(CESA_SA_MAC_DIG_SRAM_OFFSET + (offset))
186 #define CESA_SA_DESC_MAC_DIGEST_MSK cpu_to_le32(GENMASK(15, 0))
187
188 #define CESA_SA_DESC_MAC_FRAG_LEN(frag_len) cpu_to_le32((frag_len) << 16)
189 #define CESA_SA_DESC_MAC_FRAG_LEN_MSK cpu_to_le32(GENMASK(31, 16))
190
191 #define CESA_SA_DESC_MAC_IV(offset) \
192 cpu_to_le32((CESA_SA_MAC_IIV_SRAM_OFFSET + (offset)) | \
193 ((CESA_SA_MAC_OIV_SRAM_OFFSET + (offset)) << 16))
194
195 #define CESA_SA_SRAM_SIZE 2048
196 #define CESA_SA_SRAM_PAYLOAD_SIZE (cesa_dev->sram_size - \
197 CESA_SA_DATA_SRAM_OFFSET)
198
199 #define CESA_SA_DEFAULT_SRAM_SIZE 2048
200 #define CESA_SA_MIN_SRAM_SIZE 1024
201
202 #define CESA_SA_SRAM_MSK (2048 - 1)
203
204 #define CESA_MAX_HASH_BLOCK_SIZE 64
205 #define CESA_HASH_BLOCK_SIZE_MSK (CESA_MAX_HASH_BLOCK_SIZE - 1)
206
207 /**
208 * struct mv_cesa_sec_accel_desc - security accelerator descriptor
209 * @config: engine config
210 * @enc_p: input and output data pointers for a cipher operation
211 * @enc_len: cipher operation length
212 * @enc_key_p: cipher key pointer
213 * @enc_iv: cipher IV pointers
214 * @mac_src_p: input pointer and total hash length
215 * @mac_digest: digest pointer and hash operation length
216 * @mac_iv: hmac IV pointers
217 *
218 * Structure passed to the CESA engine to describe the crypto operation
219 * to be executed.
220 */
221 struct mv_cesa_sec_accel_desc {
222 __le32 config;
223 __le32 enc_p;
224 __le32 enc_len;
225 __le32 enc_key_p;
226 __le32 enc_iv;
227 __le32 mac_src_p;
228 __le32 mac_digest;
229 __le32 mac_iv;
230 };
231
232 /**
233 * struct mv_cesa_blkcipher_op_ctx - cipher operation context
234 * @key: cipher key
235 * @iv: cipher IV
236 *
237 * Context associated to a cipher operation.
238 */
239 struct mv_cesa_blkcipher_op_ctx {
240 u32 key[8];
241 u32 iv[4];
242 };
243
244 /**
245 * struct mv_cesa_hash_op_ctx - hash or hmac operation context
246 * @key: cipher key
247 * @iv: cipher IV
248 *
249 * Context associated to an hash or hmac operation.
250 */
251 struct mv_cesa_hash_op_ctx {
252 u32 iv[16];
253 u32 hash[8];
254 };
255
256 /**
257 * struct mv_cesa_op_ctx - crypto operation context
258 * @desc: CESA descriptor
259 * @ctx: context associated to the crypto operation
260 *
261 * Context associated to a crypto operation.
262 */
263 struct mv_cesa_op_ctx {
264 struct mv_cesa_sec_accel_desc desc;
265 union {
266 struct mv_cesa_blkcipher_op_ctx blkcipher;
267 struct mv_cesa_hash_op_ctx hash;
268 } ctx;
269 };
270
271 /* TDMA descriptor flags */
272 #define CESA_TDMA_DST_IN_SRAM BIT(31)
273 #define CESA_TDMA_SRC_IN_SRAM BIT(30)
274 #define CESA_TDMA_TYPE_MSK GENMASK(29, 0)
275 #define CESA_TDMA_DUMMY 0
276 #define CESA_TDMA_DATA 1
277 #define CESA_TDMA_OP 2
278
279 /**
280 * struct mv_cesa_tdma_desc - TDMA descriptor
281 * @byte_cnt: number of bytes to transfer
282 * @src: DMA address of the source
283 * @dst: DMA address of the destination
284 * @next_dma: DMA address of the next TDMA descriptor
285 * @cur_dma: DMA address of this TDMA descriptor
286 * @next: pointer to the next TDMA descriptor
287 * @op: CESA operation attached to this TDMA descriptor
288 * @data: raw data attached to this TDMA descriptor
289 * @flags: flags describing the TDMA transfer. See the
290 * "TDMA descriptor flags" section above
291 *
292 * TDMA descriptor used to create a transfer chain describing a crypto
293 * operation.
294 */
295 struct mv_cesa_tdma_desc {
296 __le32 byte_cnt;
297 __le32 src;
298 __le32 dst;
299 __le32 next_dma;
300
301 /* Software state */
302 dma_addr_t cur_dma;
303 struct mv_cesa_tdma_desc *next;
304 union {
305 struct mv_cesa_op_ctx *op;
306 void *data;
307 };
308 u32 flags;
309 };
310
311 /**
312 * struct mv_cesa_sg_dma_iter - scatter-gather iterator
313 * @dir: transfer direction
314 * @sg: scatter list
315 * @offset: current position in the scatter list
316 * @op_offset: current position in the crypto operation
317 *
318 * Iterator used to iterate over a scatterlist while creating a TDMA chain for
319 * a crypto operation.
320 */
321 struct mv_cesa_sg_dma_iter {
322 enum dma_data_direction dir;
323 struct scatterlist *sg;
324 unsigned int offset;
325 unsigned int op_offset;
326 };
327
328 /**
329 * struct mv_cesa_dma_iter - crypto operation iterator
330 * @len: the crypto operation length
331 * @offset: current position in the crypto operation
332 * @op_len: sub-operation length (the crypto engine can only act on 2kb
333 * chunks)
334 *
335 * Iterator used to create a TDMA chain for a given crypto operation.
336 */
337 struct mv_cesa_dma_iter {
338 unsigned int len;
339 unsigned int offset;
340 unsigned int op_len;
341 };
342
343 /**
344 * struct mv_cesa_tdma_chain - TDMA chain
345 * @first: first entry in the TDMA chain
346 * @last: last entry in the TDMA chain
347 *
348 * Stores a TDMA chain for a specific crypto operation.
349 */
350 struct mv_cesa_tdma_chain {
351 struct mv_cesa_tdma_desc *first;
352 struct mv_cesa_tdma_desc *last;
353 };
354
355 struct mv_cesa_engine;
356
357 /**
358 * struct mv_cesa_caps - CESA device capabilities
359 * @engines: number of engines
360 * @has_tdma: whether this device has a TDMA block
361 * @cipher_algs: supported cipher algorithms
362 * @ncipher_algs: number of supported cipher algorithms
363 * @ahash_algs: supported hash algorithms
364 * @nahash_algs: number of supported hash algorithms
365 *
366 * Structure used to describe CESA device capabilities.
367 */
368 struct mv_cesa_caps {
369 int nengines;
370 bool has_tdma;
371 struct crypto_alg **cipher_algs;
372 int ncipher_algs;
373 struct ahash_alg **ahash_algs;
374 int nahash_algs;
375 };
376
377 /**
378 * struct mv_cesa_dev_dma - DMA pools
379 * @tdma_desc_pool: TDMA desc pool
380 * @op_pool: crypto operation pool
381 * @cache_pool: data cache pool (used by hash implementation when the
382 * hash request is smaller than the hash block size)
383 * @padding_pool: padding pool (used by hash implementation when hardware
384 * padding cannot be used)
385 *
386 * Structure containing the different DMA pools used by this driver.
387 */
388 struct mv_cesa_dev_dma {
389 struct dma_pool *tdma_desc_pool;
390 struct dma_pool *op_pool;
391 struct dma_pool *cache_pool;
392 struct dma_pool *padding_pool;
393 };
394
395 /**
396 * struct mv_cesa_dev - CESA device
397 * @caps: device capabilities
398 * @regs: device registers
399 * @sram_size: usable SRAM size
400 * @lock: device lock
401 * @queue: crypto request queue
402 * @engines: array of engines
403 * @dma: dma pools
404 *
405 * Structure storing CESA device information.
406 */
407 struct mv_cesa_dev {
408 const struct mv_cesa_caps *caps;
409 void __iomem *regs;
410 struct device *dev;
411 unsigned int sram_size;
412 spinlock_t lock;
413 struct crypto_queue queue;
414 struct mv_cesa_engine *engines;
415 struct mv_cesa_dev_dma *dma;
416 };
417
418 /**
419 * struct mv_cesa_engine - CESA engine
420 * @id: engine id
421 * @regs: engine registers
422 * @sram: SRAM memory region
423 * @sram_dma: DMA address of the SRAM memory region
424 * @lock: engine lock
425 * @req: current crypto request
426 * @clk: engine clk
427 * @zclk: engine zclk
428 * @max_req_len: maximum chunk length (useful to create the TDMA chain)
429 * @int_mask: interrupt mask cache
430 * @pool: memory pool pointing to the memory region reserved in
431 * SRAM
432 *
433 * Structure storing CESA engine information.
434 */
435 struct mv_cesa_engine {
436 int id;
437 void __iomem *regs;
438 void __iomem *sram;
439 dma_addr_t sram_dma;
440 spinlock_t lock;
441 struct crypto_async_request *req;
442 struct clk *clk;
443 struct clk *zclk;
444 size_t max_req_len;
445 u32 int_mask;
446 struct gen_pool *pool;
447 };
448
449 /**
450 * struct mv_cesa_req_ops - CESA request operations
451 * @prepare: prepare a request to be executed on the specified engine
452 * @process: process a request chunk result (should return 0 if the
453 * operation, -EINPROGRESS if it needs more steps or an error
454 * code)
455 * @step: launch the crypto operation on the next chunk
456 * @cleanup: cleanup the crypto request (release associated data)
457 */
458 struct mv_cesa_req_ops {
459 void (*prepare)(struct crypto_async_request *req,
460 struct mv_cesa_engine *engine);
461 int (*process)(struct crypto_async_request *req, u32 status);
462 void (*step)(struct crypto_async_request *req);
463 void (*cleanup)(struct crypto_async_request *req);
464 };
465
466 /**
467 * struct mv_cesa_ctx - CESA operation context
468 * @ops: crypto operations
469 *
470 * Base context structure inherited by operation specific ones.
471 */
472 struct mv_cesa_ctx {
473 const struct mv_cesa_req_ops *ops;
474 };
475
476 /**
477 * struct mv_cesa_hash_ctx - CESA hash operation context
478 * @base: base context structure
479 *
480 * Hash context structure.
481 */
482 struct mv_cesa_hash_ctx {
483 struct mv_cesa_ctx base;
484 };
485
486 /**
487 * struct mv_cesa_hash_ctx - CESA hmac operation context
488 * @base: base context structure
489 * @iv: initialization vectors
490 *
491 * HMAC context structure.
492 */
493 struct mv_cesa_hmac_ctx {
494 struct mv_cesa_ctx base;
495 u32 iv[16];
496 };
497
498 /**
499 * enum mv_cesa_req_type - request type definitions
500 * @CESA_STD_REQ: standard request
501 * @CESA_DMA_REQ: DMA request
502 */
503 enum mv_cesa_req_type {
504 CESA_STD_REQ,
505 CESA_DMA_REQ,
506 };
507
508 /**
509 * struct mv_cesa_req - CESA request
510 * @type: request type
511 * @engine: engine associated with this request
512 */
513 struct mv_cesa_req {
514 enum mv_cesa_req_type type;
515 struct mv_cesa_engine *engine;
516 };
517
518 /**
519 * struct mv_cesa_tdma_req - CESA TDMA request
520 * @base: base information
521 * @chain: TDMA chain
522 */
523 struct mv_cesa_tdma_req {
524 struct mv_cesa_req base;
525 struct mv_cesa_tdma_chain chain;
526 };
527
528 /**
529 * struct mv_cesa_sg_std_iter - CESA scatter-gather iterator for standard
530 * requests
531 * @iter: sg mapping iterator
532 * @offset: current offset in the SG entry mapped in memory
533 */
534 struct mv_cesa_sg_std_iter {
535 struct sg_mapping_iter iter;
536 unsigned int offset;
537 };
538
539 /**
540 * struct mv_cesa_ablkcipher_std_req - cipher standard request
541 * @base: base information
542 * @op: operation context
543 * @offset: current operation offset
544 * @size: size of the crypto operation
545 */
546 struct mv_cesa_ablkcipher_std_req {
547 struct mv_cesa_req base;
548 struct mv_cesa_op_ctx op;
549 unsigned int offset;
550 unsigned int size;
551 bool skip_ctx;
552 };
553
554 /**
555 * struct mv_cesa_ablkcipher_req - cipher request
556 * @req: type specific request information
557 * @src_nents: number of entries in the src sg list
558 * @dst_nents: number of entries in the dest sg list
559 */
560 struct mv_cesa_ablkcipher_req {
561 union {
562 struct mv_cesa_req base;
563 struct mv_cesa_tdma_req dma;
564 struct mv_cesa_ablkcipher_std_req std;
565 } req;
566 int src_nents;
567 int dst_nents;
568 };
569
570 /**
571 * struct mv_cesa_ahash_std_req - standard hash request
572 * @base: base information
573 * @offset: current operation offset
574 */
575 struct mv_cesa_ahash_std_req {
576 struct mv_cesa_req base;
577 unsigned int offset;
578 };
579
580 /**
581 * struct mv_cesa_ahash_dma_req - DMA hash request
582 * @base: base information
583 * @padding: padding buffer
584 * @padding_dma: DMA address of the padding buffer
585 * @cache_dma: DMA address of the cache buffer
586 */
587 struct mv_cesa_ahash_dma_req {
588 struct mv_cesa_tdma_req base;
589 u8 *padding;
590 dma_addr_t padding_dma;
591 dma_addr_t cache_dma;
592 };
593
594 /**
595 * struct mv_cesa_ahash_req - hash request
596 * @req: type specific request information
597 * @cache: cache buffer
598 * @cache_ptr: write pointer in the cache buffer
599 * @len: hash total length
600 * @src_nents: number of entries in the scatterlist
601 * @last_req: define whether the current operation is the last one
602 * or not
603 * @state: hash state
604 */
605 struct mv_cesa_ahash_req {
606 union {
607 struct mv_cesa_req base;
608 struct mv_cesa_ahash_dma_req dma;
609 struct mv_cesa_ahash_std_req std;
610 } req;
611 struct mv_cesa_op_ctx op_tmpl;
612 u8 *cache;
613 unsigned int cache_ptr;
614 u64 len;
615 int src_nents;
616 bool last_req;
617 bool algo_le;
618 u32 state[8];
619 };
620
621 /* CESA functions */
622
623 extern struct mv_cesa_dev *cesa_dev;
624
mv_cesa_update_op_cfg(struct mv_cesa_op_ctx * op,u32 cfg,u32 mask)625 static inline void mv_cesa_update_op_cfg(struct mv_cesa_op_ctx *op,
626 u32 cfg, u32 mask)
627 {
628 op->desc.config &= cpu_to_le32(~mask);
629 op->desc.config |= cpu_to_le32(cfg);
630 }
631
mv_cesa_get_op_cfg(const struct mv_cesa_op_ctx * op)632 static inline u32 mv_cesa_get_op_cfg(const struct mv_cesa_op_ctx *op)
633 {
634 return le32_to_cpu(op->desc.config);
635 }
636
mv_cesa_set_op_cfg(struct mv_cesa_op_ctx * op,u32 cfg)637 static inline void mv_cesa_set_op_cfg(struct mv_cesa_op_ctx *op, u32 cfg)
638 {
639 op->desc.config = cpu_to_le32(cfg);
640 }
641
mv_cesa_adjust_op(struct mv_cesa_engine * engine,struct mv_cesa_op_ctx * op)642 static inline void mv_cesa_adjust_op(struct mv_cesa_engine *engine,
643 struct mv_cesa_op_ctx *op)
644 {
645 u32 offset = engine->sram_dma & CESA_SA_SRAM_MSK;
646
647 op->desc.enc_p = CESA_SA_DESC_CRYPT_DATA(offset);
648 op->desc.enc_key_p = CESA_SA_DESC_CRYPT_KEY(offset);
649 op->desc.enc_iv = CESA_SA_DESC_CRYPT_IV(offset);
650 op->desc.mac_src_p &= ~CESA_SA_DESC_MAC_DATA_MSK;
651 op->desc.mac_src_p |= CESA_SA_DESC_MAC_DATA(offset);
652 op->desc.mac_digest &= ~CESA_SA_DESC_MAC_DIGEST_MSK;
653 op->desc.mac_digest |= CESA_SA_DESC_MAC_DIGEST(offset);
654 op->desc.mac_iv = CESA_SA_DESC_MAC_IV(offset);
655 }
656
mv_cesa_set_crypt_op_len(struct mv_cesa_op_ctx * op,int len)657 static inline void mv_cesa_set_crypt_op_len(struct mv_cesa_op_ctx *op, int len)
658 {
659 op->desc.enc_len = cpu_to_le32(len);
660 }
661
mv_cesa_set_mac_op_total_len(struct mv_cesa_op_ctx * op,int len)662 static inline void mv_cesa_set_mac_op_total_len(struct mv_cesa_op_ctx *op,
663 int len)
664 {
665 op->desc.mac_src_p &= ~CESA_SA_DESC_MAC_TOTAL_LEN_MSK;
666 op->desc.mac_src_p |= CESA_SA_DESC_MAC_TOTAL_LEN(len);
667 }
668
mv_cesa_set_mac_op_frag_len(struct mv_cesa_op_ctx * op,int len)669 static inline void mv_cesa_set_mac_op_frag_len(struct mv_cesa_op_ctx *op,
670 int len)
671 {
672 op->desc.mac_digest &= ~CESA_SA_DESC_MAC_FRAG_LEN_MSK;
673 op->desc.mac_digest |= CESA_SA_DESC_MAC_FRAG_LEN(len);
674 }
675
mv_cesa_set_int_mask(struct mv_cesa_engine * engine,u32 int_mask)676 static inline void mv_cesa_set_int_mask(struct mv_cesa_engine *engine,
677 u32 int_mask)
678 {
679 if (int_mask == engine->int_mask)
680 return;
681
682 writel_relaxed(int_mask, engine->regs + CESA_SA_INT_MSK);
683 engine->int_mask = int_mask;
684 }
685
mv_cesa_get_int_mask(struct mv_cesa_engine * engine)686 static inline u32 mv_cesa_get_int_mask(struct mv_cesa_engine *engine)
687 {
688 return engine->int_mask;
689 }
690
mv_cesa_mac_op_is_first_frag(const struct mv_cesa_op_ctx * op)691 static inline bool mv_cesa_mac_op_is_first_frag(const struct mv_cesa_op_ctx *op)
692 {
693 return (mv_cesa_get_op_cfg(op) & CESA_SA_DESC_CFG_FRAG_MSK) ==
694 CESA_SA_DESC_CFG_FIRST_FRAG;
695 }
696
697 int mv_cesa_queue_req(struct crypto_async_request *req);
698
699 /*
700 * Helper function that indicates whether a crypto request needs to be
701 * cleaned up or not after being enqueued using mv_cesa_queue_req().
702 */
mv_cesa_req_needs_cleanup(struct crypto_async_request * req,int ret)703 static inline int mv_cesa_req_needs_cleanup(struct crypto_async_request *req,
704 int ret)
705 {
706 /*
707 * The queue still had some space, the request was queued
708 * normally, so there's no need to clean it up.
709 */
710 if (ret == -EINPROGRESS)
711 return false;
712
713 /*
714 * The queue had not space left, but since the request is
715 * flagged with CRYPTO_TFM_REQ_MAY_BACKLOG, it was added to
716 * the backlog and will be processed later. There's no need to
717 * clean it up.
718 */
719 if (ret == -EBUSY && req->flags & CRYPTO_TFM_REQ_MAY_BACKLOG)
720 return false;
721
722 /* Request wasn't queued, we need to clean it up */
723 return true;
724 }
725
726 /* TDMA functions */
727
mv_cesa_req_dma_iter_init(struct mv_cesa_dma_iter * iter,unsigned int len)728 static inline void mv_cesa_req_dma_iter_init(struct mv_cesa_dma_iter *iter,
729 unsigned int len)
730 {
731 iter->len = len;
732 iter->op_len = min(len, CESA_SA_SRAM_PAYLOAD_SIZE);
733 iter->offset = 0;
734 }
735
mv_cesa_sg_dma_iter_init(struct mv_cesa_sg_dma_iter * iter,struct scatterlist * sg,enum dma_data_direction dir)736 static inline void mv_cesa_sg_dma_iter_init(struct mv_cesa_sg_dma_iter *iter,
737 struct scatterlist *sg,
738 enum dma_data_direction dir)
739 {
740 iter->op_offset = 0;
741 iter->offset = 0;
742 iter->sg = sg;
743 iter->dir = dir;
744 }
745
746 static inline unsigned int
mv_cesa_req_dma_iter_transfer_len(struct mv_cesa_dma_iter * iter,struct mv_cesa_sg_dma_iter * sgiter)747 mv_cesa_req_dma_iter_transfer_len(struct mv_cesa_dma_iter *iter,
748 struct mv_cesa_sg_dma_iter *sgiter)
749 {
750 return min(iter->op_len - sgiter->op_offset,
751 sg_dma_len(sgiter->sg) - sgiter->offset);
752 }
753
754 bool mv_cesa_req_dma_iter_next_transfer(struct mv_cesa_dma_iter *chain,
755 struct mv_cesa_sg_dma_iter *sgiter,
756 unsigned int len);
757
mv_cesa_req_dma_iter_next_op(struct mv_cesa_dma_iter * iter)758 static inline bool mv_cesa_req_dma_iter_next_op(struct mv_cesa_dma_iter *iter)
759 {
760 iter->offset += iter->op_len;
761 iter->op_len = min(iter->len - iter->offset,
762 CESA_SA_SRAM_PAYLOAD_SIZE);
763
764 return iter->op_len;
765 }
766
767 void mv_cesa_dma_step(struct mv_cesa_tdma_req *dreq);
768
mv_cesa_dma_process(struct mv_cesa_tdma_req * dreq,u32 status)769 static inline int mv_cesa_dma_process(struct mv_cesa_tdma_req *dreq,
770 u32 status)
771 {
772 if (!(status & CESA_SA_INT_ACC0_IDMA_DONE))
773 return -EINPROGRESS;
774
775 if (status & CESA_SA_INT_IDMA_OWN_ERR)
776 return -EINVAL;
777
778 return 0;
779 }
780
781 void mv_cesa_dma_prepare(struct mv_cesa_tdma_req *dreq,
782 struct mv_cesa_engine *engine);
783
784 void mv_cesa_dma_cleanup(struct mv_cesa_tdma_req *dreq);
785
786 static inline void
mv_cesa_tdma_desc_iter_init(struct mv_cesa_tdma_chain * chain)787 mv_cesa_tdma_desc_iter_init(struct mv_cesa_tdma_chain *chain)
788 {
789 memset(chain, 0, sizeof(*chain));
790 }
791
792 struct mv_cesa_op_ctx *mv_cesa_dma_add_op(struct mv_cesa_tdma_chain *chain,
793 const struct mv_cesa_op_ctx *op_templ,
794 bool skip_ctx,
795 gfp_t flags);
796
797 int mv_cesa_dma_add_data_transfer(struct mv_cesa_tdma_chain *chain,
798 dma_addr_t dst, dma_addr_t src, u32 size,
799 u32 flags, gfp_t gfp_flags);
800
801 int mv_cesa_dma_add_dummy_launch(struct mv_cesa_tdma_chain *chain, gfp_t flags);
802 int mv_cesa_dma_add_dummy_end(struct mv_cesa_tdma_chain *chain, gfp_t flags);
803
804 int mv_cesa_dma_add_op_transfers(struct mv_cesa_tdma_chain *chain,
805 struct mv_cesa_dma_iter *dma_iter,
806 struct mv_cesa_sg_dma_iter *sgiter,
807 gfp_t gfp_flags);
808
809 /* Algorithm definitions */
810
811 extern struct ahash_alg mv_md5_alg;
812 extern struct ahash_alg mv_sha1_alg;
813 extern struct ahash_alg mv_sha256_alg;
814 extern struct ahash_alg mv_ahmac_md5_alg;
815 extern struct ahash_alg mv_ahmac_sha1_alg;
816 extern struct ahash_alg mv_ahmac_sha256_alg;
817
818 extern struct crypto_alg mv_cesa_ecb_des_alg;
819 extern struct crypto_alg mv_cesa_cbc_des_alg;
820 extern struct crypto_alg mv_cesa_ecb_des3_ede_alg;
821 extern struct crypto_alg mv_cesa_cbc_des3_ede_alg;
822 extern struct crypto_alg mv_cesa_ecb_aes_alg;
823 extern struct crypto_alg mv_cesa_cbc_aes_alg;
824
825 #endif /* __MARVELL_CESA_H__ */
826