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Searched refs:CLKS_MASK (Results 1 – 14 of 14) sorted by relevance

/drivers/gpu/drm/radeon/
Drv740d.h115 #define CLKS_MASK (0xfff << 0) macro
Drv6xxd.h160 # define CLKS_MASK (0xff << 3) macro
Drv740_dpm.c261 mpll_ss2 &= ~CLKS_MASK; in rv740_populate_mclk_value()
Drv770d.h272 #define CLKS_MASK (0xfff << 4) macro
Dnid.h692 #define CLKS_MASK (0xfff << 0) macro
Drv6xx_dpm.c319 CLKS(clk_s), ~CLKS_MASK); in rv6xx_set_engine_spread_spectrum_clk_s()
343 WREG32_P(CG_MPLL_SPREAD_SPECTRUM, CLKS(clk_s), ~CLKS_MASK); in rv6xx_set_memory_spread_spectrum_clk_s()
Dsid.h635 #define CLKS_MASK (0xfff << 0) macro
Dcikd.h760 #define CLKS_MASK (0xfff << 0) macro
Devergreend.h230 #define CLKS_MASK (0xfff << 0) macro
Dcypress_dpm.c568 mpll_ss2 &= ~CLKS_MASK; in cypress_populate_mclk_value()
Drv770_dpm.c547 cg_spll_spread_spectrum &= ~CLKS_MASK; in rv770_populate_sclk_value()
Dni_dpm.c2251 mpll_ss2 &= ~CLKS_MASK; in ni_populate_mclk_value()
Dsi_dpm.c4985 mpll_ss2 &= ~CLKS_MASK; in si_populate_mclk_value()
Dci_dpm.c2824 mpll_ss2 &= ~CLKS_MASK; in ci_calculate_mclk_params()