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Searched refs:CLK_DIV (Results 1 – 7 of 7) sorted by relevance

/drivers/clk/zte/
Dclk-zx296702.c30 #define CLK_DIV (topcrm_base + 0x08) macro
290 zx_divtbl("main_hclk", "matrix_aclk", CLK_DIV, 0, 2, in zx296702_top_clocks_init()
293 zx_divtbl("main_pclk", "matrix_aclk", CLK_DIV, 2, 2, in zx296702_top_clocks_init()
321 zx_divtbl("a9_as1_aclk_div", "a9_as1_aclk_mux", CLK_DIV, 4, 2, in zx296702_top_clocks_init()
377 zx_divtbl("sec_wclk_div", "pll_lsp_104M", CLK_DIV, 6, 3, in zx296702_top_clocks_init()
/drivers/mfd/
Drtsx_usb.c462 rtsx_usb_add_cmd(ucr, WRITE_REG_CMD, CLK_DIV, CLK_CHANGE, CLK_CHANGE); in rtsx_usb_switch_clock()
463 rtsx_usb_add_cmd(ucr, WRITE_REG_CMD, CLK_DIV, in rtsx_usb_switch_clock()
489 ret = rtsx_usb_write_register(ucr, CLK_DIV, CLK_CHANGE, 0); in rtsx_usb_switch_clock()
592 ret = rtsx_usb_write_register(ucr, CLK_DIV, CLK_CHANGE, 0x00); in rtsx_usb_init_chip()
Drtsx_pcr.c710 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_DIV, in rtsx_pci_switch_clock()
1014 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_DIV, 0x07, 0x07); in rtsx_pci_init_hw()
/drivers/staging/rts5208/
Drtsx_card.c682 rtsx_add_cmd(chip, WRITE_REG_CMD, CLK_DIV, 0xFF, (div << 4) | mcu_cnt); in switch_ssc_clock()
818 retval = rtsx_write_register(chip, CLK_DIV, 0xFF, in switch_normal_clock()
Drtsx_card.h832 #define CLK_DIV 0xFC03 macro
Drtsx_chip.c1002 retval = rtsx_write_register(chip, CLK_DIV, 0x07, 0x07); in rtsx_init_chip()
/drivers/mmc/host/
Drtsx_usb_sdmmc.c600 rtsx_usb_add_cmd(ucr, WRITE_REG_CMD, CLK_DIV, CLK_CHANGE, CLK_CHANGE); in sd_change_phase()
612 rtsx_usb_add_cmd(ucr, WRITE_REG_CMD, CLK_DIV, CLK_CHANGE, 0); in sd_change_phase()