1 /*
2 * Texas Instruments Ethernet Switch Driver
3 *
4 * Copyright (C) 2012 Texas Instruments
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation version 2.
9 *
10 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
11 * kind, whether express or implied; without even the implied warranty
12 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16 #include <linux/kernel.h>
17 #include <linux/io.h>
18 #include <linux/clk.h>
19 #include <linux/timer.h>
20 #include <linux/module.h>
21 #include <linux/platform_device.h>
22 #include <linux/irqreturn.h>
23 #include <linux/interrupt.h>
24 #include <linux/if_ether.h>
25 #include <linux/etherdevice.h>
26 #include <linux/netdevice.h>
27 #include <linux/net_tstamp.h>
28 #include <linux/phy.h>
29 #include <linux/workqueue.h>
30 #include <linux/delay.h>
31 #include <linux/pm_runtime.h>
32 #include <linux/gpio.h>
33 #include <linux/of.h>
34 #include <linux/of_mdio.h>
35 #include <linux/of_net.h>
36 #include <linux/of_device.h>
37 #include <linux/if_vlan.h>
38
39 #include <linux/pinctrl/consumer.h>
40
41 #include "cpsw.h"
42 #include "cpsw_ale.h"
43 #include "cpts.h"
44 #include "davinci_cpdma.h"
45
46 #define CPSW_DEBUG (NETIF_MSG_HW | NETIF_MSG_WOL | \
47 NETIF_MSG_DRV | NETIF_MSG_LINK | \
48 NETIF_MSG_IFUP | NETIF_MSG_INTR | \
49 NETIF_MSG_PROBE | NETIF_MSG_TIMER | \
50 NETIF_MSG_IFDOWN | NETIF_MSG_RX_ERR | \
51 NETIF_MSG_TX_ERR | NETIF_MSG_TX_DONE | \
52 NETIF_MSG_PKTDATA | NETIF_MSG_TX_QUEUED | \
53 NETIF_MSG_RX_STATUS)
54
55 #define cpsw_info(priv, type, format, ...) \
56 do { \
57 if (netif_msg_##type(priv) && net_ratelimit()) \
58 dev_info(priv->dev, format, ## __VA_ARGS__); \
59 } while (0)
60
61 #define cpsw_err(priv, type, format, ...) \
62 do { \
63 if (netif_msg_##type(priv) && net_ratelimit()) \
64 dev_err(priv->dev, format, ## __VA_ARGS__); \
65 } while (0)
66
67 #define cpsw_dbg(priv, type, format, ...) \
68 do { \
69 if (netif_msg_##type(priv) && net_ratelimit()) \
70 dev_dbg(priv->dev, format, ## __VA_ARGS__); \
71 } while (0)
72
73 #define cpsw_notice(priv, type, format, ...) \
74 do { \
75 if (netif_msg_##type(priv) && net_ratelimit()) \
76 dev_notice(priv->dev, format, ## __VA_ARGS__); \
77 } while (0)
78
79 #define ALE_ALL_PORTS 0x7
80
81 #define CPSW_MAJOR_VERSION(reg) (reg >> 8 & 0x7)
82 #define CPSW_MINOR_VERSION(reg) (reg & 0xff)
83 #define CPSW_RTL_VERSION(reg) ((reg >> 11) & 0x1f)
84
85 #define CPSW_VERSION_1 0x19010a
86 #define CPSW_VERSION_2 0x19010c
87 #define CPSW_VERSION_3 0x19010f
88 #define CPSW_VERSION_4 0x190112
89
90 #define HOST_PORT_NUM 0
91 #define SLIVER_SIZE 0x40
92
93 #define CPSW1_HOST_PORT_OFFSET 0x028
94 #define CPSW1_SLAVE_OFFSET 0x050
95 #define CPSW1_SLAVE_SIZE 0x040
96 #define CPSW1_CPDMA_OFFSET 0x100
97 #define CPSW1_STATERAM_OFFSET 0x200
98 #define CPSW1_HW_STATS 0x400
99 #define CPSW1_CPTS_OFFSET 0x500
100 #define CPSW1_ALE_OFFSET 0x600
101 #define CPSW1_SLIVER_OFFSET 0x700
102
103 #define CPSW2_HOST_PORT_OFFSET 0x108
104 #define CPSW2_SLAVE_OFFSET 0x200
105 #define CPSW2_SLAVE_SIZE 0x100
106 #define CPSW2_CPDMA_OFFSET 0x800
107 #define CPSW2_HW_STATS 0x900
108 #define CPSW2_STATERAM_OFFSET 0xa00
109 #define CPSW2_CPTS_OFFSET 0xc00
110 #define CPSW2_ALE_OFFSET 0xd00
111 #define CPSW2_SLIVER_OFFSET 0xd80
112 #define CPSW2_BD_OFFSET 0x2000
113
114 #define CPDMA_RXTHRESH 0x0c0
115 #define CPDMA_RXFREE 0x0e0
116 #define CPDMA_TXHDP 0x00
117 #define CPDMA_RXHDP 0x20
118 #define CPDMA_TXCP 0x40
119 #define CPDMA_RXCP 0x60
120
121 #define CPSW_POLL_WEIGHT 64
122 #define CPSW_MIN_PACKET_SIZE 60
123 #define CPSW_MAX_PACKET_SIZE (1500 + 14 + 4 + 4)
124
125 #define RX_PRIORITY_MAPPING 0x76543210
126 #define TX_PRIORITY_MAPPING 0x33221100
127 #define CPDMA_TX_PRIORITY_MAP 0x76543210
128
129 #define CPSW_VLAN_AWARE BIT(1)
130 #define CPSW_ALE_VLAN_AWARE 1
131
132 #define CPSW_FIFO_NORMAL_MODE (0 << 16)
133 #define CPSW_FIFO_DUAL_MAC_MODE (1 << 16)
134 #define CPSW_FIFO_RATE_LIMIT_MODE (2 << 16)
135
136 #define CPSW_INTPACEEN (0x3f << 16)
137 #define CPSW_INTPRESCALE_MASK (0x7FF << 0)
138 #define CPSW_CMINTMAX_CNT 63
139 #define CPSW_CMINTMIN_CNT 2
140 #define CPSW_CMINTMAX_INTVL (1000 / CPSW_CMINTMIN_CNT)
141 #define CPSW_CMINTMIN_INTVL ((1000 / CPSW_CMINTMAX_CNT) + 1)
142
143 #define cpsw_slave_index(priv) \
144 ((priv->data.dual_emac) ? priv->emac_port : \
145 priv->data.active_slave)
146
147 static int debug_level;
148 module_param(debug_level, int, 0);
149 MODULE_PARM_DESC(debug_level, "cpsw debug level (NETIF_MSG bits)");
150
151 static int ale_ageout = 10;
152 module_param(ale_ageout, int, 0);
153 MODULE_PARM_DESC(ale_ageout, "cpsw ale ageout interval (seconds)");
154
155 static int rx_packet_max = CPSW_MAX_PACKET_SIZE;
156 module_param(rx_packet_max, int, 0);
157 MODULE_PARM_DESC(rx_packet_max, "maximum receive packet size (bytes)");
158
159 struct cpsw_wr_regs {
160 u32 id_ver;
161 u32 soft_reset;
162 u32 control;
163 u32 int_control;
164 u32 rx_thresh_en;
165 u32 rx_en;
166 u32 tx_en;
167 u32 misc_en;
168 u32 mem_allign1[8];
169 u32 rx_thresh_stat;
170 u32 rx_stat;
171 u32 tx_stat;
172 u32 misc_stat;
173 u32 mem_allign2[8];
174 u32 rx_imax;
175 u32 tx_imax;
176
177 };
178
179 struct cpsw_ss_regs {
180 u32 id_ver;
181 u32 control;
182 u32 soft_reset;
183 u32 stat_port_en;
184 u32 ptype;
185 u32 soft_idle;
186 u32 thru_rate;
187 u32 gap_thresh;
188 u32 tx_start_wds;
189 u32 flow_control;
190 u32 vlan_ltype;
191 u32 ts_ltype;
192 u32 dlr_ltype;
193 };
194
195 /* CPSW_PORT_V1 */
196 #define CPSW1_MAX_BLKS 0x00 /* Maximum FIFO Blocks */
197 #define CPSW1_BLK_CNT 0x04 /* FIFO Block Usage Count (Read Only) */
198 #define CPSW1_TX_IN_CTL 0x08 /* Transmit FIFO Control */
199 #define CPSW1_PORT_VLAN 0x0c /* VLAN Register */
200 #define CPSW1_TX_PRI_MAP 0x10 /* Tx Header Priority to Switch Pri Mapping */
201 #define CPSW1_TS_CTL 0x14 /* Time Sync Control */
202 #define CPSW1_TS_SEQ_LTYPE 0x18 /* Time Sync Sequence ID Offset and Msg Type */
203 #define CPSW1_TS_VLAN 0x1c /* Time Sync VLAN1 and VLAN2 */
204
205 /* CPSW_PORT_V2 */
206 #define CPSW2_CONTROL 0x00 /* Control Register */
207 #define CPSW2_MAX_BLKS 0x08 /* Maximum FIFO Blocks */
208 #define CPSW2_BLK_CNT 0x0c /* FIFO Block Usage Count (Read Only) */
209 #define CPSW2_TX_IN_CTL 0x10 /* Transmit FIFO Control */
210 #define CPSW2_PORT_VLAN 0x14 /* VLAN Register */
211 #define CPSW2_TX_PRI_MAP 0x18 /* Tx Header Priority to Switch Pri Mapping */
212 #define CPSW2_TS_SEQ_MTYPE 0x1c /* Time Sync Sequence ID Offset and Msg Type */
213
214 /* CPSW_PORT_V1 and V2 */
215 #define SA_LO 0x20 /* CPGMAC_SL Source Address Low */
216 #define SA_HI 0x24 /* CPGMAC_SL Source Address High */
217 #define SEND_PERCENT 0x28 /* Transmit Queue Send Percentages */
218
219 /* CPSW_PORT_V2 only */
220 #define RX_DSCP_PRI_MAP0 0x30 /* Rx DSCP Priority to Rx Packet Mapping */
221 #define RX_DSCP_PRI_MAP1 0x34 /* Rx DSCP Priority to Rx Packet Mapping */
222 #define RX_DSCP_PRI_MAP2 0x38 /* Rx DSCP Priority to Rx Packet Mapping */
223 #define RX_DSCP_PRI_MAP3 0x3c /* Rx DSCP Priority to Rx Packet Mapping */
224 #define RX_DSCP_PRI_MAP4 0x40 /* Rx DSCP Priority to Rx Packet Mapping */
225 #define RX_DSCP_PRI_MAP5 0x44 /* Rx DSCP Priority to Rx Packet Mapping */
226 #define RX_DSCP_PRI_MAP6 0x48 /* Rx DSCP Priority to Rx Packet Mapping */
227 #define RX_DSCP_PRI_MAP7 0x4c /* Rx DSCP Priority to Rx Packet Mapping */
228
229 /* Bit definitions for the CPSW2_CONTROL register */
230 #define PASS_PRI_TAGGED (1<<24) /* Pass Priority Tagged */
231 #define VLAN_LTYPE2_EN (1<<21) /* VLAN LTYPE 2 enable */
232 #define VLAN_LTYPE1_EN (1<<20) /* VLAN LTYPE 1 enable */
233 #define DSCP_PRI_EN (1<<16) /* DSCP Priority Enable */
234 #define TS_320 (1<<14) /* Time Sync Dest Port 320 enable */
235 #define TS_319 (1<<13) /* Time Sync Dest Port 319 enable */
236 #define TS_132 (1<<12) /* Time Sync Dest IP Addr 132 enable */
237 #define TS_131 (1<<11) /* Time Sync Dest IP Addr 131 enable */
238 #define TS_130 (1<<10) /* Time Sync Dest IP Addr 130 enable */
239 #define TS_129 (1<<9) /* Time Sync Dest IP Addr 129 enable */
240 #define TS_TTL_NONZERO (1<<8) /* Time Sync Time To Live Non-zero enable */
241 #define TS_ANNEX_F_EN (1<<6) /* Time Sync Annex F enable */
242 #define TS_ANNEX_D_EN (1<<4) /* Time Sync Annex D enable */
243 #define TS_LTYPE2_EN (1<<3) /* Time Sync LTYPE 2 enable */
244 #define TS_LTYPE1_EN (1<<2) /* Time Sync LTYPE 1 enable */
245 #define TS_TX_EN (1<<1) /* Time Sync Transmit Enable */
246 #define TS_RX_EN (1<<0) /* Time Sync Receive Enable */
247
248 #define CTRL_V2_TS_BITS \
249 (TS_320 | TS_319 | TS_132 | TS_131 | TS_130 | TS_129 |\
250 TS_TTL_NONZERO | TS_ANNEX_D_EN | TS_LTYPE1_EN)
251
252 #define CTRL_V2_ALL_TS_MASK (CTRL_V2_TS_BITS | TS_TX_EN | TS_RX_EN)
253 #define CTRL_V2_TX_TS_BITS (CTRL_V2_TS_BITS | TS_TX_EN)
254 #define CTRL_V2_RX_TS_BITS (CTRL_V2_TS_BITS | TS_RX_EN)
255
256
257 #define CTRL_V3_TS_BITS \
258 (TS_320 | TS_319 | TS_132 | TS_131 | TS_130 | TS_129 |\
259 TS_TTL_NONZERO | TS_ANNEX_F_EN | TS_ANNEX_D_EN |\
260 TS_LTYPE1_EN)
261
262 #define CTRL_V3_ALL_TS_MASK (CTRL_V3_TS_BITS | TS_TX_EN | TS_RX_EN)
263 #define CTRL_V3_TX_TS_BITS (CTRL_V3_TS_BITS | TS_TX_EN)
264 #define CTRL_V3_RX_TS_BITS (CTRL_V3_TS_BITS | TS_RX_EN)
265
266 /* Bit definitions for the CPSW2_TS_SEQ_MTYPE register */
267 #define TS_SEQ_ID_OFFSET_SHIFT (16) /* Time Sync Sequence ID Offset */
268 #define TS_SEQ_ID_OFFSET_MASK (0x3f)
269 #define TS_MSG_TYPE_EN_SHIFT (0) /* Time Sync Message Type Enable */
270 #define TS_MSG_TYPE_EN_MASK (0xffff)
271
272 /* The PTP event messages - Sync, Delay_Req, Pdelay_Req, and Pdelay_Resp. */
273 #define EVENT_MSG_BITS ((1<<0) | (1<<1) | (1<<2) | (1<<3))
274
275 /* Bit definitions for the CPSW1_TS_CTL register */
276 #define CPSW_V1_TS_RX_EN BIT(0)
277 #define CPSW_V1_TS_TX_EN BIT(4)
278 #define CPSW_V1_MSG_TYPE_OFS 16
279
280 /* Bit definitions for the CPSW1_TS_SEQ_LTYPE register */
281 #define CPSW_V1_SEQ_ID_OFS_SHIFT 16
282
283 #define CPSW_MAX_BLKS_TX 15
284 #define CPSW_MAX_BLKS_TX_SHIFT 4
285 #define CPSW_MAX_BLKS_RX 5
286
287 struct cpsw_host_regs {
288 u32 max_blks;
289 u32 blk_cnt;
290 u32 tx_in_ctl;
291 u32 port_vlan;
292 u32 tx_pri_map;
293 u32 cpdma_tx_pri_map;
294 u32 cpdma_rx_chan_map;
295 };
296
297 struct cpsw_sliver_regs {
298 u32 id_ver;
299 u32 mac_control;
300 u32 mac_status;
301 u32 soft_reset;
302 u32 rx_maxlen;
303 u32 __reserved_0;
304 u32 rx_pause;
305 u32 tx_pause;
306 u32 __reserved_1;
307 u32 rx_pri_map;
308 };
309
310 struct cpsw_hw_stats {
311 u32 rxgoodframes;
312 u32 rxbroadcastframes;
313 u32 rxmulticastframes;
314 u32 rxpauseframes;
315 u32 rxcrcerrors;
316 u32 rxaligncodeerrors;
317 u32 rxoversizedframes;
318 u32 rxjabberframes;
319 u32 rxundersizedframes;
320 u32 rxfragments;
321 u32 __pad_0[2];
322 u32 rxoctets;
323 u32 txgoodframes;
324 u32 txbroadcastframes;
325 u32 txmulticastframes;
326 u32 txpauseframes;
327 u32 txdeferredframes;
328 u32 txcollisionframes;
329 u32 txsinglecollframes;
330 u32 txmultcollframes;
331 u32 txexcessivecollisions;
332 u32 txlatecollisions;
333 u32 txunderrun;
334 u32 txcarriersenseerrors;
335 u32 txoctets;
336 u32 octetframes64;
337 u32 octetframes65t127;
338 u32 octetframes128t255;
339 u32 octetframes256t511;
340 u32 octetframes512t1023;
341 u32 octetframes1024tup;
342 u32 netoctets;
343 u32 rxsofoverruns;
344 u32 rxmofoverruns;
345 u32 rxdmaoverruns;
346 };
347
348 struct cpsw_slave {
349 void __iomem *regs;
350 struct cpsw_sliver_regs __iomem *sliver;
351 int slave_num;
352 u32 mac_control;
353 struct cpsw_slave_data *data;
354 struct phy_device *phy;
355 struct net_device *ndev;
356 u32 port_vlan;
357 u32 open_stat;
358 };
359
slave_read(struct cpsw_slave * slave,u32 offset)360 static inline u32 slave_read(struct cpsw_slave *slave, u32 offset)
361 {
362 return __raw_readl(slave->regs + offset);
363 }
364
slave_write(struct cpsw_slave * slave,u32 val,u32 offset)365 static inline void slave_write(struct cpsw_slave *slave, u32 val, u32 offset)
366 {
367 __raw_writel(val, slave->regs + offset);
368 }
369
370 struct cpsw_priv {
371 spinlock_t lock;
372 struct platform_device *pdev;
373 struct net_device *ndev;
374 struct napi_struct napi_rx;
375 struct napi_struct napi_tx;
376 struct device *dev;
377 struct cpsw_platform_data data;
378 struct cpsw_ss_regs __iomem *regs;
379 struct cpsw_wr_regs __iomem *wr_regs;
380 u8 __iomem *hw_stats;
381 struct cpsw_host_regs __iomem *host_port_regs;
382 u32 msg_enable;
383 u32 version;
384 u32 coal_intvl;
385 u32 bus_freq_mhz;
386 int rx_packet_max;
387 int host_port;
388 struct clk *clk;
389 u8 mac_addr[ETH_ALEN];
390 struct cpsw_slave *slaves;
391 struct cpdma_ctlr *dma;
392 struct cpdma_chan *txch, *rxch;
393 struct cpsw_ale *ale;
394 bool rx_pause;
395 bool tx_pause;
396 bool quirk_irq;
397 bool rx_irq_disabled;
398 bool tx_irq_disabled;
399 /* snapshot of IRQ numbers */
400 u32 irqs_table[4];
401 u32 num_irqs;
402 struct cpts *cpts;
403 u32 emac_port;
404 };
405
406 struct cpsw_stats {
407 char stat_string[ETH_GSTRING_LEN];
408 int type;
409 int sizeof_stat;
410 int stat_offset;
411 };
412
413 enum {
414 CPSW_STATS,
415 CPDMA_RX_STATS,
416 CPDMA_TX_STATS,
417 };
418
419 #define CPSW_STAT(m) CPSW_STATS, \
420 sizeof(((struct cpsw_hw_stats *)0)->m), \
421 offsetof(struct cpsw_hw_stats, m)
422 #define CPDMA_RX_STAT(m) CPDMA_RX_STATS, \
423 sizeof(((struct cpdma_chan_stats *)0)->m), \
424 offsetof(struct cpdma_chan_stats, m)
425 #define CPDMA_TX_STAT(m) CPDMA_TX_STATS, \
426 sizeof(((struct cpdma_chan_stats *)0)->m), \
427 offsetof(struct cpdma_chan_stats, m)
428
429 static const struct cpsw_stats cpsw_gstrings_stats[] = {
430 { "Good Rx Frames", CPSW_STAT(rxgoodframes) },
431 { "Broadcast Rx Frames", CPSW_STAT(rxbroadcastframes) },
432 { "Multicast Rx Frames", CPSW_STAT(rxmulticastframes) },
433 { "Pause Rx Frames", CPSW_STAT(rxpauseframes) },
434 { "Rx CRC Errors", CPSW_STAT(rxcrcerrors) },
435 { "Rx Align/Code Errors", CPSW_STAT(rxaligncodeerrors) },
436 { "Oversize Rx Frames", CPSW_STAT(rxoversizedframes) },
437 { "Rx Jabbers", CPSW_STAT(rxjabberframes) },
438 { "Undersize (Short) Rx Frames", CPSW_STAT(rxundersizedframes) },
439 { "Rx Fragments", CPSW_STAT(rxfragments) },
440 { "Rx Octets", CPSW_STAT(rxoctets) },
441 { "Good Tx Frames", CPSW_STAT(txgoodframes) },
442 { "Broadcast Tx Frames", CPSW_STAT(txbroadcastframes) },
443 { "Multicast Tx Frames", CPSW_STAT(txmulticastframes) },
444 { "Pause Tx Frames", CPSW_STAT(txpauseframes) },
445 { "Deferred Tx Frames", CPSW_STAT(txdeferredframes) },
446 { "Collisions", CPSW_STAT(txcollisionframes) },
447 { "Single Collision Tx Frames", CPSW_STAT(txsinglecollframes) },
448 { "Multiple Collision Tx Frames", CPSW_STAT(txmultcollframes) },
449 { "Excessive Collisions", CPSW_STAT(txexcessivecollisions) },
450 { "Late Collisions", CPSW_STAT(txlatecollisions) },
451 { "Tx Underrun", CPSW_STAT(txunderrun) },
452 { "Carrier Sense Errors", CPSW_STAT(txcarriersenseerrors) },
453 { "Tx Octets", CPSW_STAT(txoctets) },
454 { "Rx + Tx 64 Octet Frames", CPSW_STAT(octetframes64) },
455 { "Rx + Tx 65-127 Octet Frames", CPSW_STAT(octetframes65t127) },
456 { "Rx + Tx 128-255 Octet Frames", CPSW_STAT(octetframes128t255) },
457 { "Rx + Tx 256-511 Octet Frames", CPSW_STAT(octetframes256t511) },
458 { "Rx + Tx 512-1023 Octet Frames", CPSW_STAT(octetframes512t1023) },
459 { "Rx + Tx 1024-Up Octet Frames", CPSW_STAT(octetframes1024tup) },
460 { "Net Octets", CPSW_STAT(netoctets) },
461 { "Rx Start of Frame Overruns", CPSW_STAT(rxsofoverruns) },
462 { "Rx Middle of Frame Overruns", CPSW_STAT(rxmofoverruns) },
463 { "Rx DMA Overruns", CPSW_STAT(rxdmaoverruns) },
464 { "Rx DMA chan: head_enqueue", CPDMA_RX_STAT(head_enqueue) },
465 { "Rx DMA chan: tail_enqueue", CPDMA_RX_STAT(tail_enqueue) },
466 { "Rx DMA chan: pad_enqueue", CPDMA_RX_STAT(pad_enqueue) },
467 { "Rx DMA chan: misqueued", CPDMA_RX_STAT(misqueued) },
468 { "Rx DMA chan: desc_alloc_fail", CPDMA_RX_STAT(desc_alloc_fail) },
469 { "Rx DMA chan: pad_alloc_fail", CPDMA_RX_STAT(pad_alloc_fail) },
470 { "Rx DMA chan: runt_receive_buf", CPDMA_RX_STAT(runt_receive_buff) },
471 { "Rx DMA chan: runt_transmit_buf", CPDMA_RX_STAT(runt_transmit_buff) },
472 { "Rx DMA chan: empty_dequeue", CPDMA_RX_STAT(empty_dequeue) },
473 { "Rx DMA chan: busy_dequeue", CPDMA_RX_STAT(busy_dequeue) },
474 { "Rx DMA chan: good_dequeue", CPDMA_RX_STAT(good_dequeue) },
475 { "Rx DMA chan: requeue", CPDMA_RX_STAT(requeue) },
476 { "Rx DMA chan: teardown_dequeue", CPDMA_RX_STAT(teardown_dequeue) },
477 { "Tx DMA chan: head_enqueue", CPDMA_TX_STAT(head_enqueue) },
478 { "Tx DMA chan: tail_enqueue", CPDMA_TX_STAT(tail_enqueue) },
479 { "Tx DMA chan: pad_enqueue", CPDMA_TX_STAT(pad_enqueue) },
480 { "Tx DMA chan: misqueued", CPDMA_TX_STAT(misqueued) },
481 { "Tx DMA chan: desc_alloc_fail", CPDMA_TX_STAT(desc_alloc_fail) },
482 { "Tx DMA chan: pad_alloc_fail", CPDMA_TX_STAT(pad_alloc_fail) },
483 { "Tx DMA chan: runt_receive_buf", CPDMA_TX_STAT(runt_receive_buff) },
484 { "Tx DMA chan: runt_transmit_buf", CPDMA_TX_STAT(runt_transmit_buff) },
485 { "Tx DMA chan: empty_dequeue", CPDMA_TX_STAT(empty_dequeue) },
486 { "Tx DMA chan: busy_dequeue", CPDMA_TX_STAT(busy_dequeue) },
487 { "Tx DMA chan: good_dequeue", CPDMA_TX_STAT(good_dequeue) },
488 { "Tx DMA chan: requeue", CPDMA_TX_STAT(requeue) },
489 { "Tx DMA chan: teardown_dequeue", CPDMA_TX_STAT(teardown_dequeue) },
490 };
491
492 #define CPSW_STATS_LEN ARRAY_SIZE(cpsw_gstrings_stats)
493
494 #define napi_to_priv(napi) container_of(napi, struct cpsw_priv, napi)
495 #define for_each_slave(priv, func, arg...) \
496 do { \
497 struct cpsw_slave *slave; \
498 int n; \
499 if (priv->data.dual_emac) \
500 (func)((priv)->slaves + priv->emac_port, ##arg);\
501 else \
502 for (n = (priv)->data.slaves, \
503 slave = (priv)->slaves; \
504 n; n--) \
505 (func)(slave++, ##arg); \
506 } while (0)
507 #define cpsw_get_slave_ndev(priv, __slave_no__) \
508 ((__slave_no__ < priv->data.slaves) ? \
509 priv->slaves[__slave_no__].ndev : NULL)
510 #define cpsw_get_slave_priv(priv, __slave_no__) \
511 (((__slave_no__ < priv->data.slaves) && \
512 (priv->slaves[__slave_no__].ndev)) ? \
513 netdev_priv(priv->slaves[__slave_no__].ndev) : NULL) \
514
515 #define cpsw_dual_emac_src_port_detect(status, priv, ndev, skb) \
516 do { \
517 if (!priv->data.dual_emac) \
518 break; \
519 if (CPDMA_RX_SOURCE_PORT(status) == 1) { \
520 ndev = cpsw_get_slave_ndev(priv, 0); \
521 priv = netdev_priv(ndev); \
522 skb->dev = ndev; \
523 } else if (CPDMA_RX_SOURCE_PORT(status) == 2) { \
524 ndev = cpsw_get_slave_ndev(priv, 1); \
525 priv = netdev_priv(ndev); \
526 skb->dev = ndev; \
527 } \
528 } while (0)
529 #define cpsw_add_mcast(priv, addr) \
530 do { \
531 if (priv->data.dual_emac) { \
532 struct cpsw_slave *slave = priv->slaves + \
533 priv->emac_port; \
534 int slave_port = cpsw_get_slave_port(priv, \
535 slave->slave_num); \
536 cpsw_ale_add_mcast(priv->ale, addr, \
537 1 << slave_port | 1 << priv->host_port, \
538 ALE_VLAN, slave->port_vlan, 0); \
539 } else { \
540 cpsw_ale_add_mcast(priv->ale, addr, \
541 ALE_ALL_PORTS << priv->host_port, \
542 0, 0, 0); \
543 } \
544 } while (0)
545
cpsw_get_slave_port(struct cpsw_priv * priv,u32 slave_num)546 static inline int cpsw_get_slave_port(struct cpsw_priv *priv, u32 slave_num)
547 {
548 if (priv->host_port == 0)
549 return slave_num + 1;
550 else
551 return slave_num;
552 }
553
cpsw_set_promiscious(struct net_device * ndev,bool enable)554 static void cpsw_set_promiscious(struct net_device *ndev, bool enable)
555 {
556 struct cpsw_priv *priv = netdev_priv(ndev);
557 struct cpsw_ale *ale = priv->ale;
558 int i;
559
560 if (priv->data.dual_emac) {
561 bool flag = false;
562
563 /* Enabling promiscuous mode for one interface will be
564 * common for both the interface as the interface shares
565 * the same hardware resource.
566 */
567 for (i = 0; i < priv->data.slaves; i++)
568 if (priv->slaves[i].ndev->flags & IFF_PROMISC)
569 flag = true;
570
571 if (!enable && flag) {
572 enable = true;
573 dev_err(&ndev->dev, "promiscuity not disabled as the other interface is still in promiscuity mode\n");
574 }
575
576 if (enable) {
577 /* Enable Bypass */
578 cpsw_ale_control_set(ale, 0, ALE_BYPASS, 1);
579
580 dev_dbg(&ndev->dev, "promiscuity enabled\n");
581 } else {
582 /* Disable Bypass */
583 cpsw_ale_control_set(ale, 0, ALE_BYPASS, 0);
584 dev_dbg(&ndev->dev, "promiscuity disabled\n");
585 }
586 } else {
587 if (enable) {
588 unsigned long timeout = jiffies + HZ;
589
590 /* Disable Learn for all ports (host is port 0 and slaves are port 1 and up */
591 for (i = 0; i <= priv->data.slaves; i++) {
592 cpsw_ale_control_set(ale, i,
593 ALE_PORT_NOLEARN, 1);
594 cpsw_ale_control_set(ale, i,
595 ALE_PORT_NO_SA_UPDATE, 1);
596 }
597
598 /* Clear All Untouched entries */
599 cpsw_ale_control_set(ale, 0, ALE_AGEOUT, 1);
600 do {
601 cpu_relax();
602 if (cpsw_ale_control_get(ale, 0, ALE_AGEOUT))
603 break;
604 } while (time_after(timeout, jiffies));
605 cpsw_ale_control_set(ale, 0, ALE_AGEOUT, 1);
606
607 /* Clear all mcast from ALE */
608 cpsw_ale_flush_multicast(ale, ALE_ALL_PORTS <<
609 priv->host_port, -1);
610
611 /* Flood All Unicast Packets to Host port */
612 cpsw_ale_control_set(ale, 0, ALE_P0_UNI_FLOOD, 1);
613 dev_dbg(&ndev->dev, "promiscuity enabled\n");
614 } else {
615 /* Don't Flood All Unicast Packets to Host port */
616 cpsw_ale_control_set(ale, 0, ALE_P0_UNI_FLOOD, 0);
617
618 /* Enable Learn for all ports (host is port 0 and slaves are port 1 and up */
619 for (i = 0; i <= priv->data.slaves; i++) {
620 cpsw_ale_control_set(ale, i,
621 ALE_PORT_NOLEARN, 0);
622 cpsw_ale_control_set(ale, i,
623 ALE_PORT_NO_SA_UPDATE, 0);
624 }
625 dev_dbg(&ndev->dev, "promiscuity disabled\n");
626 }
627 }
628 }
629
cpsw_ndo_set_rx_mode(struct net_device * ndev)630 static void cpsw_ndo_set_rx_mode(struct net_device *ndev)
631 {
632 struct cpsw_priv *priv = netdev_priv(ndev);
633 int vid;
634
635 if (priv->data.dual_emac)
636 vid = priv->slaves[priv->emac_port].port_vlan;
637 else
638 vid = priv->data.default_vlan;
639
640 if (ndev->flags & IFF_PROMISC) {
641 /* Enable promiscuous mode */
642 cpsw_set_promiscious(ndev, true);
643 cpsw_ale_set_allmulti(priv->ale, IFF_ALLMULTI);
644 return;
645 } else {
646 /* Disable promiscuous mode */
647 cpsw_set_promiscious(ndev, false);
648 }
649
650 /* Restore allmulti on vlans if necessary */
651 cpsw_ale_set_allmulti(priv->ale, priv->ndev->flags & IFF_ALLMULTI);
652
653 /* Clear all mcast from ALE */
654 cpsw_ale_flush_multicast(priv->ale, ALE_ALL_PORTS << priv->host_port,
655 vid);
656
657 if (!netdev_mc_empty(ndev)) {
658 struct netdev_hw_addr *ha;
659
660 /* program multicast address list into ALE register */
661 netdev_for_each_mc_addr(ha, ndev) {
662 cpsw_add_mcast(priv, (u8 *)ha->addr);
663 }
664 }
665 }
666
cpsw_intr_enable(struct cpsw_priv * priv)667 static void cpsw_intr_enable(struct cpsw_priv *priv)
668 {
669 __raw_writel(0xFF, &priv->wr_regs->tx_en);
670 __raw_writel(0xFF, &priv->wr_regs->rx_en);
671
672 cpdma_ctlr_int_ctrl(priv->dma, true);
673 return;
674 }
675
cpsw_intr_disable(struct cpsw_priv * priv)676 static void cpsw_intr_disable(struct cpsw_priv *priv)
677 {
678 __raw_writel(0, &priv->wr_regs->tx_en);
679 __raw_writel(0, &priv->wr_regs->rx_en);
680
681 cpdma_ctlr_int_ctrl(priv->dma, false);
682 return;
683 }
684
cpsw_tx_handler(void * token,int len,int status)685 static void cpsw_tx_handler(void *token, int len, int status)
686 {
687 struct sk_buff *skb = token;
688 struct net_device *ndev = skb->dev;
689 struct cpsw_priv *priv = netdev_priv(ndev);
690
691 /* Check whether the queue is stopped due to stalled tx dma, if the
692 * queue is stopped then start the queue as we have free desc for tx
693 */
694 if (unlikely(netif_queue_stopped(ndev)))
695 netif_wake_queue(ndev);
696 cpts_tx_timestamp(priv->cpts, skb);
697 ndev->stats.tx_packets++;
698 ndev->stats.tx_bytes += len;
699 dev_kfree_skb_any(skb);
700 }
701
cpsw_rx_handler(void * token,int len,int status)702 static void cpsw_rx_handler(void *token, int len, int status)
703 {
704 struct sk_buff *skb = token;
705 struct sk_buff *new_skb;
706 struct net_device *ndev = skb->dev;
707 struct cpsw_priv *priv = netdev_priv(ndev);
708 int ret = 0;
709
710 cpsw_dual_emac_src_port_detect(status, priv, ndev, skb);
711
712 if (unlikely(status < 0) || unlikely(!netif_running(ndev))) {
713 bool ndev_status = false;
714 struct cpsw_slave *slave = priv->slaves;
715 int n;
716
717 if (priv->data.dual_emac) {
718 /* In dual emac mode check for all interfaces */
719 for (n = priv->data.slaves; n; n--, slave++)
720 if (netif_running(slave->ndev))
721 ndev_status = true;
722 }
723
724 if (ndev_status && (status >= 0)) {
725 /* The packet received is for the interface which
726 * is already down and the other interface is up
727 * and running, instead of freeing which results
728 * in reducing of the number of rx descriptor in
729 * DMA engine, requeue skb back to cpdma.
730 */
731 new_skb = skb;
732 goto requeue;
733 }
734
735 /* the interface is going down, skbs are purged */
736 dev_kfree_skb_any(skb);
737 return;
738 }
739
740 new_skb = netdev_alloc_skb_ip_align(ndev, priv->rx_packet_max);
741 if (new_skb) {
742 skb_put(skb, len);
743 cpts_rx_timestamp(priv->cpts, skb);
744 skb->protocol = eth_type_trans(skb, ndev);
745 netif_receive_skb(skb);
746 ndev->stats.rx_bytes += len;
747 ndev->stats.rx_packets++;
748 } else {
749 ndev->stats.rx_dropped++;
750 new_skb = skb;
751 }
752
753 requeue:
754 ret = cpdma_chan_submit(priv->rxch, new_skb, new_skb->data,
755 skb_tailroom(new_skb), 0);
756 if (WARN_ON(ret < 0))
757 dev_kfree_skb_any(new_skb);
758 }
759
cpsw_tx_interrupt(int irq,void * dev_id)760 static irqreturn_t cpsw_tx_interrupt(int irq, void *dev_id)
761 {
762 struct cpsw_priv *priv = dev_id;
763
764 writel(0, &priv->wr_regs->tx_en);
765 cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_TX);
766
767 if (priv->quirk_irq) {
768 disable_irq_nosync(priv->irqs_table[1]);
769 priv->tx_irq_disabled = true;
770 }
771
772 napi_schedule(&priv->napi_tx);
773 return IRQ_HANDLED;
774 }
775
cpsw_rx_interrupt(int irq,void * dev_id)776 static irqreturn_t cpsw_rx_interrupt(int irq, void *dev_id)
777 {
778 struct cpsw_priv *priv = dev_id;
779
780 writel(0, &priv->wr_regs->rx_en);
781 cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_RX);
782
783 if (priv->quirk_irq) {
784 disable_irq_nosync(priv->irqs_table[0]);
785 priv->rx_irq_disabled = true;
786 }
787
788 napi_schedule(&priv->napi_rx);
789 return IRQ_HANDLED;
790 }
791
cpsw_tx_poll(struct napi_struct * napi_tx,int budget)792 static int cpsw_tx_poll(struct napi_struct *napi_tx, int budget)
793 {
794 struct cpsw_priv *priv = napi_to_priv(napi_tx);
795 int num_tx;
796
797 num_tx = cpdma_chan_process(priv->txch, budget);
798 if (num_tx < budget) {
799 napi_complete(napi_tx);
800 writel(0xff, &priv->wr_regs->tx_en);
801 if (priv->quirk_irq && priv->tx_irq_disabled) {
802 priv->tx_irq_disabled = false;
803 enable_irq(priv->irqs_table[1]);
804 }
805 }
806
807 if (num_tx)
808 cpsw_dbg(priv, intr, "poll %d tx pkts\n", num_tx);
809
810 return num_tx;
811 }
812
cpsw_rx_poll(struct napi_struct * napi_rx,int budget)813 static int cpsw_rx_poll(struct napi_struct *napi_rx, int budget)
814 {
815 struct cpsw_priv *priv = napi_to_priv(napi_rx);
816 int num_rx;
817
818 num_rx = cpdma_chan_process(priv->rxch, budget);
819 if (num_rx < budget) {
820 napi_complete(napi_rx);
821 writel(0xff, &priv->wr_regs->rx_en);
822 if (priv->quirk_irq && priv->rx_irq_disabled) {
823 priv->rx_irq_disabled = false;
824 enable_irq(priv->irqs_table[0]);
825 }
826 }
827
828 if (num_rx)
829 cpsw_dbg(priv, intr, "poll %d rx pkts\n", num_rx);
830
831 return num_rx;
832 }
833
soft_reset(const char * module,void __iomem * reg)834 static inline void soft_reset(const char *module, void __iomem *reg)
835 {
836 unsigned long timeout = jiffies + HZ;
837
838 __raw_writel(1, reg);
839 do {
840 cpu_relax();
841 } while ((__raw_readl(reg) & 1) && time_after(timeout, jiffies));
842
843 WARN(__raw_readl(reg) & 1, "failed to soft-reset %s\n", module);
844 }
845
846 #define mac_hi(mac) (((mac)[0] << 0) | ((mac)[1] << 8) | \
847 ((mac)[2] << 16) | ((mac)[3] << 24))
848 #define mac_lo(mac) (((mac)[4] << 0) | ((mac)[5] << 8))
849
cpsw_set_slave_mac(struct cpsw_slave * slave,struct cpsw_priv * priv)850 static void cpsw_set_slave_mac(struct cpsw_slave *slave,
851 struct cpsw_priv *priv)
852 {
853 slave_write(slave, mac_hi(priv->mac_addr), SA_HI);
854 slave_write(slave, mac_lo(priv->mac_addr), SA_LO);
855 }
856
_cpsw_adjust_link(struct cpsw_slave * slave,struct cpsw_priv * priv,bool * link)857 static void _cpsw_adjust_link(struct cpsw_slave *slave,
858 struct cpsw_priv *priv, bool *link)
859 {
860 struct phy_device *phy = slave->phy;
861 u32 mac_control = 0;
862 u32 slave_port;
863
864 if (!phy)
865 return;
866
867 slave_port = cpsw_get_slave_port(priv, slave->slave_num);
868
869 if (phy->link) {
870 mac_control = priv->data.mac_control;
871
872 /* enable forwarding */
873 cpsw_ale_control_set(priv->ale, slave_port,
874 ALE_PORT_STATE, ALE_PORT_STATE_FORWARD);
875
876 if (phy->speed == 1000)
877 mac_control |= BIT(7); /* GIGABITEN */
878 if (phy->duplex)
879 mac_control |= BIT(0); /* FULLDUPLEXEN */
880
881 /* set speed_in input in case RMII mode is used in 100Mbps */
882 if (phy->speed == 100)
883 mac_control |= BIT(15);
884 /* in band mode only works in 10Mbps RGMII mode */
885 else if ((phy->speed == 10) && phy_interface_is_rgmii(phy))
886 mac_control |= BIT(18); /* In Band mode */
887
888 if (priv->rx_pause)
889 mac_control |= BIT(3);
890
891 if (priv->tx_pause)
892 mac_control |= BIT(4);
893
894 *link = true;
895 } else {
896 mac_control = 0;
897 /* disable forwarding */
898 cpsw_ale_control_set(priv->ale, slave_port,
899 ALE_PORT_STATE, ALE_PORT_STATE_DISABLE);
900 }
901
902 if (mac_control != slave->mac_control) {
903 phy_print_status(phy);
904 __raw_writel(mac_control, &slave->sliver->mac_control);
905 }
906
907 slave->mac_control = mac_control;
908 }
909
cpsw_adjust_link(struct net_device * ndev)910 static void cpsw_adjust_link(struct net_device *ndev)
911 {
912 struct cpsw_priv *priv = netdev_priv(ndev);
913 bool link = false;
914
915 for_each_slave(priv, _cpsw_adjust_link, priv, &link);
916
917 if (link) {
918 netif_carrier_on(ndev);
919 if (netif_running(ndev))
920 netif_wake_queue(ndev);
921 } else {
922 netif_carrier_off(ndev);
923 netif_stop_queue(ndev);
924 }
925 }
926
cpsw_get_coalesce(struct net_device * ndev,struct ethtool_coalesce * coal)927 static int cpsw_get_coalesce(struct net_device *ndev,
928 struct ethtool_coalesce *coal)
929 {
930 struct cpsw_priv *priv = netdev_priv(ndev);
931
932 coal->rx_coalesce_usecs = priv->coal_intvl;
933 return 0;
934 }
935
cpsw_set_coalesce(struct net_device * ndev,struct ethtool_coalesce * coal)936 static int cpsw_set_coalesce(struct net_device *ndev,
937 struct ethtool_coalesce *coal)
938 {
939 struct cpsw_priv *priv = netdev_priv(ndev);
940 u32 int_ctrl;
941 u32 num_interrupts = 0;
942 u32 prescale = 0;
943 u32 addnl_dvdr = 1;
944 u32 coal_intvl = 0;
945
946 coal_intvl = coal->rx_coalesce_usecs;
947
948 int_ctrl = readl(&priv->wr_regs->int_control);
949 prescale = priv->bus_freq_mhz * 4;
950
951 if (!coal->rx_coalesce_usecs) {
952 int_ctrl &= ~(CPSW_INTPRESCALE_MASK | CPSW_INTPACEEN);
953 goto update_return;
954 }
955
956 if (coal_intvl < CPSW_CMINTMIN_INTVL)
957 coal_intvl = CPSW_CMINTMIN_INTVL;
958
959 if (coal_intvl > CPSW_CMINTMAX_INTVL) {
960 /* Interrupt pacer works with 4us Pulse, we can
961 * throttle further by dilating the 4us pulse.
962 */
963 addnl_dvdr = CPSW_INTPRESCALE_MASK / prescale;
964
965 if (addnl_dvdr > 1) {
966 prescale *= addnl_dvdr;
967 if (coal_intvl > (CPSW_CMINTMAX_INTVL * addnl_dvdr))
968 coal_intvl = (CPSW_CMINTMAX_INTVL
969 * addnl_dvdr);
970 } else {
971 addnl_dvdr = 1;
972 coal_intvl = CPSW_CMINTMAX_INTVL;
973 }
974 }
975
976 num_interrupts = (1000 * addnl_dvdr) / coal_intvl;
977 writel(num_interrupts, &priv->wr_regs->rx_imax);
978 writel(num_interrupts, &priv->wr_regs->tx_imax);
979
980 int_ctrl |= CPSW_INTPACEEN;
981 int_ctrl &= (~CPSW_INTPRESCALE_MASK);
982 int_ctrl |= (prescale & CPSW_INTPRESCALE_MASK);
983
984 update_return:
985 writel(int_ctrl, &priv->wr_regs->int_control);
986
987 cpsw_notice(priv, timer, "Set coalesce to %d usecs.\n", coal_intvl);
988 if (priv->data.dual_emac) {
989 int i;
990
991 for (i = 0; i < priv->data.slaves; i++) {
992 priv = netdev_priv(priv->slaves[i].ndev);
993 priv->coal_intvl = coal_intvl;
994 }
995 } else {
996 priv->coal_intvl = coal_intvl;
997 }
998
999 return 0;
1000 }
1001
cpsw_get_sset_count(struct net_device * ndev,int sset)1002 static int cpsw_get_sset_count(struct net_device *ndev, int sset)
1003 {
1004 switch (sset) {
1005 case ETH_SS_STATS:
1006 return CPSW_STATS_LEN;
1007 default:
1008 return -EOPNOTSUPP;
1009 }
1010 }
1011
cpsw_get_strings(struct net_device * ndev,u32 stringset,u8 * data)1012 static void cpsw_get_strings(struct net_device *ndev, u32 stringset, u8 *data)
1013 {
1014 u8 *p = data;
1015 int i;
1016
1017 switch (stringset) {
1018 case ETH_SS_STATS:
1019 for (i = 0; i < CPSW_STATS_LEN; i++) {
1020 memcpy(p, cpsw_gstrings_stats[i].stat_string,
1021 ETH_GSTRING_LEN);
1022 p += ETH_GSTRING_LEN;
1023 }
1024 break;
1025 }
1026 }
1027
cpsw_get_ethtool_stats(struct net_device * ndev,struct ethtool_stats * stats,u64 * data)1028 static void cpsw_get_ethtool_stats(struct net_device *ndev,
1029 struct ethtool_stats *stats, u64 *data)
1030 {
1031 struct cpsw_priv *priv = netdev_priv(ndev);
1032 struct cpdma_chan_stats rx_stats;
1033 struct cpdma_chan_stats tx_stats;
1034 u32 val;
1035 u8 *p;
1036 int i;
1037
1038 /* Collect Davinci CPDMA stats for Rx and Tx Channel */
1039 cpdma_chan_get_stats(priv->rxch, &rx_stats);
1040 cpdma_chan_get_stats(priv->txch, &tx_stats);
1041
1042 for (i = 0; i < CPSW_STATS_LEN; i++) {
1043 switch (cpsw_gstrings_stats[i].type) {
1044 case CPSW_STATS:
1045 val = readl(priv->hw_stats +
1046 cpsw_gstrings_stats[i].stat_offset);
1047 data[i] = val;
1048 break;
1049
1050 case CPDMA_RX_STATS:
1051 p = (u8 *)&rx_stats +
1052 cpsw_gstrings_stats[i].stat_offset;
1053 data[i] = *(u32 *)p;
1054 break;
1055
1056 case CPDMA_TX_STATS:
1057 p = (u8 *)&tx_stats +
1058 cpsw_gstrings_stats[i].stat_offset;
1059 data[i] = *(u32 *)p;
1060 break;
1061 }
1062 }
1063 }
1064
cpsw_common_res_usage_state(struct cpsw_priv * priv)1065 static int cpsw_common_res_usage_state(struct cpsw_priv *priv)
1066 {
1067 u32 i;
1068 u32 usage_count = 0;
1069
1070 if (!priv->data.dual_emac)
1071 return 0;
1072
1073 for (i = 0; i < priv->data.slaves; i++)
1074 if (priv->slaves[i].open_stat)
1075 usage_count++;
1076
1077 return usage_count;
1078 }
1079
cpsw_tx_packet_submit(struct net_device * ndev,struct cpsw_priv * priv,struct sk_buff * skb)1080 static inline int cpsw_tx_packet_submit(struct net_device *ndev,
1081 struct cpsw_priv *priv, struct sk_buff *skb)
1082 {
1083 if (!priv->data.dual_emac)
1084 return cpdma_chan_submit(priv->txch, skb, skb->data,
1085 skb->len, 0);
1086
1087 if (ndev == cpsw_get_slave_ndev(priv, 0))
1088 return cpdma_chan_submit(priv->txch, skb, skb->data,
1089 skb->len, 1);
1090 else
1091 return cpdma_chan_submit(priv->txch, skb, skb->data,
1092 skb->len, 2);
1093 }
1094
cpsw_add_dual_emac_def_ale_entries(struct cpsw_priv * priv,struct cpsw_slave * slave,u32 slave_port)1095 static inline void cpsw_add_dual_emac_def_ale_entries(
1096 struct cpsw_priv *priv, struct cpsw_slave *slave,
1097 u32 slave_port)
1098 {
1099 u32 port_mask = 1 << slave_port | 1 << priv->host_port;
1100
1101 if (priv->version == CPSW_VERSION_1)
1102 slave_write(slave, slave->port_vlan, CPSW1_PORT_VLAN);
1103 else
1104 slave_write(slave, slave->port_vlan, CPSW2_PORT_VLAN);
1105 cpsw_ale_add_vlan(priv->ale, slave->port_vlan, port_mask,
1106 port_mask, port_mask, 0);
1107 cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast,
1108 port_mask, ALE_VLAN, slave->port_vlan, 0);
1109 cpsw_ale_add_ucast(priv->ale, priv->mac_addr,
1110 priv->host_port, ALE_VLAN | ALE_SECURE, slave->port_vlan);
1111 }
1112
soft_reset_slave(struct cpsw_slave * slave)1113 static void soft_reset_slave(struct cpsw_slave *slave)
1114 {
1115 char name[32];
1116
1117 snprintf(name, sizeof(name), "slave-%d", slave->slave_num);
1118 soft_reset(name, &slave->sliver->soft_reset);
1119 }
1120
cpsw_slave_open(struct cpsw_slave * slave,struct cpsw_priv * priv)1121 static void cpsw_slave_open(struct cpsw_slave *slave, struct cpsw_priv *priv)
1122 {
1123 u32 slave_port;
1124
1125 soft_reset_slave(slave);
1126
1127 /* setup priority mapping */
1128 __raw_writel(RX_PRIORITY_MAPPING, &slave->sliver->rx_pri_map);
1129
1130 switch (priv->version) {
1131 case CPSW_VERSION_1:
1132 slave_write(slave, TX_PRIORITY_MAPPING, CPSW1_TX_PRI_MAP);
1133 /* Increase RX FIFO size to 5 for supporting fullduplex
1134 * flow control mode
1135 */
1136 slave_write(slave,
1137 (CPSW_MAX_BLKS_TX << CPSW_MAX_BLKS_TX_SHIFT) |
1138 CPSW_MAX_BLKS_RX, CPSW1_MAX_BLKS);
1139 break;
1140 case CPSW_VERSION_2:
1141 case CPSW_VERSION_3:
1142 case CPSW_VERSION_4:
1143 slave_write(slave, TX_PRIORITY_MAPPING, CPSW2_TX_PRI_MAP);
1144 /* Increase RX FIFO size to 5 for supporting fullduplex
1145 * flow control mode
1146 */
1147 slave_write(slave,
1148 (CPSW_MAX_BLKS_TX << CPSW_MAX_BLKS_TX_SHIFT) |
1149 CPSW_MAX_BLKS_RX, CPSW2_MAX_BLKS);
1150 break;
1151 }
1152
1153 /* setup max packet size, and mac address */
1154 __raw_writel(priv->rx_packet_max, &slave->sliver->rx_maxlen);
1155 cpsw_set_slave_mac(slave, priv);
1156
1157 slave->mac_control = 0; /* no link yet */
1158
1159 slave_port = cpsw_get_slave_port(priv, slave->slave_num);
1160
1161 if (priv->data.dual_emac)
1162 cpsw_add_dual_emac_def_ale_entries(priv, slave, slave_port);
1163 else
1164 cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast,
1165 1 << slave_port, 0, 0, ALE_MCAST_FWD_2);
1166
1167 if (slave->data->phy_node) {
1168 slave->phy = of_phy_connect(priv->ndev, slave->data->phy_node,
1169 &cpsw_adjust_link, 0, slave->data->phy_if);
1170 if (!slave->phy) {
1171 dev_err(priv->dev, "phy \"%s\" not found on slave %d\n",
1172 slave->data->phy_node->full_name,
1173 slave->slave_num);
1174 return;
1175 }
1176 } else {
1177 slave->phy = phy_connect(priv->ndev, slave->data->phy_id,
1178 &cpsw_adjust_link, slave->data->phy_if);
1179 if (IS_ERR(slave->phy)) {
1180 dev_err(priv->dev,
1181 "phy \"%s\" not found on slave %d, err %ld\n",
1182 slave->data->phy_id, slave->slave_num,
1183 PTR_ERR(slave->phy));
1184 slave->phy = NULL;
1185 return;
1186 }
1187 }
1188
1189 dev_info(priv->dev, "phy found : id is : 0x%x\n", slave->phy->phy_id);
1190
1191 phy_start(slave->phy);
1192
1193 /* Configure GMII_SEL register */
1194 cpsw_phy_sel(&priv->pdev->dev, slave->phy->interface, slave->slave_num);
1195 }
1196
cpsw_add_default_vlan(struct cpsw_priv * priv)1197 static inline void cpsw_add_default_vlan(struct cpsw_priv *priv)
1198 {
1199 const int vlan = priv->data.default_vlan;
1200 const int port = priv->host_port;
1201 u32 reg;
1202 int i;
1203 int unreg_mcast_mask;
1204
1205 reg = (priv->version == CPSW_VERSION_1) ? CPSW1_PORT_VLAN :
1206 CPSW2_PORT_VLAN;
1207
1208 writel(vlan, &priv->host_port_regs->port_vlan);
1209
1210 for (i = 0; i < priv->data.slaves; i++)
1211 slave_write(priv->slaves + i, vlan, reg);
1212
1213 if (priv->ndev->flags & IFF_ALLMULTI)
1214 unreg_mcast_mask = ALE_ALL_PORTS;
1215 else
1216 unreg_mcast_mask = ALE_PORT_1 | ALE_PORT_2;
1217
1218 cpsw_ale_add_vlan(priv->ale, vlan, ALE_ALL_PORTS << port,
1219 ALE_ALL_PORTS << port, ALE_ALL_PORTS << port,
1220 unreg_mcast_mask << port);
1221 }
1222
cpsw_init_host_port(struct cpsw_priv * priv)1223 static void cpsw_init_host_port(struct cpsw_priv *priv)
1224 {
1225 u32 control_reg;
1226 u32 fifo_mode;
1227
1228 /* soft reset the controller and initialize ale */
1229 soft_reset("cpsw", &priv->regs->soft_reset);
1230 cpsw_ale_start(priv->ale);
1231
1232 /* switch to vlan unaware mode */
1233 cpsw_ale_control_set(priv->ale, priv->host_port, ALE_VLAN_AWARE,
1234 CPSW_ALE_VLAN_AWARE);
1235 control_reg = readl(&priv->regs->control);
1236 control_reg |= CPSW_VLAN_AWARE;
1237 writel(control_reg, &priv->regs->control);
1238 fifo_mode = (priv->data.dual_emac) ? CPSW_FIFO_DUAL_MAC_MODE :
1239 CPSW_FIFO_NORMAL_MODE;
1240 writel(fifo_mode, &priv->host_port_regs->tx_in_ctl);
1241
1242 /* setup host port priority mapping */
1243 __raw_writel(CPDMA_TX_PRIORITY_MAP,
1244 &priv->host_port_regs->cpdma_tx_pri_map);
1245 __raw_writel(0, &priv->host_port_regs->cpdma_rx_chan_map);
1246
1247 cpsw_ale_control_set(priv->ale, priv->host_port,
1248 ALE_PORT_STATE, ALE_PORT_STATE_FORWARD);
1249
1250 if (!priv->data.dual_emac) {
1251 cpsw_ale_add_ucast(priv->ale, priv->mac_addr, priv->host_port,
1252 0, 0);
1253 cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast,
1254 1 << priv->host_port, 0, 0, ALE_MCAST_FWD_2);
1255 }
1256 }
1257
cpsw_slave_stop(struct cpsw_slave * slave,struct cpsw_priv * priv)1258 static void cpsw_slave_stop(struct cpsw_slave *slave, struct cpsw_priv *priv)
1259 {
1260 u32 slave_port;
1261
1262 slave_port = cpsw_get_slave_port(priv, slave->slave_num);
1263
1264 if (!slave->phy)
1265 return;
1266 phy_stop(slave->phy);
1267 phy_disconnect(slave->phy);
1268 slave->phy = NULL;
1269 cpsw_ale_control_set(priv->ale, slave_port,
1270 ALE_PORT_STATE, ALE_PORT_STATE_DISABLE);
1271 }
1272
cpsw_ndo_open(struct net_device * ndev)1273 static int cpsw_ndo_open(struct net_device *ndev)
1274 {
1275 struct cpsw_priv *priv = netdev_priv(ndev);
1276 int i, ret;
1277 u32 reg;
1278
1279 if (!cpsw_common_res_usage_state(priv))
1280 cpsw_intr_disable(priv);
1281 netif_carrier_off(ndev);
1282
1283 pm_runtime_get_sync(&priv->pdev->dev);
1284
1285 reg = priv->version;
1286
1287 dev_info(priv->dev, "initializing cpsw version %d.%d (%d)\n",
1288 CPSW_MAJOR_VERSION(reg), CPSW_MINOR_VERSION(reg),
1289 CPSW_RTL_VERSION(reg));
1290
1291 /* initialize host and slave ports */
1292 if (!cpsw_common_res_usage_state(priv))
1293 cpsw_init_host_port(priv);
1294 for_each_slave(priv, cpsw_slave_open, priv);
1295
1296 /* Add default VLAN */
1297 if (!priv->data.dual_emac)
1298 cpsw_add_default_vlan(priv);
1299 else
1300 cpsw_ale_add_vlan(priv->ale, priv->data.default_vlan,
1301 ALE_ALL_PORTS << priv->host_port,
1302 ALE_ALL_PORTS << priv->host_port, 0, 0);
1303
1304 if (!cpsw_common_res_usage_state(priv)) {
1305 struct cpsw_priv *priv_sl0 = cpsw_get_slave_priv(priv, 0);
1306
1307 /* setup tx dma to fixed prio and zero offset */
1308 cpdma_control_set(priv->dma, CPDMA_TX_PRIO_FIXED, 1);
1309 cpdma_control_set(priv->dma, CPDMA_RX_BUFFER_OFFSET, 0);
1310
1311 /* disable priority elevation */
1312 __raw_writel(0, &priv->regs->ptype);
1313
1314 /* enable statistics collection only on all ports */
1315 __raw_writel(0x7, &priv->regs->stat_port_en);
1316
1317 /* Enable internal fifo flow control */
1318 writel(0x7, &priv->regs->flow_control);
1319
1320 napi_enable(&priv_sl0->napi_rx);
1321 napi_enable(&priv_sl0->napi_tx);
1322
1323 if (priv_sl0->tx_irq_disabled) {
1324 priv_sl0->tx_irq_disabled = false;
1325 enable_irq(priv->irqs_table[1]);
1326 }
1327
1328 if (priv_sl0->rx_irq_disabled) {
1329 priv_sl0->rx_irq_disabled = false;
1330 enable_irq(priv->irqs_table[0]);
1331 }
1332
1333 if (WARN_ON(!priv->data.rx_descs))
1334 priv->data.rx_descs = 128;
1335
1336 for (i = 0; i < priv->data.rx_descs; i++) {
1337 struct sk_buff *skb;
1338
1339 ret = -ENOMEM;
1340 skb = __netdev_alloc_skb_ip_align(priv->ndev,
1341 priv->rx_packet_max, GFP_KERNEL);
1342 if (!skb)
1343 goto err_cleanup;
1344 ret = cpdma_chan_submit(priv->rxch, skb, skb->data,
1345 skb_tailroom(skb), 0);
1346 if (ret < 0) {
1347 kfree_skb(skb);
1348 goto err_cleanup;
1349 }
1350 }
1351 /* continue even if we didn't manage to submit all
1352 * receive descs
1353 */
1354 cpsw_info(priv, ifup, "submitted %d rx descriptors\n", i);
1355
1356 if (cpts_register(&priv->pdev->dev, priv->cpts,
1357 priv->data.cpts_clock_mult,
1358 priv->data.cpts_clock_shift))
1359 dev_err(priv->dev, "error registering cpts device\n");
1360
1361 }
1362
1363 /* Enable Interrupt pacing if configured */
1364 if (priv->coal_intvl != 0) {
1365 struct ethtool_coalesce coal;
1366
1367 coal.rx_coalesce_usecs = (priv->coal_intvl << 4);
1368 cpsw_set_coalesce(ndev, &coal);
1369 }
1370
1371 cpdma_ctlr_start(priv->dma);
1372 cpsw_intr_enable(priv);
1373
1374 if (priv->data.dual_emac)
1375 priv->slaves[priv->emac_port].open_stat = true;
1376 return 0;
1377
1378 err_cleanup:
1379 cpdma_ctlr_stop(priv->dma);
1380 for_each_slave(priv, cpsw_slave_stop, priv);
1381 pm_runtime_put_sync(&priv->pdev->dev);
1382 netif_carrier_off(priv->ndev);
1383 return ret;
1384 }
1385
cpsw_ndo_stop(struct net_device * ndev)1386 static int cpsw_ndo_stop(struct net_device *ndev)
1387 {
1388 struct cpsw_priv *priv = netdev_priv(ndev);
1389
1390 cpsw_info(priv, ifdown, "shutting down cpsw device\n");
1391 netif_stop_queue(priv->ndev);
1392 netif_carrier_off(priv->ndev);
1393
1394 if (cpsw_common_res_usage_state(priv) <= 1) {
1395 struct cpsw_priv *priv_sl0 = cpsw_get_slave_priv(priv, 0);
1396
1397 napi_disable(&priv_sl0->napi_rx);
1398 napi_disable(&priv_sl0->napi_tx);
1399 cpts_unregister(priv->cpts);
1400 cpsw_intr_disable(priv);
1401 cpdma_ctlr_stop(priv->dma);
1402 cpsw_ale_stop(priv->ale);
1403 }
1404 for_each_slave(priv, cpsw_slave_stop, priv);
1405 pm_runtime_put_sync(&priv->pdev->dev);
1406 if (priv->data.dual_emac)
1407 priv->slaves[priv->emac_port].open_stat = false;
1408 return 0;
1409 }
1410
cpsw_ndo_start_xmit(struct sk_buff * skb,struct net_device * ndev)1411 static netdev_tx_t cpsw_ndo_start_xmit(struct sk_buff *skb,
1412 struct net_device *ndev)
1413 {
1414 struct cpsw_priv *priv = netdev_priv(ndev);
1415 int ret;
1416
1417 ndev->trans_start = jiffies;
1418
1419 if (skb_padto(skb, CPSW_MIN_PACKET_SIZE)) {
1420 cpsw_err(priv, tx_err, "packet pad failed\n");
1421 ndev->stats.tx_dropped++;
1422 return NETDEV_TX_OK;
1423 }
1424
1425 if (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP &&
1426 priv->cpts->tx_enable)
1427 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
1428
1429 skb_tx_timestamp(skb);
1430
1431 ret = cpsw_tx_packet_submit(ndev, priv, skb);
1432 if (unlikely(ret != 0)) {
1433 cpsw_err(priv, tx_err, "desc submit failed\n");
1434 goto fail;
1435 }
1436
1437 /* If there is no more tx desc left free then we need to
1438 * tell the kernel to stop sending us tx frames.
1439 */
1440 if (unlikely(!cpdma_check_free_tx_desc(priv->txch)))
1441 netif_stop_queue(ndev);
1442
1443 return NETDEV_TX_OK;
1444 fail:
1445 ndev->stats.tx_dropped++;
1446 netif_stop_queue(ndev);
1447 return NETDEV_TX_BUSY;
1448 }
1449
1450 #ifdef CONFIG_TI_CPTS
1451
cpsw_hwtstamp_v1(struct cpsw_priv * priv)1452 static void cpsw_hwtstamp_v1(struct cpsw_priv *priv)
1453 {
1454 struct cpsw_slave *slave = &priv->slaves[priv->data.active_slave];
1455 u32 ts_en, seq_id;
1456
1457 if (!priv->cpts->tx_enable && !priv->cpts->rx_enable) {
1458 slave_write(slave, 0, CPSW1_TS_CTL);
1459 return;
1460 }
1461
1462 seq_id = (30 << CPSW_V1_SEQ_ID_OFS_SHIFT) | ETH_P_1588;
1463 ts_en = EVENT_MSG_BITS << CPSW_V1_MSG_TYPE_OFS;
1464
1465 if (priv->cpts->tx_enable)
1466 ts_en |= CPSW_V1_TS_TX_EN;
1467
1468 if (priv->cpts->rx_enable)
1469 ts_en |= CPSW_V1_TS_RX_EN;
1470
1471 slave_write(slave, ts_en, CPSW1_TS_CTL);
1472 slave_write(slave, seq_id, CPSW1_TS_SEQ_LTYPE);
1473 }
1474
cpsw_hwtstamp_v2(struct cpsw_priv * priv)1475 static void cpsw_hwtstamp_v2(struct cpsw_priv *priv)
1476 {
1477 struct cpsw_slave *slave;
1478 u32 ctrl, mtype;
1479
1480 if (priv->data.dual_emac)
1481 slave = &priv->slaves[priv->emac_port];
1482 else
1483 slave = &priv->slaves[priv->data.active_slave];
1484
1485 ctrl = slave_read(slave, CPSW2_CONTROL);
1486 switch (priv->version) {
1487 case CPSW_VERSION_2:
1488 ctrl &= ~CTRL_V2_ALL_TS_MASK;
1489
1490 if (priv->cpts->tx_enable)
1491 ctrl |= CTRL_V2_TX_TS_BITS;
1492
1493 if (priv->cpts->rx_enable)
1494 ctrl |= CTRL_V2_RX_TS_BITS;
1495 break;
1496 case CPSW_VERSION_3:
1497 default:
1498 ctrl &= ~CTRL_V3_ALL_TS_MASK;
1499
1500 if (priv->cpts->tx_enable)
1501 ctrl |= CTRL_V3_TX_TS_BITS;
1502
1503 if (priv->cpts->rx_enable)
1504 ctrl |= CTRL_V3_RX_TS_BITS;
1505 break;
1506 }
1507
1508 mtype = (30 << TS_SEQ_ID_OFFSET_SHIFT) | EVENT_MSG_BITS;
1509
1510 slave_write(slave, mtype, CPSW2_TS_SEQ_MTYPE);
1511 slave_write(slave, ctrl, CPSW2_CONTROL);
1512 __raw_writel(ETH_P_1588, &priv->regs->ts_ltype);
1513 }
1514
cpsw_hwtstamp_set(struct net_device * dev,struct ifreq * ifr)1515 static int cpsw_hwtstamp_set(struct net_device *dev, struct ifreq *ifr)
1516 {
1517 struct cpsw_priv *priv = netdev_priv(dev);
1518 struct cpts *cpts = priv->cpts;
1519 struct hwtstamp_config cfg;
1520
1521 if (priv->version != CPSW_VERSION_1 &&
1522 priv->version != CPSW_VERSION_2 &&
1523 priv->version != CPSW_VERSION_3)
1524 return -EOPNOTSUPP;
1525
1526 if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg)))
1527 return -EFAULT;
1528
1529 /* reserved for future extensions */
1530 if (cfg.flags)
1531 return -EINVAL;
1532
1533 if (cfg.tx_type != HWTSTAMP_TX_OFF && cfg.tx_type != HWTSTAMP_TX_ON)
1534 return -ERANGE;
1535
1536 switch (cfg.rx_filter) {
1537 case HWTSTAMP_FILTER_NONE:
1538 cpts->rx_enable = 0;
1539 break;
1540 case HWTSTAMP_FILTER_ALL:
1541 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
1542 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
1543 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
1544 return -ERANGE;
1545 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
1546 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
1547 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
1548 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
1549 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
1550 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
1551 case HWTSTAMP_FILTER_PTP_V2_EVENT:
1552 case HWTSTAMP_FILTER_PTP_V2_SYNC:
1553 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
1554 cpts->rx_enable = 1;
1555 cfg.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
1556 break;
1557 default:
1558 return -ERANGE;
1559 }
1560
1561 cpts->tx_enable = cfg.tx_type == HWTSTAMP_TX_ON;
1562
1563 switch (priv->version) {
1564 case CPSW_VERSION_1:
1565 cpsw_hwtstamp_v1(priv);
1566 break;
1567 case CPSW_VERSION_2:
1568 case CPSW_VERSION_3:
1569 cpsw_hwtstamp_v2(priv);
1570 break;
1571 default:
1572 WARN_ON(1);
1573 }
1574
1575 return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0;
1576 }
1577
cpsw_hwtstamp_get(struct net_device * dev,struct ifreq * ifr)1578 static int cpsw_hwtstamp_get(struct net_device *dev, struct ifreq *ifr)
1579 {
1580 struct cpsw_priv *priv = netdev_priv(dev);
1581 struct cpts *cpts = priv->cpts;
1582 struct hwtstamp_config cfg;
1583
1584 if (priv->version != CPSW_VERSION_1 &&
1585 priv->version != CPSW_VERSION_2 &&
1586 priv->version != CPSW_VERSION_3)
1587 return -EOPNOTSUPP;
1588
1589 cfg.flags = 0;
1590 cfg.tx_type = cpts->tx_enable ? HWTSTAMP_TX_ON : HWTSTAMP_TX_OFF;
1591 cfg.rx_filter = (cpts->rx_enable ?
1592 HWTSTAMP_FILTER_PTP_V2_EVENT : HWTSTAMP_FILTER_NONE);
1593
1594 return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0;
1595 }
1596
1597 #endif /*CONFIG_TI_CPTS*/
1598
cpsw_ndo_ioctl(struct net_device * dev,struct ifreq * req,int cmd)1599 static int cpsw_ndo_ioctl(struct net_device *dev, struct ifreq *req, int cmd)
1600 {
1601 struct cpsw_priv *priv = netdev_priv(dev);
1602 int slave_no = cpsw_slave_index(priv);
1603
1604 if (!netif_running(dev))
1605 return -EINVAL;
1606
1607 switch (cmd) {
1608 #ifdef CONFIG_TI_CPTS
1609 case SIOCSHWTSTAMP:
1610 return cpsw_hwtstamp_set(dev, req);
1611 case SIOCGHWTSTAMP:
1612 return cpsw_hwtstamp_get(dev, req);
1613 #endif
1614 }
1615
1616 if (!priv->slaves[slave_no].phy)
1617 return -EOPNOTSUPP;
1618 return phy_mii_ioctl(priv->slaves[slave_no].phy, req, cmd);
1619 }
1620
cpsw_ndo_tx_timeout(struct net_device * ndev)1621 static void cpsw_ndo_tx_timeout(struct net_device *ndev)
1622 {
1623 struct cpsw_priv *priv = netdev_priv(ndev);
1624
1625 cpsw_err(priv, tx_err, "transmit timeout, restarting dma\n");
1626 ndev->stats.tx_errors++;
1627 cpsw_intr_disable(priv);
1628 cpdma_chan_stop(priv->txch);
1629 cpdma_chan_start(priv->txch);
1630 cpsw_intr_enable(priv);
1631 }
1632
cpsw_ndo_set_mac_address(struct net_device * ndev,void * p)1633 static int cpsw_ndo_set_mac_address(struct net_device *ndev, void *p)
1634 {
1635 struct cpsw_priv *priv = netdev_priv(ndev);
1636 struct sockaddr *addr = (struct sockaddr *)p;
1637 int flags = 0;
1638 u16 vid = 0;
1639
1640 if (!is_valid_ether_addr(addr->sa_data))
1641 return -EADDRNOTAVAIL;
1642
1643 if (priv->data.dual_emac) {
1644 vid = priv->slaves[priv->emac_port].port_vlan;
1645 flags = ALE_VLAN;
1646 }
1647
1648 cpsw_ale_del_ucast(priv->ale, priv->mac_addr, priv->host_port,
1649 flags, vid);
1650 cpsw_ale_add_ucast(priv->ale, addr->sa_data, priv->host_port,
1651 flags, vid);
1652
1653 memcpy(priv->mac_addr, addr->sa_data, ETH_ALEN);
1654 memcpy(ndev->dev_addr, priv->mac_addr, ETH_ALEN);
1655 for_each_slave(priv, cpsw_set_slave_mac, priv);
1656
1657 return 0;
1658 }
1659
1660 #ifdef CONFIG_NET_POLL_CONTROLLER
cpsw_ndo_poll_controller(struct net_device * ndev)1661 static void cpsw_ndo_poll_controller(struct net_device *ndev)
1662 {
1663 struct cpsw_priv *priv = netdev_priv(ndev);
1664
1665 cpsw_intr_disable(priv);
1666 cpsw_rx_interrupt(priv->irqs_table[0], priv);
1667 cpsw_tx_interrupt(priv->irqs_table[1], priv);
1668 cpsw_intr_enable(priv);
1669 }
1670 #endif
1671
cpsw_add_vlan_ale_entry(struct cpsw_priv * priv,unsigned short vid)1672 static inline int cpsw_add_vlan_ale_entry(struct cpsw_priv *priv,
1673 unsigned short vid)
1674 {
1675 int ret;
1676 int unreg_mcast_mask = 0;
1677 u32 port_mask;
1678
1679 if (priv->data.dual_emac) {
1680 port_mask = (1 << (priv->emac_port + 1)) | ALE_PORT_HOST;
1681
1682 if (priv->ndev->flags & IFF_ALLMULTI)
1683 unreg_mcast_mask = port_mask;
1684 } else {
1685 port_mask = ALE_ALL_PORTS;
1686
1687 if (priv->ndev->flags & IFF_ALLMULTI)
1688 unreg_mcast_mask = ALE_ALL_PORTS;
1689 else
1690 unreg_mcast_mask = ALE_PORT_1 | ALE_PORT_2;
1691 }
1692
1693 ret = cpsw_ale_add_vlan(priv->ale, vid, port_mask, 0, port_mask,
1694 unreg_mcast_mask << priv->host_port);
1695 if (ret != 0)
1696 return ret;
1697
1698 ret = cpsw_ale_add_ucast(priv->ale, priv->mac_addr,
1699 priv->host_port, ALE_VLAN, vid);
1700 if (ret != 0)
1701 goto clean_vid;
1702
1703 ret = cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast,
1704 port_mask, ALE_VLAN, vid, 0);
1705 if (ret != 0)
1706 goto clean_vlan_ucast;
1707 return 0;
1708
1709 clean_vlan_ucast:
1710 cpsw_ale_del_ucast(priv->ale, priv->mac_addr,
1711 priv->host_port, ALE_VLAN, vid);
1712 clean_vid:
1713 cpsw_ale_del_vlan(priv->ale, vid, 0);
1714 return ret;
1715 }
1716
cpsw_ndo_vlan_rx_add_vid(struct net_device * ndev,__be16 proto,u16 vid)1717 static int cpsw_ndo_vlan_rx_add_vid(struct net_device *ndev,
1718 __be16 proto, u16 vid)
1719 {
1720 struct cpsw_priv *priv = netdev_priv(ndev);
1721
1722 if (vid == priv->data.default_vlan)
1723 return 0;
1724
1725 if (priv->data.dual_emac) {
1726 /* In dual EMAC, reserved VLAN id should not be used for
1727 * creating VLAN interfaces as this can break the dual
1728 * EMAC port separation
1729 */
1730 int i;
1731
1732 for (i = 0; i < priv->data.slaves; i++) {
1733 if (vid == priv->slaves[i].port_vlan)
1734 return -EINVAL;
1735 }
1736 }
1737
1738 dev_info(priv->dev, "Adding vlanid %d to vlan filter\n", vid);
1739 return cpsw_add_vlan_ale_entry(priv, vid);
1740 }
1741
cpsw_ndo_vlan_rx_kill_vid(struct net_device * ndev,__be16 proto,u16 vid)1742 static int cpsw_ndo_vlan_rx_kill_vid(struct net_device *ndev,
1743 __be16 proto, u16 vid)
1744 {
1745 struct cpsw_priv *priv = netdev_priv(ndev);
1746 int ret;
1747
1748 if (vid == priv->data.default_vlan)
1749 return 0;
1750
1751 if (priv->data.dual_emac) {
1752 int i;
1753
1754 for (i = 0; i < priv->data.slaves; i++) {
1755 if (vid == priv->slaves[i].port_vlan)
1756 return -EINVAL;
1757 }
1758 }
1759
1760 dev_info(priv->dev, "removing vlanid %d from vlan filter\n", vid);
1761 ret = cpsw_ale_del_vlan(priv->ale, vid, 0);
1762 if (ret != 0)
1763 return ret;
1764
1765 ret = cpsw_ale_del_ucast(priv->ale, priv->mac_addr,
1766 priv->host_port, ALE_VLAN, vid);
1767 if (ret != 0)
1768 return ret;
1769
1770 return cpsw_ale_del_mcast(priv->ale, priv->ndev->broadcast,
1771 0, ALE_VLAN, vid);
1772 }
1773
1774 static const struct net_device_ops cpsw_netdev_ops = {
1775 .ndo_open = cpsw_ndo_open,
1776 .ndo_stop = cpsw_ndo_stop,
1777 .ndo_start_xmit = cpsw_ndo_start_xmit,
1778 .ndo_set_mac_address = cpsw_ndo_set_mac_address,
1779 .ndo_do_ioctl = cpsw_ndo_ioctl,
1780 .ndo_validate_addr = eth_validate_addr,
1781 .ndo_change_mtu = eth_change_mtu,
1782 .ndo_tx_timeout = cpsw_ndo_tx_timeout,
1783 .ndo_set_rx_mode = cpsw_ndo_set_rx_mode,
1784 #ifdef CONFIG_NET_POLL_CONTROLLER
1785 .ndo_poll_controller = cpsw_ndo_poll_controller,
1786 #endif
1787 .ndo_vlan_rx_add_vid = cpsw_ndo_vlan_rx_add_vid,
1788 .ndo_vlan_rx_kill_vid = cpsw_ndo_vlan_rx_kill_vid,
1789 };
1790
cpsw_get_regs_len(struct net_device * ndev)1791 static int cpsw_get_regs_len(struct net_device *ndev)
1792 {
1793 struct cpsw_priv *priv = netdev_priv(ndev);
1794
1795 return priv->data.ale_entries * ALE_ENTRY_WORDS * sizeof(u32);
1796 }
1797
cpsw_get_regs(struct net_device * ndev,struct ethtool_regs * regs,void * p)1798 static void cpsw_get_regs(struct net_device *ndev,
1799 struct ethtool_regs *regs, void *p)
1800 {
1801 struct cpsw_priv *priv = netdev_priv(ndev);
1802 u32 *reg = p;
1803
1804 /* update CPSW IP version */
1805 regs->version = priv->version;
1806
1807 cpsw_ale_dump(priv->ale, reg);
1808 }
1809
cpsw_get_drvinfo(struct net_device * ndev,struct ethtool_drvinfo * info)1810 static void cpsw_get_drvinfo(struct net_device *ndev,
1811 struct ethtool_drvinfo *info)
1812 {
1813 struct cpsw_priv *priv = netdev_priv(ndev);
1814
1815 strlcpy(info->driver, "cpsw", sizeof(info->driver));
1816 strlcpy(info->version, "1.0", sizeof(info->version));
1817 strlcpy(info->bus_info, priv->pdev->name, sizeof(info->bus_info));
1818 }
1819
cpsw_get_msglevel(struct net_device * ndev)1820 static u32 cpsw_get_msglevel(struct net_device *ndev)
1821 {
1822 struct cpsw_priv *priv = netdev_priv(ndev);
1823 return priv->msg_enable;
1824 }
1825
cpsw_set_msglevel(struct net_device * ndev,u32 value)1826 static void cpsw_set_msglevel(struct net_device *ndev, u32 value)
1827 {
1828 struct cpsw_priv *priv = netdev_priv(ndev);
1829 priv->msg_enable = value;
1830 }
1831
cpsw_get_ts_info(struct net_device * ndev,struct ethtool_ts_info * info)1832 static int cpsw_get_ts_info(struct net_device *ndev,
1833 struct ethtool_ts_info *info)
1834 {
1835 #ifdef CONFIG_TI_CPTS
1836 struct cpsw_priv *priv = netdev_priv(ndev);
1837
1838 info->so_timestamping =
1839 SOF_TIMESTAMPING_TX_HARDWARE |
1840 SOF_TIMESTAMPING_TX_SOFTWARE |
1841 SOF_TIMESTAMPING_RX_HARDWARE |
1842 SOF_TIMESTAMPING_RX_SOFTWARE |
1843 SOF_TIMESTAMPING_SOFTWARE |
1844 SOF_TIMESTAMPING_RAW_HARDWARE;
1845 info->phc_index = priv->cpts->phc_index;
1846 info->tx_types =
1847 (1 << HWTSTAMP_TX_OFF) |
1848 (1 << HWTSTAMP_TX_ON);
1849 info->rx_filters =
1850 (1 << HWTSTAMP_FILTER_NONE) |
1851 (1 << HWTSTAMP_FILTER_PTP_V2_EVENT);
1852 #else
1853 info->so_timestamping =
1854 SOF_TIMESTAMPING_TX_SOFTWARE |
1855 SOF_TIMESTAMPING_RX_SOFTWARE |
1856 SOF_TIMESTAMPING_SOFTWARE;
1857 info->phc_index = -1;
1858 info->tx_types = 0;
1859 info->rx_filters = 0;
1860 #endif
1861 return 0;
1862 }
1863
cpsw_get_settings(struct net_device * ndev,struct ethtool_cmd * ecmd)1864 static int cpsw_get_settings(struct net_device *ndev,
1865 struct ethtool_cmd *ecmd)
1866 {
1867 struct cpsw_priv *priv = netdev_priv(ndev);
1868 int slave_no = cpsw_slave_index(priv);
1869
1870 if (priv->slaves[slave_no].phy)
1871 return phy_ethtool_gset(priv->slaves[slave_no].phy, ecmd);
1872 else
1873 return -EOPNOTSUPP;
1874 }
1875
cpsw_set_settings(struct net_device * ndev,struct ethtool_cmd * ecmd)1876 static int cpsw_set_settings(struct net_device *ndev, struct ethtool_cmd *ecmd)
1877 {
1878 struct cpsw_priv *priv = netdev_priv(ndev);
1879 int slave_no = cpsw_slave_index(priv);
1880
1881 if (priv->slaves[slave_no].phy)
1882 return phy_ethtool_sset(priv->slaves[slave_no].phy, ecmd);
1883 else
1884 return -EOPNOTSUPP;
1885 }
1886
cpsw_get_wol(struct net_device * ndev,struct ethtool_wolinfo * wol)1887 static void cpsw_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
1888 {
1889 struct cpsw_priv *priv = netdev_priv(ndev);
1890 int slave_no = cpsw_slave_index(priv);
1891
1892 wol->supported = 0;
1893 wol->wolopts = 0;
1894
1895 if (priv->slaves[slave_no].phy)
1896 phy_ethtool_get_wol(priv->slaves[slave_no].phy, wol);
1897 }
1898
cpsw_set_wol(struct net_device * ndev,struct ethtool_wolinfo * wol)1899 static int cpsw_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
1900 {
1901 struct cpsw_priv *priv = netdev_priv(ndev);
1902 int slave_no = cpsw_slave_index(priv);
1903
1904 if (priv->slaves[slave_no].phy)
1905 return phy_ethtool_set_wol(priv->slaves[slave_no].phy, wol);
1906 else
1907 return -EOPNOTSUPP;
1908 }
1909
cpsw_get_pauseparam(struct net_device * ndev,struct ethtool_pauseparam * pause)1910 static void cpsw_get_pauseparam(struct net_device *ndev,
1911 struct ethtool_pauseparam *pause)
1912 {
1913 struct cpsw_priv *priv = netdev_priv(ndev);
1914
1915 pause->autoneg = AUTONEG_DISABLE;
1916 pause->rx_pause = priv->rx_pause ? true : false;
1917 pause->tx_pause = priv->tx_pause ? true : false;
1918 }
1919
cpsw_set_pauseparam(struct net_device * ndev,struct ethtool_pauseparam * pause)1920 static int cpsw_set_pauseparam(struct net_device *ndev,
1921 struct ethtool_pauseparam *pause)
1922 {
1923 struct cpsw_priv *priv = netdev_priv(ndev);
1924 bool link;
1925
1926 priv->rx_pause = pause->rx_pause ? true : false;
1927 priv->tx_pause = pause->tx_pause ? true : false;
1928
1929 for_each_slave(priv, _cpsw_adjust_link, priv, &link);
1930
1931 return 0;
1932 }
1933
1934 static const struct ethtool_ops cpsw_ethtool_ops = {
1935 .get_drvinfo = cpsw_get_drvinfo,
1936 .get_msglevel = cpsw_get_msglevel,
1937 .set_msglevel = cpsw_set_msglevel,
1938 .get_link = ethtool_op_get_link,
1939 .get_ts_info = cpsw_get_ts_info,
1940 .get_settings = cpsw_get_settings,
1941 .set_settings = cpsw_set_settings,
1942 .get_coalesce = cpsw_get_coalesce,
1943 .set_coalesce = cpsw_set_coalesce,
1944 .get_sset_count = cpsw_get_sset_count,
1945 .get_strings = cpsw_get_strings,
1946 .get_ethtool_stats = cpsw_get_ethtool_stats,
1947 .get_pauseparam = cpsw_get_pauseparam,
1948 .set_pauseparam = cpsw_set_pauseparam,
1949 .get_wol = cpsw_get_wol,
1950 .set_wol = cpsw_set_wol,
1951 .get_regs_len = cpsw_get_regs_len,
1952 .get_regs = cpsw_get_regs,
1953 };
1954
cpsw_slave_init(struct cpsw_slave * slave,struct cpsw_priv * priv,u32 slave_reg_ofs,u32 sliver_reg_ofs)1955 static void cpsw_slave_init(struct cpsw_slave *slave, struct cpsw_priv *priv,
1956 u32 slave_reg_ofs, u32 sliver_reg_ofs)
1957 {
1958 void __iomem *regs = priv->regs;
1959 int slave_num = slave->slave_num;
1960 struct cpsw_slave_data *data = priv->data.slave_data + slave_num;
1961
1962 slave->data = data;
1963 slave->regs = regs + slave_reg_ofs;
1964 slave->sliver = regs + sliver_reg_ofs;
1965 slave->port_vlan = data->dual_emac_res_vlan;
1966 }
1967
cpsw_probe_dt(struct cpsw_platform_data * data,struct platform_device * pdev)1968 static int cpsw_probe_dt(struct cpsw_platform_data *data,
1969 struct platform_device *pdev)
1970 {
1971 struct device_node *node = pdev->dev.of_node;
1972 struct device_node *slave_node;
1973 int i = 0, ret;
1974 u32 prop;
1975
1976 if (!node)
1977 return -EINVAL;
1978
1979 if (of_property_read_u32(node, "slaves", &prop)) {
1980 dev_err(&pdev->dev, "Missing slaves property in the DT.\n");
1981 return -EINVAL;
1982 }
1983 data->slaves = prop;
1984
1985 if (of_property_read_u32(node, "active_slave", &prop)) {
1986 dev_err(&pdev->dev, "Missing active_slave property in the DT.\n");
1987 return -EINVAL;
1988 }
1989 data->active_slave = prop;
1990
1991 if (of_property_read_u32(node, "cpts_clock_mult", &prop)) {
1992 dev_err(&pdev->dev, "Missing cpts_clock_mult property in the DT.\n");
1993 return -EINVAL;
1994 }
1995 data->cpts_clock_mult = prop;
1996
1997 if (of_property_read_u32(node, "cpts_clock_shift", &prop)) {
1998 dev_err(&pdev->dev, "Missing cpts_clock_shift property in the DT.\n");
1999 return -EINVAL;
2000 }
2001 data->cpts_clock_shift = prop;
2002
2003 data->slave_data = devm_kzalloc(&pdev->dev, data->slaves
2004 * sizeof(struct cpsw_slave_data),
2005 GFP_KERNEL);
2006 if (!data->slave_data)
2007 return -ENOMEM;
2008
2009 if (of_property_read_u32(node, "cpdma_channels", &prop)) {
2010 dev_err(&pdev->dev, "Missing cpdma_channels property in the DT.\n");
2011 return -EINVAL;
2012 }
2013 data->channels = prop;
2014
2015 if (of_property_read_u32(node, "ale_entries", &prop)) {
2016 dev_err(&pdev->dev, "Missing ale_entries property in the DT.\n");
2017 return -EINVAL;
2018 }
2019 data->ale_entries = prop;
2020
2021 if (of_property_read_u32(node, "bd_ram_size", &prop)) {
2022 dev_err(&pdev->dev, "Missing bd_ram_size property in the DT.\n");
2023 return -EINVAL;
2024 }
2025 data->bd_ram_size = prop;
2026
2027 if (of_property_read_u32(node, "rx_descs", &prop)) {
2028 dev_err(&pdev->dev, "Missing rx_descs property in the DT.\n");
2029 return -EINVAL;
2030 }
2031 data->rx_descs = prop;
2032
2033 if (of_property_read_u32(node, "mac_control", &prop)) {
2034 dev_err(&pdev->dev, "Missing mac_control property in the DT.\n");
2035 return -EINVAL;
2036 }
2037 data->mac_control = prop;
2038
2039 if (of_property_read_bool(node, "dual_emac"))
2040 data->dual_emac = 1;
2041
2042 /*
2043 * Populate all the child nodes here...
2044 */
2045 ret = of_platform_populate(node, NULL, NULL, &pdev->dev);
2046 /* We do not want to force this, as in some cases may not have child */
2047 if (ret)
2048 dev_warn(&pdev->dev, "Doesn't have any child node\n");
2049
2050 for_each_child_of_node(node, slave_node) {
2051 struct cpsw_slave_data *slave_data = data->slave_data + i;
2052 const void *mac_addr = NULL;
2053 int lenp;
2054 const __be32 *parp;
2055
2056 /* This is no slave child node, continue */
2057 if (strcmp(slave_node->name, "slave"))
2058 continue;
2059
2060 slave_data->phy_node = of_parse_phandle(slave_node,
2061 "phy-handle", 0);
2062 parp = of_get_property(slave_node, "phy_id", &lenp);
2063 if (slave_data->phy_node) {
2064 dev_dbg(&pdev->dev,
2065 "slave[%d] using phy-handle=\"%s\"\n",
2066 i, slave_data->phy_node->full_name);
2067 } else if (of_phy_is_fixed_link(slave_node)) {
2068 struct device_node *phy_node;
2069 struct phy_device *phy_dev;
2070
2071 /* In the case of a fixed PHY, the DT node associated
2072 * to the PHY is the Ethernet MAC DT node.
2073 */
2074 ret = of_phy_register_fixed_link(slave_node);
2075 if (ret)
2076 return ret;
2077 phy_node = of_node_get(slave_node);
2078 phy_dev = of_phy_find_device(phy_node);
2079 if (!phy_dev)
2080 return -ENODEV;
2081 snprintf(slave_data->phy_id, sizeof(slave_data->phy_id),
2082 PHY_ID_FMT, phy_dev->bus->id, phy_dev->addr);
2083 } else if (parp) {
2084 u32 phyid;
2085 struct device_node *mdio_node;
2086 struct platform_device *mdio;
2087
2088 if (lenp != (sizeof(__be32) * 2)) {
2089 dev_err(&pdev->dev, "Invalid slave[%d] phy_id property\n", i);
2090 goto no_phy_slave;
2091 }
2092 mdio_node = of_find_node_by_phandle(be32_to_cpup(parp));
2093 phyid = be32_to_cpup(parp+1);
2094 mdio = of_find_device_by_node(mdio_node);
2095 of_node_put(mdio_node);
2096 if (!mdio) {
2097 dev_err(&pdev->dev, "Missing mdio platform device\n");
2098 return -EINVAL;
2099 }
2100 snprintf(slave_data->phy_id, sizeof(slave_data->phy_id),
2101 PHY_ID_FMT, mdio->name, phyid);
2102 put_device(&mdio->dev);
2103 } else {
2104 dev_err(&pdev->dev,
2105 "No slave[%d] phy_id, phy-handle, or fixed-link property\n",
2106 i);
2107 goto no_phy_slave;
2108 }
2109 slave_data->phy_if = of_get_phy_mode(slave_node);
2110 if (slave_data->phy_if < 0) {
2111 dev_err(&pdev->dev, "Missing or malformed slave[%d] phy-mode property\n",
2112 i);
2113 return slave_data->phy_if;
2114 }
2115
2116 no_phy_slave:
2117 mac_addr = of_get_mac_address(slave_node);
2118 if (mac_addr) {
2119 memcpy(slave_data->mac_addr, mac_addr, ETH_ALEN);
2120 } else {
2121 ret = ti_cm_get_macid(&pdev->dev, i,
2122 slave_data->mac_addr);
2123 if (ret)
2124 return ret;
2125 }
2126 if (data->dual_emac) {
2127 if (of_property_read_u32(slave_node, "dual_emac_res_vlan",
2128 &prop)) {
2129 dev_err(&pdev->dev, "Missing dual_emac_res_vlan in DT.\n");
2130 slave_data->dual_emac_res_vlan = i+1;
2131 dev_err(&pdev->dev, "Using %d as Reserved VLAN for %d slave\n",
2132 slave_data->dual_emac_res_vlan, i);
2133 } else {
2134 slave_data->dual_emac_res_vlan = prop;
2135 }
2136 }
2137
2138 i++;
2139 if (i == data->slaves)
2140 break;
2141 }
2142
2143 return 0;
2144 }
2145
cpsw_probe_dual_emac(struct platform_device * pdev,struct cpsw_priv * priv)2146 static int cpsw_probe_dual_emac(struct platform_device *pdev,
2147 struct cpsw_priv *priv)
2148 {
2149 struct cpsw_platform_data *data = &priv->data;
2150 struct net_device *ndev;
2151 struct cpsw_priv *priv_sl2;
2152 int ret = 0, i;
2153
2154 ndev = alloc_etherdev(sizeof(struct cpsw_priv));
2155 if (!ndev) {
2156 dev_err(&pdev->dev, "cpsw: error allocating net_device\n");
2157 return -ENOMEM;
2158 }
2159
2160 priv_sl2 = netdev_priv(ndev);
2161 spin_lock_init(&priv_sl2->lock);
2162 priv_sl2->data = *data;
2163 priv_sl2->pdev = pdev;
2164 priv_sl2->ndev = ndev;
2165 priv_sl2->dev = &ndev->dev;
2166 priv_sl2->msg_enable = netif_msg_init(debug_level, CPSW_DEBUG);
2167 priv_sl2->rx_packet_max = max(rx_packet_max, 128);
2168
2169 if (is_valid_ether_addr(data->slave_data[1].mac_addr)) {
2170 memcpy(priv_sl2->mac_addr, data->slave_data[1].mac_addr,
2171 ETH_ALEN);
2172 dev_info(&pdev->dev, "cpsw: Detected MACID = %pM\n", priv_sl2->mac_addr);
2173 } else {
2174 random_ether_addr(priv_sl2->mac_addr);
2175 dev_info(&pdev->dev, "cpsw: Random MACID = %pM\n", priv_sl2->mac_addr);
2176 }
2177 memcpy(ndev->dev_addr, priv_sl2->mac_addr, ETH_ALEN);
2178
2179 priv_sl2->slaves = priv->slaves;
2180 priv_sl2->clk = priv->clk;
2181
2182 priv_sl2->coal_intvl = 0;
2183 priv_sl2->bus_freq_mhz = priv->bus_freq_mhz;
2184
2185 priv_sl2->regs = priv->regs;
2186 priv_sl2->host_port = priv->host_port;
2187 priv_sl2->host_port_regs = priv->host_port_regs;
2188 priv_sl2->wr_regs = priv->wr_regs;
2189 priv_sl2->hw_stats = priv->hw_stats;
2190 priv_sl2->dma = priv->dma;
2191 priv_sl2->txch = priv->txch;
2192 priv_sl2->rxch = priv->rxch;
2193 priv_sl2->ale = priv->ale;
2194 priv_sl2->emac_port = 1;
2195 priv->slaves[1].ndev = ndev;
2196 priv_sl2->cpts = priv->cpts;
2197 priv_sl2->version = priv->version;
2198
2199 for (i = 0; i < priv->num_irqs; i++) {
2200 priv_sl2->irqs_table[i] = priv->irqs_table[i];
2201 priv_sl2->num_irqs = priv->num_irqs;
2202 }
2203 ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
2204
2205 ndev->netdev_ops = &cpsw_netdev_ops;
2206 ndev->ethtool_ops = &cpsw_ethtool_ops;
2207
2208 /* register the network device */
2209 SET_NETDEV_DEV(ndev, &pdev->dev);
2210 ret = register_netdev(ndev);
2211 if (ret) {
2212 dev_err(&pdev->dev, "cpsw: error registering net device\n");
2213 free_netdev(ndev);
2214 ret = -ENODEV;
2215 }
2216
2217 return ret;
2218 }
2219
2220 #define CPSW_QUIRK_IRQ BIT(0)
2221
2222 static struct platform_device_id cpsw_devtype[] = {
2223 {
2224 /* keep it for existing comaptibles */
2225 .name = "cpsw",
2226 .driver_data = CPSW_QUIRK_IRQ,
2227 }, {
2228 .name = "am335x-cpsw",
2229 .driver_data = CPSW_QUIRK_IRQ,
2230 }, {
2231 .name = "am4372-cpsw",
2232 .driver_data = 0,
2233 }, {
2234 .name = "dra7-cpsw",
2235 .driver_data = 0,
2236 }, {
2237 /* sentinel */
2238 }
2239 };
2240 MODULE_DEVICE_TABLE(platform, cpsw_devtype);
2241
2242 enum ti_cpsw_type {
2243 CPSW = 0,
2244 AM335X_CPSW,
2245 AM4372_CPSW,
2246 DRA7_CPSW,
2247 };
2248
2249 static const struct of_device_id cpsw_of_mtable[] = {
2250 { .compatible = "ti,cpsw", .data = &cpsw_devtype[CPSW], },
2251 { .compatible = "ti,am335x-cpsw", .data = &cpsw_devtype[AM335X_CPSW], },
2252 { .compatible = "ti,am4372-cpsw", .data = &cpsw_devtype[AM4372_CPSW], },
2253 { .compatible = "ti,dra7-cpsw", .data = &cpsw_devtype[DRA7_CPSW], },
2254 { /* sentinel */ },
2255 };
2256 MODULE_DEVICE_TABLE(of, cpsw_of_mtable);
2257
cpsw_probe(struct platform_device * pdev)2258 static int cpsw_probe(struct platform_device *pdev)
2259 {
2260 struct cpsw_platform_data *data;
2261 struct net_device *ndev;
2262 struct cpsw_priv *priv;
2263 struct cpdma_params dma_params;
2264 struct cpsw_ale_params ale_params;
2265 void __iomem *ss_regs;
2266 struct resource *res, *ss_res;
2267 const struct of_device_id *of_id;
2268 struct gpio_descs *mode;
2269 u32 slave_offset, sliver_offset, slave_size;
2270 int ret = 0, i;
2271 int irq;
2272
2273 ndev = alloc_etherdev(sizeof(struct cpsw_priv));
2274 if (!ndev) {
2275 dev_err(&pdev->dev, "error allocating net_device\n");
2276 return -ENOMEM;
2277 }
2278
2279 platform_set_drvdata(pdev, ndev);
2280 priv = netdev_priv(ndev);
2281 spin_lock_init(&priv->lock);
2282 priv->pdev = pdev;
2283 priv->ndev = ndev;
2284 priv->dev = &ndev->dev;
2285 priv->msg_enable = netif_msg_init(debug_level, CPSW_DEBUG);
2286 priv->rx_packet_max = max(rx_packet_max, 128);
2287 priv->cpts = devm_kzalloc(&pdev->dev, sizeof(struct cpts), GFP_KERNEL);
2288 if (!priv->cpts) {
2289 dev_err(&pdev->dev, "error allocating cpts\n");
2290 ret = -ENOMEM;
2291 goto clean_ndev_ret;
2292 }
2293
2294 mode = devm_gpiod_get_array_optional(&pdev->dev, "mode", GPIOD_OUT_LOW);
2295 if (IS_ERR(mode)) {
2296 ret = PTR_ERR(mode);
2297 dev_err(&pdev->dev, "gpio request failed, ret %d\n", ret);
2298 goto clean_ndev_ret;
2299 }
2300
2301 /*
2302 * This may be required here for child devices.
2303 */
2304 pm_runtime_enable(&pdev->dev);
2305
2306 /* Select default pin state */
2307 pinctrl_pm_select_default_state(&pdev->dev);
2308
2309 if (cpsw_probe_dt(&priv->data, pdev)) {
2310 dev_err(&pdev->dev, "cpsw: platform data missing\n");
2311 ret = -ENODEV;
2312 goto clean_runtime_disable_ret;
2313 }
2314 data = &priv->data;
2315
2316 if (is_valid_ether_addr(data->slave_data[0].mac_addr)) {
2317 memcpy(priv->mac_addr, data->slave_data[0].mac_addr, ETH_ALEN);
2318 dev_info(&pdev->dev, "Detected MACID = %pM\n", priv->mac_addr);
2319 } else {
2320 eth_random_addr(priv->mac_addr);
2321 dev_info(&pdev->dev, "Random MACID = %pM\n", priv->mac_addr);
2322 }
2323
2324 memcpy(ndev->dev_addr, priv->mac_addr, ETH_ALEN);
2325
2326 priv->slaves = devm_kzalloc(&pdev->dev,
2327 sizeof(struct cpsw_slave) * data->slaves,
2328 GFP_KERNEL);
2329 if (!priv->slaves) {
2330 ret = -ENOMEM;
2331 goto clean_runtime_disable_ret;
2332 }
2333 for (i = 0; i < data->slaves; i++)
2334 priv->slaves[i].slave_num = i;
2335
2336 priv->slaves[0].ndev = ndev;
2337 priv->emac_port = 0;
2338
2339 priv->clk = devm_clk_get(&pdev->dev, "fck");
2340 if (IS_ERR(priv->clk)) {
2341 dev_err(priv->dev, "fck is not found\n");
2342 ret = -ENODEV;
2343 goto clean_runtime_disable_ret;
2344 }
2345 priv->coal_intvl = 0;
2346 priv->bus_freq_mhz = clk_get_rate(priv->clk) / 1000000;
2347
2348 ss_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2349 ss_regs = devm_ioremap_resource(&pdev->dev, ss_res);
2350 if (IS_ERR(ss_regs)) {
2351 ret = PTR_ERR(ss_regs);
2352 goto clean_runtime_disable_ret;
2353 }
2354 priv->regs = ss_regs;
2355 priv->host_port = HOST_PORT_NUM;
2356
2357 /* Need to enable clocks with runtime PM api to access module
2358 * registers
2359 */
2360 pm_runtime_get_sync(&pdev->dev);
2361 priv->version = readl(&priv->regs->id_ver);
2362 pm_runtime_put_sync(&pdev->dev);
2363
2364 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
2365 priv->wr_regs = devm_ioremap_resource(&pdev->dev, res);
2366 if (IS_ERR(priv->wr_regs)) {
2367 ret = PTR_ERR(priv->wr_regs);
2368 goto clean_runtime_disable_ret;
2369 }
2370
2371 memset(&dma_params, 0, sizeof(dma_params));
2372 memset(&ale_params, 0, sizeof(ale_params));
2373
2374 switch (priv->version) {
2375 case CPSW_VERSION_1:
2376 priv->host_port_regs = ss_regs + CPSW1_HOST_PORT_OFFSET;
2377 priv->cpts->reg = ss_regs + CPSW1_CPTS_OFFSET;
2378 priv->hw_stats = ss_regs + CPSW1_HW_STATS;
2379 dma_params.dmaregs = ss_regs + CPSW1_CPDMA_OFFSET;
2380 dma_params.txhdp = ss_regs + CPSW1_STATERAM_OFFSET;
2381 ale_params.ale_regs = ss_regs + CPSW1_ALE_OFFSET;
2382 slave_offset = CPSW1_SLAVE_OFFSET;
2383 slave_size = CPSW1_SLAVE_SIZE;
2384 sliver_offset = CPSW1_SLIVER_OFFSET;
2385 dma_params.desc_mem_phys = 0;
2386 break;
2387 case CPSW_VERSION_2:
2388 case CPSW_VERSION_3:
2389 case CPSW_VERSION_4:
2390 priv->host_port_regs = ss_regs + CPSW2_HOST_PORT_OFFSET;
2391 priv->cpts->reg = ss_regs + CPSW2_CPTS_OFFSET;
2392 priv->hw_stats = ss_regs + CPSW2_HW_STATS;
2393 dma_params.dmaregs = ss_regs + CPSW2_CPDMA_OFFSET;
2394 dma_params.txhdp = ss_regs + CPSW2_STATERAM_OFFSET;
2395 ale_params.ale_regs = ss_regs + CPSW2_ALE_OFFSET;
2396 slave_offset = CPSW2_SLAVE_OFFSET;
2397 slave_size = CPSW2_SLAVE_SIZE;
2398 sliver_offset = CPSW2_SLIVER_OFFSET;
2399 dma_params.desc_mem_phys =
2400 (u32 __force) ss_res->start + CPSW2_BD_OFFSET;
2401 break;
2402 default:
2403 dev_err(priv->dev, "unknown version 0x%08x\n", priv->version);
2404 ret = -ENODEV;
2405 goto clean_runtime_disable_ret;
2406 }
2407 for (i = 0; i < priv->data.slaves; i++) {
2408 struct cpsw_slave *slave = &priv->slaves[i];
2409 cpsw_slave_init(slave, priv, slave_offset, sliver_offset);
2410 slave_offset += slave_size;
2411 sliver_offset += SLIVER_SIZE;
2412 }
2413
2414 dma_params.dev = &pdev->dev;
2415 dma_params.rxthresh = dma_params.dmaregs + CPDMA_RXTHRESH;
2416 dma_params.rxfree = dma_params.dmaregs + CPDMA_RXFREE;
2417 dma_params.rxhdp = dma_params.txhdp + CPDMA_RXHDP;
2418 dma_params.txcp = dma_params.txhdp + CPDMA_TXCP;
2419 dma_params.rxcp = dma_params.txhdp + CPDMA_RXCP;
2420
2421 dma_params.num_chan = data->channels;
2422 dma_params.has_soft_reset = true;
2423 dma_params.min_packet_size = CPSW_MIN_PACKET_SIZE;
2424 dma_params.desc_mem_size = data->bd_ram_size;
2425 dma_params.desc_align = 16;
2426 dma_params.has_ext_regs = true;
2427 dma_params.desc_hw_addr = dma_params.desc_mem_phys;
2428
2429 priv->dma = cpdma_ctlr_create(&dma_params);
2430 if (!priv->dma) {
2431 dev_err(priv->dev, "error initializing dma\n");
2432 ret = -ENOMEM;
2433 goto clean_runtime_disable_ret;
2434 }
2435
2436 priv->txch = cpdma_chan_create(priv->dma, tx_chan_num(0),
2437 cpsw_tx_handler);
2438 priv->rxch = cpdma_chan_create(priv->dma, rx_chan_num(0),
2439 cpsw_rx_handler);
2440
2441 if (WARN_ON(!priv->txch || !priv->rxch)) {
2442 dev_err(priv->dev, "error initializing dma channels\n");
2443 ret = -ENOMEM;
2444 goto clean_dma_ret;
2445 }
2446
2447 ale_params.dev = &ndev->dev;
2448 ale_params.ale_ageout = ale_ageout;
2449 ale_params.ale_entries = data->ale_entries;
2450 ale_params.ale_ports = data->slaves;
2451
2452 priv->ale = cpsw_ale_create(&ale_params);
2453 if (!priv->ale) {
2454 dev_err(priv->dev, "error initializing ale engine\n");
2455 ret = -ENODEV;
2456 goto clean_dma_ret;
2457 }
2458
2459 ndev->irq = platform_get_irq(pdev, 1);
2460 if (ndev->irq < 0) {
2461 dev_err(priv->dev, "error getting irq resource\n");
2462 ret = ndev->irq;
2463 goto clean_ale_ret;
2464 }
2465
2466 of_id = of_match_device(cpsw_of_mtable, &pdev->dev);
2467 if (of_id) {
2468 pdev->id_entry = of_id->data;
2469 if (pdev->id_entry->driver_data)
2470 priv->quirk_irq = true;
2471 }
2472
2473 /* Grab RX and TX IRQs. Note that we also have RX_THRESHOLD and
2474 * MISC IRQs which are always kept disabled with this driver so
2475 * we will not request them.
2476 *
2477 * If anyone wants to implement support for those, make sure to
2478 * first request and append them to irqs_table array.
2479 */
2480
2481 /* RX IRQ */
2482 irq = platform_get_irq(pdev, 1);
2483 if (irq < 0) {
2484 ret = irq;
2485 goto clean_ale_ret;
2486 }
2487
2488 priv->irqs_table[0] = irq;
2489 ret = devm_request_irq(&pdev->dev, irq, cpsw_rx_interrupt,
2490 0, dev_name(&pdev->dev), priv);
2491 if (ret < 0) {
2492 dev_err(priv->dev, "error attaching irq (%d)\n", ret);
2493 goto clean_ale_ret;
2494 }
2495
2496 /* TX IRQ */
2497 irq = platform_get_irq(pdev, 2);
2498 if (irq < 0) {
2499 ret = irq;
2500 goto clean_ale_ret;
2501 }
2502
2503 priv->irqs_table[1] = irq;
2504 ret = devm_request_irq(&pdev->dev, irq, cpsw_tx_interrupt,
2505 0, dev_name(&pdev->dev), priv);
2506 if (ret < 0) {
2507 dev_err(priv->dev, "error attaching irq (%d)\n", ret);
2508 goto clean_ale_ret;
2509 }
2510 priv->num_irqs = 2;
2511
2512 ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
2513
2514 ndev->netdev_ops = &cpsw_netdev_ops;
2515 ndev->ethtool_ops = &cpsw_ethtool_ops;
2516 netif_napi_add(ndev, &priv->napi_rx, cpsw_rx_poll, CPSW_POLL_WEIGHT);
2517 netif_napi_add(ndev, &priv->napi_tx, cpsw_tx_poll, CPSW_POLL_WEIGHT);
2518
2519 /* register the network device */
2520 SET_NETDEV_DEV(ndev, &pdev->dev);
2521 ret = register_netdev(ndev);
2522 if (ret) {
2523 dev_err(priv->dev, "error registering net device\n");
2524 ret = -ENODEV;
2525 goto clean_ale_ret;
2526 }
2527
2528 cpsw_notice(priv, probe, "initialized device (regs %pa, irq %d)\n",
2529 &ss_res->start, ndev->irq);
2530
2531 if (priv->data.dual_emac) {
2532 ret = cpsw_probe_dual_emac(pdev, priv);
2533 if (ret) {
2534 cpsw_err(priv, probe, "error probe slave 2 emac interface\n");
2535 goto clean_unregister_netdev_ret;
2536 }
2537 }
2538
2539 return 0;
2540
2541 clean_unregister_netdev_ret:
2542 unregister_netdev(ndev);
2543 clean_ale_ret:
2544 cpsw_ale_destroy(priv->ale);
2545 clean_dma_ret:
2546 cpdma_chan_destroy(priv->txch);
2547 cpdma_chan_destroy(priv->rxch);
2548 cpdma_ctlr_destroy(priv->dma);
2549 clean_runtime_disable_ret:
2550 pm_runtime_disable(&pdev->dev);
2551 clean_ndev_ret:
2552 free_netdev(priv->ndev);
2553 return ret;
2554 }
2555
cpsw_remove_child_device(struct device * dev,void * c)2556 static int cpsw_remove_child_device(struct device *dev, void *c)
2557 {
2558 struct platform_device *pdev = to_platform_device(dev);
2559
2560 of_device_unregister(pdev);
2561
2562 return 0;
2563 }
2564
cpsw_remove(struct platform_device * pdev)2565 static int cpsw_remove(struct platform_device *pdev)
2566 {
2567 struct net_device *ndev = platform_get_drvdata(pdev);
2568 struct cpsw_priv *priv = netdev_priv(ndev);
2569
2570 if (priv->data.dual_emac)
2571 unregister_netdev(cpsw_get_slave_ndev(priv, 1));
2572 unregister_netdev(ndev);
2573
2574 cpsw_ale_destroy(priv->ale);
2575 cpdma_chan_destroy(priv->txch);
2576 cpdma_chan_destroy(priv->rxch);
2577 cpdma_ctlr_destroy(priv->dma);
2578 pm_runtime_disable(&pdev->dev);
2579 device_for_each_child(&pdev->dev, NULL, cpsw_remove_child_device);
2580 if (priv->data.dual_emac)
2581 free_netdev(cpsw_get_slave_ndev(priv, 1));
2582 free_netdev(ndev);
2583 return 0;
2584 }
2585
2586 #ifdef CONFIG_PM_SLEEP
cpsw_suspend(struct device * dev)2587 static int cpsw_suspend(struct device *dev)
2588 {
2589 struct platform_device *pdev = to_platform_device(dev);
2590 struct net_device *ndev = platform_get_drvdata(pdev);
2591 struct cpsw_priv *priv = netdev_priv(ndev);
2592
2593 if (priv->data.dual_emac) {
2594 int i;
2595
2596 for (i = 0; i < priv->data.slaves; i++) {
2597 if (netif_running(priv->slaves[i].ndev))
2598 cpsw_ndo_stop(priv->slaves[i].ndev);
2599 soft_reset_slave(priv->slaves + i);
2600 }
2601 } else {
2602 if (netif_running(ndev))
2603 cpsw_ndo_stop(ndev);
2604 for_each_slave(priv, soft_reset_slave);
2605 }
2606
2607 pm_runtime_put_sync(&pdev->dev);
2608
2609 /* Select sleep pin state */
2610 pinctrl_pm_select_sleep_state(&pdev->dev);
2611
2612 return 0;
2613 }
2614
cpsw_resume(struct device * dev)2615 static int cpsw_resume(struct device *dev)
2616 {
2617 struct platform_device *pdev = to_platform_device(dev);
2618 struct net_device *ndev = platform_get_drvdata(pdev);
2619 struct cpsw_priv *priv = netdev_priv(ndev);
2620
2621 pm_runtime_get_sync(&pdev->dev);
2622
2623 /* Select default pin state */
2624 pinctrl_pm_select_default_state(&pdev->dev);
2625
2626 if (priv->data.dual_emac) {
2627 int i;
2628
2629 for (i = 0; i < priv->data.slaves; i++) {
2630 if (netif_running(priv->slaves[i].ndev))
2631 cpsw_ndo_open(priv->slaves[i].ndev);
2632 }
2633 } else {
2634 if (netif_running(ndev))
2635 cpsw_ndo_open(ndev);
2636 }
2637 return 0;
2638 }
2639 #endif
2640
2641 static SIMPLE_DEV_PM_OPS(cpsw_pm_ops, cpsw_suspend, cpsw_resume);
2642
2643 static struct platform_driver cpsw_driver = {
2644 .driver = {
2645 .name = "cpsw",
2646 .pm = &cpsw_pm_ops,
2647 .of_match_table = cpsw_of_mtable,
2648 },
2649 .probe = cpsw_probe,
2650 .remove = cpsw_remove,
2651 };
2652
2653 module_platform_driver(cpsw_driver);
2654
2655 MODULE_LICENSE("GPL");
2656 MODULE_AUTHOR("Cyril Chemparathy <cyril@ti.com>");
2657 MODULE_AUTHOR("Mugunthan V N <mugunthanvnm@ti.com>");
2658 MODULE_DESCRIPTION("TI CPSW Ethernet driver");
2659