1 /* $Id: tg3.h,v 1.37.2.32 2002/03/11 12:18:18 davem Exp $ 2 * tg3.h: Definitions for Broadcom Tigon3 ethernet driver. 3 * 4 * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com) 5 * Copyright (C) 2001 Jeff Garzik (jgarzik@pobox.com) 6 * Copyright (C) 2004 Sun Microsystems Inc. 7 * Copyright (C) 2007-2014 Broadcom Corporation. 8 */ 9 10 #ifndef _T3_H 11 #define _T3_H 12 13 #define TG3_64BIT_REG_HIGH 0x00UL 14 #define TG3_64BIT_REG_LOW 0x04UL 15 16 /* Descriptor block info. */ 17 #define TG3_BDINFO_HOST_ADDR 0x0UL /* 64-bit */ 18 #define TG3_BDINFO_MAXLEN_FLAGS 0x8UL /* 32-bit */ 19 #define BDINFO_FLAGS_USE_EXT_RECV 0x00000001 /* ext rx_buffer_desc */ 20 #define BDINFO_FLAGS_DISABLED 0x00000002 21 #define BDINFO_FLAGS_MAXLEN_MASK 0xffff0000 22 #define BDINFO_FLAGS_MAXLEN_SHIFT 16 23 #define TG3_BDINFO_NIC_ADDR 0xcUL /* 32-bit */ 24 #define TG3_BDINFO_SIZE 0x10UL 25 26 #define TG3_RX_STD_MAX_SIZE_5700 512 27 #define TG3_RX_STD_MAX_SIZE_5717 2048 28 #define TG3_RX_JMB_MAX_SIZE_5700 256 29 #define TG3_RX_JMB_MAX_SIZE_5717 1024 30 #define TG3_RX_RET_MAX_SIZE_5700 1024 31 #define TG3_RX_RET_MAX_SIZE_5705 512 32 #define TG3_RX_RET_MAX_SIZE_5717 4096 33 34 #define TG3_RSS_INDIR_TBL_SIZE 128 35 36 /* First 256 bytes are a mirror of PCI config space. */ 37 #define TG3PCI_VENDOR 0x00000000 38 #define TG3PCI_VENDOR_BROADCOM 0x14e4 39 #define TG3PCI_DEVICE 0x00000002 40 #define TG3PCI_DEVICE_TIGON3_1 0x1644 /* BCM5700 */ 41 #define TG3PCI_DEVICE_TIGON3_2 0x1645 /* BCM5701 */ 42 #define TG3PCI_DEVICE_TIGON3_3 0x1646 /* BCM5702 */ 43 #define TG3PCI_DEVICE_TIGON3_4 0x1647 /* BCM5703 */ 44 #define TG3PCI_DEVICE_TIGON3_5761S 0x1688 45 #define TG3PCI_DEVICE_TIGON3_5761SE 0x1689 46 #define TG3PCI_DEVICE_TIGON3_57780 0x1692 47 #define TG3PCI_DEVICE_TIGON3_5787M 0x1693 48 #define TG3PCI_DEVICE_TIGON3_57760 0x1690 49 #define TG3PCI_DEVICE_TIGON3_57790 0x1694 50 #define TG3PCI_DEVICE_TIGON3_57788 0x1691 51 #define TG3PCI_DEVICE_TIGON3_5785_G 0x1699 /* GPHY */ 52 #define TG3PCI_DEVICE_TIGON3_5785_F 0x16a0 /* 10/100 only */ 53 #define TG3PCI_DEVICE_TIGON3_5717 0x1655 54 #define TG3PCI_DEVICE_TIGON3_5717_C 0x1665 55 #define TG3PCI_DEVICE_TIGON3_5718 0x1656 56 #define TG3PCI_DEVICE_TIGON3_57781 0x16b1 57 #define TG3PCI_DEVICE_TIGON3_57785 0x16b5 58 #define TG3PCI_DEVICE_TIGON3_57761 0x16b0 59 #define TG3PCI_DEVICE_TIGON3_57765 0x16b4 60 #define TG3PCI_DEVICE_TIGON3_57791 0x16b2 61 #define TG3PCI_DEVICE_TIGON3_57795 0x16b6 62 #define TG3PCI_DEVICE_TIGON3_5719 0x1657 63 #define TG3PCI_DEVICE_TIGON3_5720 0x165f 64 #define TG3PCI_DEVICE_TIGON3_57762 0x1682 65 #define TG3PCI_DEVICE_TIGON3_57766 0x1686 66 #define TG3PCI_DEVICE_TIGON3_57786 0x16b3 67 #define TG3PCI_DEVICE_TIGON3_57782 0x16b7 68 #define TG3PCI_DEVICE_TIGON3_5762 0x1687 69 #define TG3PCI_DEVICE_TIGON3_5725 0x1643 70 #define TG3PCI_DEVICE_TIGON3_5727 0x16f3 71 #define TG3PCI_DEVICE_TIGON3_57764 0x1642 72 #define TG3PCI_DEVICE_TIGON3_57767 0x1683 73 #define TG3PCI_DEVICE_TIGON3_57787 0x1641 74 /* 0x04 --> 0x2c unused */ 75 #define TG3PCI_SUBVENDOR_ID_BROADCOM PCI_VENDOR_ID_BROADCOM 76 #define TG3PCI_SUBDEVICE_ID_BROADCOM_95700A6 0x1644 77 #define TG3PCI_SUBDEVICE_ID_BROADCOM_95701A5 0x0001 78 #define TG3PCI_SUBDEVICE_ID_BROADCOM_95700T6 0x0002 79 #define TG3PCI_SUBDEVICE_ID_BROADCOM_95700A9 0x0003 80 #define TG3PCI_SUBDEVICE_ID_BROADCOM_95701T1 0x0005 81 #define TG3PCI_SUBDEVICE_ID_BROADCOM_95701T8 0x0006 82 #define TG3PCI_SUBDEVICE_ID_BROADCOM_95701A7 0x0007 83 #define TG3PCI_SUBDEVICE_ID_BROADCOM_95701A10 0x0008 84 #define TG3PCI_SUBDEVICE_ID_BROADCOM_95701A12 0x8008 85 #define TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX1 0x0009 86 #define TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX2 0x8009 87 #define TG3PCI_SUBVENDOR_ID_3COM PCI_VENDOR_ID_3COM 88 #define TG3PCI_SUBDEVICE_ID_3COM_3C996T 0x1000 89 #define TG3PCI_SUBDEVICE_ID_3COM_3C996BT 0x1006 90 #define TG3PCI_SUBDEVICE_ID_3COM_3C996SX 0x1004 91 #define TG3PCI_SUBDEVICE_ID_3COM_3C1000T 0x1007 92 #define TG3PCI_SUBDEVICE_ID_3COM_3C940BR01 0x1008 93 #define TG3PCI_SUBVENDOR_ID_DELL PCI_VENDOR_ID_DELL 94 #define TG3PCI_SUBDEVICE_ID_DELL_VIPER 0x00d1 95 #define TG3PCI_SUBDEVICE_ID_DELL_JAGUAR 0x0106 96 #define TG3PCI_SUBDEVICE_ID_DELL_MERLOT 0x0109 97 #define TG3PCI_SUBDEVICE_ID_DELL_SLIM_MERLOT 0x010a 98 #define TG3PCI_SUBDEVICE_ID_DELL_5762 0x07f0 99 #define TG3PCI_SUBVENDOR_ID_COMPAQ PCI_VENDOR_ID_COMPAQ 100 #define TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE 0x007c 101 #define TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE_2 0x009a 102 #define TG3PCI_SUBDEVICE_ID_COMPAQ_CHANGELING 0x007d 103 #define TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780 0x0085 104 #define TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780_2 0x0099 105 #define TG3PCI_SUBVENDOR_ID_IBM PCI_VENDOR_ID_IBM 106 #define TG3PCI_SUBDEVICE_ID_IBM_5703SAX2 0x0281 107 #define TG3PCI_SUBDEVICE_ID_ACER_57780_A 0x0601 108 #define TG3PCI_SUBDEVICE_ID_ACER_57780_B 0x0612 109 #define TG3PCI_SUBDEVICE_ID_LENOVO_5787M 0x3056 110 111 /* 0x30 --> 0x64 unused */ 112 #define TG3PCI_MSI_DATA 0x00000064 113 /* 0x66 --> 0x68 unused */ 114 #define TG3PCI_MISC_HOST_CTRL 0x00000068 115 #define MISC_HOST_CTRL_CLEAR_INT 0x00000001 116 #define MISC_HOST_CTRL_MASK_PCI_INT 0x00000002 117 #define MISC_HOST_CTRL_BYTE_SWAP 0x00000004 118 #define MISC_HOST_CTRL_WORD_SWAP 0x00000008 119 #define MISC_HOST_CTRL_PCISTATE_RW 0x00000010 120 #define MISC_HOST_CTRL_CLKREG_RW 0x00000020 121 #define MISC_HOST_CTRL_REGWORD_SWAP 0x00000040 122 #define MISC_HOST_CTRL_INDIR_ACCESS 0x00000080 123 #define MISC_HOST_CTRL_IRQ_MASK_MODE 0x00000100 124 #define MISC_HOST_CTRL_TAGGED_STATUS 0x00000200 125 #define MISC_HOST_CTRL_CHIPREV 0xffff0000 126 #define MISC_HOST_CTRL_CHIPREV_SHIFT 16 127 128 #define CHIPREV_ID_5700_A0 0x7000 129 #define CHIPREV_ID_5700_A1 0x7001 130 #define CHIPREV_ID_5700_B0 0x7100 131 #define CHIPREV_ID_5700_B1 0x7101 132 #define CHIPREV_ID_5700_B3 0x7102 133 #define CHIPREV_ID_5700_ALTIMA 0x7104 134 #define CHIPREV_ID_5700_C0 0x7200 135 #define CHIPREV_ID_5701_A0 0x0000 136 #define CHIPREV_ID_5701_B0 0x0100 137 #define CHIPREV_ID_5701_B2 0x0102 138 #define CHIPREV_ID_5701_B5 0x0105 139 #define CHIPREV_ID_5703_A0 0x1000 140 #define CHIPREV_ID_5703_A1 0x1001 141 #define CHIPREV_ID_5703_A2 0x1002 142 #define CHIPREV_ID_5703_A3 0x1003 143 #define CHIPREV_ID_5704_A0 0x2000 144 #define CHIPREV_ID_5704_A1 0x2001 145 #define CHIPREV_ID_5704_A2 0x2002 146 #define CHIPREV_ID_5704_A3 0x2003 147 #define CHIPREV_ID_5705_A0 0x3000 148 #define CHIPREV_ID_5705_A1 0x3001 149 #define CHIPREV_ID_5705_A2 0x3002 150 #define CHIPREV_ID_5705_A3 0x3003 151 #define CHIPREV_ID_5750_A0 0x4000 152 #define CHIPREV_ID_5750_A1 0x4001 153 #define CHIPREV_ID_5750_A3 0x4003 154 #define CHIPREV_ID_5750_C2 0x4202 155 #define CHIPREV_ID_5752_A0_HW 0x5000 156 #define CHIPREV_ID_5752_A0 0x6000 157 #define CHIPREV_ID_5752_A1 0x6001 158 #define CHIPREV_ID_5714_A2 0x9002 159 #define CHIPREV_ID_5906_A1 0xc001 160 #define CHIPREV_ID_57780_A0 0x57780000 161 #define CHIPREV_ID_57780_A1 0x57780001 162 #define CHIPREV_ID_5717_A0 0x05717000 163 #define CHIPREV_ID_5717_C0 0x05717200 164 #define CHIPREV_ID_57765_A0 0x57785000 165 #define CHIPREV_ID_5719_A0 0x05719000 166 #define CHIPREV_ID_5720_A0 0x05720000 167 #define CHIPREV_ID_5762_A0 0x05762000 168 169 #define ASIC_REV_5700 0x07 170 #define ASIC_REV_5701 0x00 171 #define ASIC_REV_5703 0x01 172 #define ASIC_REV_5704 0x02 173 #define ASIC_REV_5705 0x03 174 #define ASIC_REV_5750 0x04 175 #define ASIC_REV_5752 0x06 176 #define ASIC_REV_5780 0x08 177 #define ASIC_REV_5714 0x09 178 #define ASIC_REV_5755 0x0a 179 #define ASIC_REV_5787 0x0b 180 #define ASIC_REV_5906 0x0c 181 #define ASIC_REV_USE_PROD_ID_REG 0x0f 182 #define ASIC_REV_5784 0x5784 183 #define ASIC_REV_5761 0x5761 184 #define ASIC_REV_5785 0x5785 185 #define ASIC_REV_57780 0x57780 186 #define ASIC_REV_5717 0x5717 187 #define ASIC_REV_57765 0x57785 188 #define ASIC_REV_5719 0x5719 189 #define ASIC_REV_5720 0x5720 190 #define ASIC_REV_57766 0x57766 191 #define ASIC_REV_5762 0x5762 192 #define CHIPREV_5700_AX 0x70 193 #define CHIPREV_5700_BX 0x71 194 #define CHIPREV_5700_CX 0x72 195 #define CHIPREV_5701_AX 0x00 196 #define CHIPREV_5703_AX 0x10 197 #define CHIPREV_5704_AX 0x20 198 #define CHIPREV_5704_BX 0x21 199 #define CHIPREV_5750_AX 0x40 200 #define CHIPREV_5750_BX 0x41 201 #define CHIPREV_5784_AX 0x57840 202 #define CHIPREV_5761_AX 0x57610 203 #define CHIPREV_57765_AX 0x577650 204 #define METAL_REV_A0 0x00 205 #define METAL_REV_A1 0x01 206 #define METAL_REV_B0 0x00 207 #define METAL_REV_B1 0x01 208 #define METAL_REV_B2 0x02 209 #define TG3PCI_DMA_RW_CTRL 0x0000006c 210 #define DMA_RWCTRL_DIS_CACHE_ALIGNMENT 0x00000001 211 #define DMA_RWCTRL_TAGGED_STAT_WA 0x00000080 212 #define DMA_RWCTRL_CRDRDR_RDMA_MRRS_MSK 0x00000380 213 #define DMA_RWCTRL_READ_BNDRY_MASK 0x00000700 214 #define DMA_RWCTRL_READ_BNDRY_DISAB 0x00000000 215 #define DMA_RWCTRL_READ_BNDRY_16 0x00000100 216 #define DMA_RWCTRL_READ_BNDRY_128_PCIX 0x00000100 217 #define DMA_RWCTRL_READ_BNDRY_32 0x00000200 218 #define DMA_RWCTRL_READ_BNDRY_256_PCIX 0x00000200 219 #define DMA_RWCTRL_READ_BNDRY_64 0x00000300 220 #define DMA_RWCTRL_READ_BNDRY_384_PCIX 0x00000300 221 #define DMA_RWCTRL_READ_BNDRY_128 0x00000400 222 #define DMA_RWCTRL_READ_BNDRY_256 0x00000500 223 #define DMA_RWCTRL_READ_BNDRY_512 0x00000600 224 #define DMA_RWCTRL_READ_BNDRY_1024 0x00000700 225 #define DMA_RWCTRL_WRITE_BNDRY_MASK 0x00003800 226 #define DMA_RWCTRL_WRITE_BNDRY_DISAB 0x00000000 227 #define DMA_RWCTRL_WRITE_BNDRY_16 0x00000800 228 #define DMA_RWCTRL_WRITE_BNDRY_128_PCIX 0x00000800 229 #define DMA_RWCTRL_WRITE_BNDRY_32 0x00001000 230 #define DMA_RWCTRL_WRITE_BNDRY_256_PCIX 0x00001000 231 #define DMA_RWCTRL_WRITE_BNDRY_64 0x00001800 232 #define DMA_RWCTRL_WRITE_BNDRY_384_PCIX 0x00001800 233 #define DMA_RWCTRL_WRITE_BNDRY_128 0x00002000 234 #define DMA_RWCTRL_WRITE_BNDRY_256 0x00002800 235 #define DMA_RWCTRL_WRITE_BNDRY_512 0x00003000 236 #define DMA_RWCTRL_WRITE_BNDRY_1024 0x00003800 237 #define DMA_RWCTRL_ONE_DMA 0x00004000 238 #define DMA_RWCTRL_READ_WATER 0x00070000 239 #define DMA_RWCTRL_READ_WATER_SHIFT 16 240 #define DMA_RWCTRL_WRITE_WATER 0x00380000 241 #define DMA_RWCTRL_WRITE_WATER_SHIFT 19 242 #define DMA_RWCTRL_USE_MEM_READ_MULT 0x00400000 243 #define DMA_RWCTRL_ASSERT_ALL_BE 0x00800000 244 #define DMA_RWCTRL_PCI_READ_CMD 0x0f000000 245 #define DMA_RWCTRL_PCI_READ_CMD_SHIFT 24 246 #define DMA_RWCTRL_PCI_WRITE_CMD 0xf0000000 247 #define DMA_RWCTRL_PCI_WRITE_CMD_SHIFT 28 248 #define DMA_RWCTRL_WRITE_BNDRY_64_PCIE 0x10000000 249 #define DMA_RWCTRL_WRITE_BNDRY_128_PCIE 0x30000000 250 #define DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE 0x70000000 251 #define TG3PCI_PCISTATE 0x00000070 252 #define PCISTATE_FORCE_RESET 0x00000001 253 #define PCISTATE_INT_NOT_ACTIVE 0x00000002 254 #define PCISTATE_CONV_PCI_MODE 0x00000004 255 #define PCISTATE_BUS_SPEED_HIGH 0x00000008 256 #define PCISTATE_BUS_32BIT 0x00000010 257 #define PCISTATE_ROM_ENABLE 0x00000020 258 #define PCISTATE_ROM_RETRY_ENABLE 0x00000040 259 #define PCISTATE_FLAT_VIEW 0x00000100 260 #define PCISTATE_RETRY_SAME_DMA 0x00002000 261 #define PCISTATE_ALLOW_APE_CTLSPC_WR 0x00010000 262 #define PCISTATE_ALLOW_APE_SHMEM_WR 0x00020000 263 #define PCISTATE_ALLOW_APE_PSPACE_WR 0x00040000 264 #define TG3PCI_CLOCK_CTRL 0x00000074 265 #define CLOCK_CTRL_CORECLK_DISABLE 0x00000200 266 #define CLOCK_CTRL_RXCLK_DISABLE 0x00000400 267 #define CLOCK_CTRL_TXCLK_DISABLE 0x00000800 268 #define CLOCK_CTRL_ALTCLK 0x00001000 269 #define CLOCK_CTRL_PWRDOWN_PLL133 0x00008000 270 #define CLOCK_CTRL_44MHZ_CORE 0x00040000 271 #define CLOCK_CTRL_625_CORE 0x00100000 272 #define CLOCK_CTRL_FORCE_CLKRUN 0x00200000 273 #define CLOCK_CTRL_CLKRUN_OENABLE 0x00400000 274 #define CLOCK_CTRL_DELAY_PCI_GRANT 0x80000000 275 #define TG3PCI_REG_BASE_ADDR 0x00000078 276 #define TG3PCI_MEM_WIN_BASE_ADDR 0x0000007c 277 #define TG3PCI_REG_DATA 0x00000080 278 #define TG3PCI_MEM_WIN_DATA 0x00000084 279 #define TG3PCI_MISC_LOCAL_CTRL 0x00000090 280 /* 0x94 --> 0x98 unused */ 281 #define TG3PCI_STD_RING_PROD_IDX 0x00000098 /* 64-bit */ 282 #define TG3PCI_RCV_RET_RING_CON_IDX 0x000000a0 /* 64-bit */ 283 /* 0xa8 --> 0xb8 unused */ 284 #define TG3PCI_DEV_STATUS_CTRL 0x000000b4 285 #define MAX_READ_REQ_SIZE_2048 0x00004000 286 #define MAX_READ_REQ_MASK 0x00007000 287 #define TG3PCI_DUAL_MAC_CTRL 0x000000b8 288 #define DUAL_MAC_CTRL_CH_MASK 0x00000003 289 #define DUAL_MAC_CTRL_ID 0x00000004 290 #define TG3PCI_PRODID_ASICREV 0x000000bc 291 #define PROD_ID_ASIC_REV_MASK 0x0fffffff 292 /* 0xc0 --> 0xf4 unused */ 293 294 #define TG3PCI_GEN2_PRODID_ASICREV 0x000000f4 295 #define TG3PCI_GEN15_PRODID_ASICREV 0x000000fc 296 /* 0xf8 --> 0x200 unused */ 297 298 #define TG3_CORR_ERR_STAT 0x00000110 299 #define TG3_CORR_ERR_STAT_CLEAR 0xffffffff 300 /* 0x114 --> 0x200 unused */ 301 302 /* Mailbox registers */ 303 #define MAILBOX_INTERRUPT_0 0x00000200 /* 64-bit */ 304 #define MAILBOX_INTERRUPT_1 0x00000208 /* 64-bit */ 305 #define MAILBOX_INTERRUPT_2 0x00000210 /* 64-bit */ 306 #define MAILBOX_INTERRUPT_3 0x00000218 /* 64-bit */ 307 #define MAILBOX_GENERAL_0 0x00000220 /* 64-bit */ 308 #define MAILBOX_GENERAL_1 0x00000228 /* 64-bit */ 309 #define MAILBOX_GENERAL_2 0x00000230 /* 64-bit */ 310 #define MAILBOX_GENERAL_3 0x00000238 /* 64-bit */ 311 #define MAILBOX_GENERAL_4 0x00000240 /* 64-bit */ 312 #define MAILBOX_GENERAL_5 0x00000248 /* 64-bit */ 313 #define MAILBOX_GENERAL_6 0x00000250 /* 64-bit */ 314 #define MAILBOX_GENERAL_7 0x00000258 /* 64-bit */ 315 #define MAILBOX_RELOAD_STAT 0x00000260 /* 64-bit */ 316 #define MAILBOX_RCV_STD_PROD_IDX 0x00000268 /* 64-bit */ 317 #define TG3_RX_STD_PROD_IDX_REG (MAILBOX_RCV_STD_PROD_IDX + \ 318 TG3_64BIT_REG_LOW) 319 #define MAILBOX_RCV_JUMBO_PROD_IDX 0x00000270 /* 64-bit */ 320 #define TG3_RX_JMB_PROD_IDX_REG (MAILBOX_RCV_JUMBO_PROD_IDX + \ 321 TG3_64BIT_REG_LOW) 322 #define MAILBOX_RCV_MINI_PROD_IDX 0x00000278 /* 64-bit */ 323 #define MAILBOX_RCVRET_CON_IDX_0 0x00000280 /* 64-bit */ 324 #define MAILBOX_RCVRET_CON_IDX_1 0x00000288 /* 64-bit */ 325 #define MAILBOX_RCVRET_CON_IDX_2 0x00000290 /* 64-bit */ 326 #define MAILBOX_RCVRET_CON_IDX_3 0x00000298 /* 64-bit */ 327 #define MAILBOX_RCVRET_CON_IDX_4 0x000002a0 /* 64-bit */ 328 #define MAILBOX_RCVRET_CON_IDX_5 0x000002a8 /* 64-bit */ 329 #define MAILBOX_RCVRET_CON_IDX_6 0x000002b0 /* 64-bit */ 330 #define MAILBOX_RCVRET_CON_IDX_7 0x000002b8 /* 64-bit */ 331 #define MAILBOX_RCVRET_CON_IDX_8 0x000002c0 /* 64-bit */ 332 #define MAILBOX_RCVRET_CON_IDX_9 0x000002c8 /* 64-bit */ 333 #define MAILBOX_RCVRET_CON_IDX_10 0x000002d0 /* 64-bit */ 334 #define MAILBOX_RCVRET_CON_IDX_11 0x000002d8 /* 64-bit */ 335 #define MAILBOX_RCVRET_CON_IDX_12 0x000002e0 /* 64-bit */ 336 #define MAILBOX_RCVRET_CON_IDX_13 0x000002e8 /* 64-bit */ 337 #define MAILBOX_RCVRET_CON_IDX_14 0x000002f0 /* 64-bit */ 338 #define MAILBOX_RCVRET_CON_IDX_15 0x000002f8 /* 64-bit */ 339 #define MAILBOX_SNDHOST_PROD_IDX_0 0x00000300 /* 64-bit */ 340 #define MAILBOX_SNDHOST_PROD_IDX_1 0x00000308 /* 64-bit */ 341 #define MAILBOX_SNDHOST_PROD_IDX_2 0x00000310 /* 64-bit */ 342 #define MAILBOX_SNDHOST_PROD_IDX_3 0x00000318 /* 64-bit */ 343 #define MAILBOX_SNDHOST_PROD_IDX_4 0x00000320 /* 64-bit */ 344 #define MAILBOX_SNDHOST_PROD_IDX_5 0x00000328 /* 64-bit */ 345 #define MAILBOX_SNDHOST_PROD_IDX_6 0x00000330 /* 64-bit */ 346 #define MAILBOX_SNDHOST_PROD_IDX_7 0x00000338 /* 64-bit */ 347 #define MAILBOX_SNDHOST_PROD_IDX_8 0x00000340 /* 64-bit */ 348 #define MAILBOX_SNDHOST_PROD_IDX_9 0x00000348 /* 64-bit */ 349 #define MAILBOX_SNDHOST_PROD_IDX_10 0x00000350 /* 64-bit */ 350 #define MAILBOX_SNDHOST_PROD_IDX_11 0x00000358 /* 64-bit */ 351 #define MAILBOX_SNDHOST_PROD_IDX_12 0x00000360 /* 64-bit */ 352 #define MAILBOX_SNDHOST_PROD_IDX_13 0x00000368 /* 64-bit */ 353 #define MAILBOX_SNDHOST_PROD_IDX_14 0x00000370 /* 64-bit */ 354 #define MAILBOX_SNDHOST_PROD_IDX_15 0x00000378 /* 64-bit */ 355 #define MAILBOX_SNDNIC_PROD_IDX_0 0x00000380 /* 64-bit */ 356 #define MAILBOX_SNDNIC_PROD_IDX_1 0x00000388 /* 64-bit */ 357 #define MAILBOX_SNDNIC_PROD_IDX_2 0x00000390 /* 64-bit */ 358 #define MAILBOX_SNDNIC_PROD_IDX_3 0x00000398 /* 64-bit */ 359 #define MAILBOX_SNDNIC_PROD_IDX_4 0x000003a0 /* 64-bit */ 360 #define MAILBOX_SNDNIC_PROD_IDX_5 0x000003a8 /* 64-bit */ 361 #define MAILBOX_SNDNIC_PROD_IDX_6 0x000003b0 /* 64-bit */ 362 #define MAILBOX_SNDNIC_PROD_IDX_7 0x000003b8 /* 64-bit */ 363 #define MAILBOX_SNDNIC_PROD_IDX_8 0x000003c0 /* 64-bit */ 364 #define MAILBOX_SNDNIC_PROD_IDX_9 0x000003c8 /* 64-bit */ 365 #define MAILBOX_SNDNIC_PROD_IDX_10 0x000003d0 /* 64-bit */ 366 #define MAILBOX_SNDNIC_PROD_IDX_11 0x000003d8 /* 64-bit */ 367 #define MAILBOX_SNDNIC_PROD_IDX_12 0x000003e0 /* 64-bit */ 368 #define MAILBOX_SNDNIC_PROD_IDX_13 0x000003e8 /* 64-bit */ 369 #define MAILBOX_SNDNIC_PROD_IDX_14 0x000003f0 /* 64-bit */ 370 #define MAILBOX_SNDNIC_PROD_IDX_15 0x000003f8 /* 64-bit */ 371 372 /* MAC control registers */ 373 #define MAC_MODE 0x00000400 374 #define MAC_MODE_RESET 0x00000001 375 #define MAC_MODE_HALF_DUPLEX 0x00000002 376 #define MAC_MODE_PORT_MODE_MASK 0x0000000c 377 #define MAC_MODE_PORT_MODE_TBI 0x0000000c 378 #define MAC_MODE_PORT_MODE_GMII 0x00000008 379 #define MAC_MODE_PORT_MODE_MII 0x00000004 380 #define MAC_MODE_PORT_MODE_NONE 0x00000000 381 #define MAC_MODE_PORT_INT_LPBACK 0x00000010 382 #define MAC_MODE_TAGGED_MAC_CTRL 0x00000080 383 #define MAC_MODE_TX_BURSTING 0x00000100 384 #define MAC_MODE_MAX_DEFER 0x00000200 385 #define MAC_MODE_LINK_POLARITY 0x00000400 386 #define MAC_MODE_RXSTAT_ENABLE 0x00000800 387 #define MAC_MODE_RXSTAT_CLEAR 0x00001000 388 #define MAC_MODE_RXSTAT_FLUSH 0x00002000 389 #define MAC_MODE_TXSTAT_ENABLE 0x00004000 390 #define MAC_MODE_TXSTAT_CLEAR 0x00008000 391 #define MAC_MODE_TXSTAT_FLUSH 0x00010000 392 #define MAC_MODE_SEND_CONFIGS 0x00020000 393 #define MAC_MODE_MAGIC_PKT_ENABLE 0x00040000 394 #define MAC_MODE_ACPI_ENABLE 0x00080000 395 #define MAC_MODE_MIP_ENABLE 0x00100000 396 #define MAC_MODE_TDE_ENABLE 0x00200000 397 #define MAC_MODE_RDE_ENABLE 0x00400000 398 #define MAC_MODE_FHDE_ENABLE 0x00800000 399 #define MAC_MODE_KEEP_FRAME_IN_WOL 0x01000000 400 #define MAC_MODE_APE_RX_EN 0x08000000 401 #define MAC_MODE_APE_TX_EN 0x10000000 402 #define MAC_STATUS 0x00000404 403 #define MAC_STATUS_PCS_SYNCED 0x00000001 404 #define MAC_STATUS_SIGNAL_DET 0x00000002 405 #define MAC_STATUS_RCVD_CFG 0x00000004 406 #define MAC_STATUS_CFG_CHANGED 0x00000008 407 #define MAC_STATUS_SYNC_CHANGED 0x00000010 408 #define MAC_STATUS_PORT_DEC_ERR 0x00000400 409 #define MAC_STATUS_LNKSTATE_CHANGED 0x00001000 410 #define MAC_STATUS_MI_COMPLETION 0x00400000 411 #define MAC_STATUS_MI_INTERRUPT 0x00800000 412 #define MAC_STATUS_AP_ERROR 0x01000000 413 #define MAC_STATUS_ODI_ERROR 0x02000000 414 #define MAC_STATUS_RXSTAT_OVERRUN 0x04000000 415 #define MAC_STATUS_TXSTAT_OVERRUN 0x08000000 416 #define MAC_EVENT 0x00000408 417 #define MAC_EVENT_PORT_DECODE_ERR 0x00000400 418 #define MAC_EVENT_LNKSTATE_CHANGED 0x00001000 419 #define MAC_EVENT_MI_COMPLETION 0x00400000 420 #define MAC_EVENT_MI_INTERRUPT 0x00800000 421 #define MAC_EVENT_AP_ERROR 0x01000000 422 #define MAC_EVENT_ODI_ERROR 0x02000000 423 #define MAC_EVENT_RXSTAT_OVERRUN 0x04000000 424 #define MAC_EVENT_TXSTAT_OVERRUN 0x08000000 425 #define MAC_LED_CTRL 0x0000040c 426 #define LED_CTRL_LNKLED_OVERRIDE 0x00000001 427 #define LED_CTRL_1000MBPS_ON 0x00000002 428 #define LED_CTRL_100MBPS_ON 0x00000004 429 #define LED_CTRL_10MBPS_ON 0x00000008 430 #define LED_CTRL_TRAFFIC_OVERRIDE 0x00000010 431 #define LED_CTRL_TRAFFIC_BLINK 0x00000020 432 #define LED_CTRL_TRAFFIC_LED 0x00000040 433 #define LED_CTRL_1000MBPS_STATUS 0x00000080 434 #define LED_CTRL_100MBPS_STATUS 0x00000100 435 #define LED_CTRL_10MBPS_STATUS 0x00000200 436 #define LED_CTRL_TRAFFIC_STATUS 0x00000400 437 #define LED_CTRL_MODE_MAC 0x00000000 438 #define LED_CTRL_MODE_PHY_1 0x00000800 439 #define LED_CTRL_MODE_PHY_2 0x00001000 440 #define LED_CTRL_MODE_SHASTA_MAC 0x00002000 441 #define LED_CTRL_MODE_SHARED 0x00004000 442 #define LED_CTRL_MODE_COMBO 0x00008000 443 #define LED_CTRL_BLINK_RATE_MASK 0x7ff80000 444 #define LED_CTRL_BLINK_RATE_SHIFT 19 445 #define LED_CTRL_BLINK_PER_OVERRIDE 0x00080000 446 #define LED_CTRL_BLINK_RATE_OVERRIDE 0x80000000 447 #define MAC_ADDR_0_HIGH 0x00000410 /* upper 2 bytes */ 448 #define MAC_ADDR_0_LOW 0x00000414 /* lower 4 bytes */ 449 #define MAC_ADDR_1_HIGH 0x00000418 /* upper 2 bytes */ 450 #define MAC_ADDR_1_LOW 0x0000041c /* lower 4 bytes */ 451 #define MAC_ADDR_2_HIGH 0x00000420 /* upper 2 bytes */ 452 #define MAC_ADDR_2_LOW 0x00000424 /* lower 4 bytes */ 453 #define MAC_ADDR_3_HIGH 0x00000428 /* upper 2 bytes */ 454 #define MAC_ADDR_3_LOW 0x0000042c /* lower 4 bytes */ 455 #define MAC_ACPI_MBUF_PTR 0x00000430 456 #define MAC_ACPI_LEN_OFFSET 0x00000434 457 #define ACPI_LENOFF_LEN_MASK 0x0000ffff 458 #define ACPI_LENOFF_LEN_SHIFT 0 459 #define ACPI_LENOFF_OFF_MASK 0x0fff0000 460 #define ACPI_LENOFF_OFF_SHIFT 16 461 #define MAC_TX_BACKOFF_SEED 0x00000438 462 #define TX_BACKOFF_SEED_MASK 0x000003ff 463 #define MAC_RX_MTU_SIZE 0x0000043c 464 #define RX_MTU_SIZE_MASK 0x0000ffff 465 #define MAC_PCS_TEST 0x00000440 466 #define PCS_TEST_PATTERN_MASK 0x000fffff 467 #define PCS_TEST_PATTERN_SHIFT 0 468 #define PCS_TEST_ENABLE 0x00100000 469 #define MAC_TX_AUTO_NEG 0x00000444 470 #define TX_AUTO_NEG_MASK 0x0000ffff 471 #define TX_AUTO_NEG_SHIFT 0 472 #define MAC_RX_AUTO_NEG 0x00000448 473 #define RX_AUTO_NEG_MASK 0x0000ffff 474 #define RX_AUTO_NEG_SHIFT 0 475 #define MAC_MI_COM 0x0000044c 476 #define MI_COM_CMD_MASK 0x0c000000 477 #define MI_COM_CMD_WRITE 0x04000000 478 #define MI_COM_CMD_READ 0x08000000 479 #define MI_COM_READ_FAILED 0x10000000 480 #define MI_COM_START 0x20000000 481 #define MI_COM_BUSY 0x20000000 482 #define MI_COM_PHY_ADDR_MASK 0x03e00000 483 #define MI_COM_PHY_ADDR_SHIFT 21 484 #define MI_COM_REG_ADDR_MASK 0x001f0000 485 #define MI_COM_REG_ADDR_SHIFT 16 486 #define MI_COM_DATA_MASK 0x0000ffff 487 #define MAC_MI_STAT 0x00000450 488 #define MAC_MI_STAT_LNKSTAT_ATTN_ENAB 0x00000001 489 #define MAC_MI_STAT_10MBPS_MODE 0x00000002 490 #define MAC_MI_MODE 0x00000454 491 #define MAC_MI_MODE_CLK_10MHZ 0x00000001 492 #define MAC_MI_MODE_SHORT_PREAMBLE 0x00000002 493 #define MAC_MI_MODE_AUTO_POLL 0x00000010 494 #define MAC_MI_MODE_500KHZ_CONST 0x00008000 495 #define MAC_MI_MODE_BASE 0x000c0000 /* XXX magic values XXX */ 496 #define MAC_AUTO_POLL_STATUS 0x00000458 497 #define MAC_AUTO_POLL_ERROR 0x00000001 498 #define MAC_TX_MODE 0x0000045c 499 #define TX_MODE_RESET 0x00000001 500 #define TX_MODE_ENABLE 0x00000002 501 #define TX_MODE_FLOW_CTRL_ENABLE 0x00000010 502 #define TX_MODE_BIG_BCKOFF_ENABLE 0x00000020 503 #define TX_MODE_LONG_PAUSE_ENABLE 0x00000040 504 #define TX_MODE_MBUF_LOCKUP_FIX 0x00000100 505 #define TX_MODE_JMB_FRM_LEN 0x00400000 506 #define TX_MODE_CNT_DN_MODE 0x00800000 507 #define MAC_TX_STATUS 0x00000460 508 #define TX_STATUS_XOFFED 0x00000001 509 #define TX_STATUS_SENT_XOFF 0x00000002 510 #define TX_STATUS_SENT_XON 0x00000004 511 #define TX_STATUS_LINK_UP 0x00000008 512 #define TX_STATUS_ODI_UNDERRUN 0x00000010 513 #define TX_STATUS_ODI_OVERRUN 0x00000020 514 #define MAC_TX_LENGTHS 0x00000464 515 #define TX_LENGTHS_SLOT_TIME_MASK 0x000000ff 516 #define TX_LENGTHS_SLOT_TIME_SHIFT 0 517 #define TX_LENGTHS_IPG_MASK 0x00000f00 518 #define TX_LENGTHS_IPG_SHIFT 8 519 #define TX_LENGTHS_IPG_CRS_MASK 0x00003000 520 #define TX_LENGTHS_IPG_CRS_SHIFT 12 521 #define TX_LENGTHS_JMB_FRM_LEN_MSK 0x00ff0000 522 #define TX_LENGTHS_CNT_DWN_VAL_MSK 0xff000000 523 #define MAC_RX_MODE 0x00000468 524 #define RX_MODE_RESET 0x00000001 525 #define RX_MODE_ENABLE 0x00000002 526 #define RX_MODE_FLOW_CTRL_ENABLE 0x00000004 527 #define RX_MODE_KEEP_MAC_CTRL 0x00000008 528 #define RX_MODE_KEEP_PAUSE 0x00000010 529 #define RX_MODE_ACCEPT_OVERSIZED 0x00000020 530 #define RX_MODE_ACCEPT_RUNTS 0x00000040 531 #define RX_MODE_LEN_CHECK 0x00000080 532 #define RX_MODE_PROMISC 0x00000100 533 #define RX_MODE_NO_CRC_CHECK 0x00000200 534 #define RX_MODE_KEEP_VLAN_TAG 0x00000400 535 #define RX_MODE_RSS_IPV4_HASH_EN 0x00010000 536 #define RX_MODE_RSS_TCP_IPV4_HASH_EN 0x00020000 537 #define RX_MODE_RSS_IPV6_HASH_EN 0x00040000 538 #define RX_MODE_RSS_TCP_IPV6_HASH_EN 0x00080000 539 #define RX_MODE_RSS_ITBL_HASH_BITS_7 0x00700000 540 #define RX_MODE_RSS_ENABLE 0x00800000 541 #define RX_MODE_IPV6_CSUM_ENABLE 0x01000000 542 #define RX_MODE_IPV4_FRAG_FIX 0x02000000 543 #define MAC_RX_STATUS 0x0000046c 544 #define RX_STATUS_REMOTE_TX_XOFFED 0x00000001 545 #define RX_STATUS_XOFF_RCVD 0x00000002 546 #define RX_STATUS_XON_RCVD 0x00000004 547 #define MAC_HASH_REG_0 0x00000470 548 #define MAC_HASH_REG_1 0x00000474 549 #define MAC_HASH_REG_2 0x00000478 550 #define MAC_HASH_REG_3 0x0000047c 551 #define MAC_RCV_RULE_0 0x00000480 552 #define MAC_RCV_VALUE_0 0x00000484 553 #define MAC_RCV_RULE_1 0x00000488 554 #define MAC_RCV_VALUE_1 0x0000048c 555 #define MAC_RCV_RULE_2 0x00000490 556 #define MAC_RCV_VALUE_2 0x00000494 557 #define MAC_RCV_RULE_3 0x00000498 558 #define MAC_RCV_VALUE_3 0x0000049c 559 #define MAC_RCV_RULE_4 0x000004a0 560 #define MAC_RCV_VALUE_4 0x000004a4 561 #define MAC_RCV_RULE_5 0x000004a8 562 #define MAC_RCV_VALUE_5 0x000004ac 563 #define MAC_RCV_RULE_6 0x000004b0 564 #define MAC_RCV_VALUE_6 0x000004b4 565 #define MAC_RCV_RULE_7 0x000004b8 566 #define MAC_RCV_VALUE_7 0x000004bc 567 #define MAC_RCV_RULE_8 0x000004c0 568 #define MAC_RCV_VALUE_8 0x000004c4 569 #define MAC_RCV_RULE_9 0x000004c8 570 #define MAC_RCV_VALUE_9 0x000004cc 571 #define MAC_RCV_RULE_10 0x000004d0 572 #define MAC_RCV_VALUE_10 0x000004d4 573 #define MAC_RCV_RULE_11 0x000004d8 574 #define MAC_RCV_VALUE_11 0x000004dc 575 #define MAC_RCV_RULE_12 0x000004e0 576 #define MAC_RCV_VALUE_12 0x000004e4 577 #define MAC_RCV_RULE_13 0x000004e8 578 #define MAC_RCV_VALUE_13 0x000004ec 579 #define MAC_RCV_RULE_14 0x000004f0 580 #define MAC_RCV_VALUE_14 0x000004f4 581 #define MAC_RCV_RULE_15 0x000004f8 582 #define MAC_RCV_VALUE_15 0x000004fc 583 #define RCV_RULE_DISABLE_MASK 0x7fffffff 584 #define MAC_RCV_RULE_CFG 0x00000500 585 #define RCV_RULE_CFG_DEFAULT_CLASS 0x00000008 586 #define MAC_LOW_WMARK_MAX_RX_FRAME 0x00000504 587 /* 0x508 --> 0x520 unused */ 588 #define MAC_HASHREGU_0 0x00000520 589 #define MAC_HASHREGU_1 0x00000524 590 #define MAC_HASHREGU_2 0x00000528 591 #define MAC_HASHREGU_3 0x0000052c 592 #define MAC_EXTADDR_0_HIGH 0x00000530 593 #define MAC_EXTADDR_0_LOW 0x00000534 594 #define MAC_EXTADDR_1_HIGH 0x00000538 595 #define MAC_EXTADDR_1_LOW 0x0000053c 596 #define MAC_EXTADDR_2_HIGH 0x00000540 597 #define MAC_EXTADDR_2_LOW 0x00000544 598 #define MAC_EXTADDR_3_HIGH 0x00000548 599 #define MAC_EXTADDR_3_LOW 0x0000054c 600 #define MAC_EXTADDR_4_HIGH 0x00000550 601 #define MAC_EXTADDR_4_LOW 0x00000554 602 #define MAC_EXTADDR_5_HIGH 0x00000558 603 #define MAC_EXTADDR_5_LOW 0x0000055c 604 #define MAC_EXTADDR_6_HIGH 0x00000560 605 #define MAC_EXTADDR_6_LOW 0x00000564 606 #define MAC_EXTADDR_7_HIGH 0x00000568 607 #define MAC_EXTADDR_7_LOW 0x0000056c 608 #define MAC_EXTADDR_8_HIGH 0x00000570 609 #define MAC_EXTADDR_8_LOW 0x00000574 610 #define MAC_EXTADDR_9_HIGH 0x00000578 611 #define MAC_EXTADDR_9_LOW 0x0000057c 612 #define MAC_EXTADDR_10_HIGH 0x00000580 613 #define MAC_EXTADDR_10_LOW 0x00000584 614 #define MAC_EXTADDR_11_HIGH 0x00000588 615 #define MAC_EXTADDR_11_LOW 0x0000058c 616 #define MAC_SERDES_CFG 0x00000590 617 #define MAC_SERDES_CFG_EDGE_SELECT 0x00001000 618 #define MAC_SERDES_STAT 0x00000594 619 /* 0x598 --> 0x5a0 unused */ 620 #define MAC_PHYCFG1 0x000005a0 621 #define MAC_PHYCFG1_RGMII_INT 0x00000001 622 #define MAC_PHYCFG1_RXCLK_TO_MASK 0x00001ff0 623 #define MAC_PHYCFG1_RXCLK_TIMEOUT 0x00001000 624 #define MAC_PHYCFG1_TXCLK_TO_MASK 0x01ff0000 625 #define MAC_PHYCFG1_TXCLK_TIMEOUT 0x01000000 626 #define MAC_PHYCFG1_RGMII_EXT_RX_DEC 0x02000000 627 #define MAC_PHYCFG1_RGMII_SND_STAT_EN 0x04000000 628 #define MAC_PHYCFG1_TXC_DRV 0x20000000 629 #define MAC_PHYCFG2 0x000005a4 630 #define MAC_PHYCFG2_INBAND_ENABLE 0x00000001 631 #define MAC_PHYCFG2_EMODE_MASK_MASK 0x000001c0 632 #define MAC_PHYCFG2_EMODE_MASK_AC131 0x000000c0 633 #define MAC_PHYCFG2_EMODE_MASK_50610 0x00000100 634 #define MAC_PHYCFG2_EMODE_MASK_RT8211 0x00000000 635 #define MAC_PHYCFG2_EMODE_MASK_RT8201 0x000001c0 636 #define MAC_PHYCFG2_EMODE_COMP_MASK 0x00000e00 637 #define MAC_PHYCFG2_EMODE_COMP_AC131 0x00000600 638 #define MAC_PHYCFG2_EMODE_COMP_50610 0x00000400 639 #define MAC_PHYCFG2_EMODE_COMP_RT8211 0x00000800 640 #define MAC_PHYCFG2_EMODE_COMP_RT8201 0x00000000 641 #define MAC_PHYCFG2_FMODE_MASK_MASK 0x00007000 642 #define MAC_PHYCFG2_FMODE_MASK_AC131 0x00006000 643 #define MAC_PHYCFG2_FMODE_MASK_50610 0x00004000 644 #define MAC_PHYCFG2_FMODE_MASK_RT8211 0x00000000 645 #define MAC_PHYCFG2_FMODE_MASK_RT8201 0x00007000 646 #define MAC_PHYCFG2_FMODE_COMP_MASK 0x00038000 647 #define MAC_PHYCFG2_FMODE_COMP_AC131 0x00030000 648 #define MAC_PHYCFG2_FMODE_COMP_50610 0x00008000 649 #define MAC_PHYCFG2_FMODE_COMP_RT8211 0x00038000 650 #define MAC_PHYCFG2_FMODE_COMP_RT8201 0x00000000 651 #define MAC_PHYCFG2_GMODE_MASK_MASK 0x001c0000 652 #define MAC_PHYCFG2_GMODE_MASK_AC131 0x001c0000 653 #define MAC_PHYCFG2_GMODE_MASK_50610 0x00100000 654 #define MAC_PHYCFG2_GMODE_MASK_RT8211 0x00000000 655 #define MAC_PHYCFG2_GMODE_MASK_RT8201 0x001c0000 656 #define MAC_PHYCFG2_GMODE_COMP_MASK 0x00e00000 657 #define MAC_PHYCFG2_GMODE_COMP_AC131 0x00e00000 658 #define MAC_PHYCFG2_GMODE_COMP_50610 0x00000000 659 #define MAC_PHYCFG2_GMODE_COMP_RT8211 0x00200000 660 #define MAC_PHYCFG2_GMODE_COMP_RT8201 0x00000000 661 #define MAC_PHYCFG2_ACT_MASK_MASK 0x03000000 662 #define MAC_PHYCFG2_ACT_MASK_AC131 0x03000000 663 #define MAC_PHYCFG2_ACT_MASK_50610 0x01000000 664 #define MAC_PHYCFG2_ACT_MASK_RT8211 0x03000000 665 #define MAC_PHYCFG2_ACT_MASK_RT8201 0x01000000 666 #define MAC_PHYCFG2_ACT_COMP_MASK 0x0c000000 667 #define MAC_PHYCFG2_ACT_COMP_AC131 0x00000000 668 #define MAC_PHYCFG2_ACT_COMP_50610 0x00000000 669 #define MAC_PHYCFG2_ACT_COMP_RT8211 0x00000000 670 #define MAC_PHYCFG2_ACT_COMP_RT8201 0x08000000 671 #define MAC_PHYCFG2_QUAL_MASK_MASK 0x30000000 672 #define MAC_PHYCFG2_QUAL_MASK_AC131 0x30000000 673 #define MAC_PHYCFG2_QUAL_MASK_50610 0x30000000 674 #define MAC_PHYCFG2_QUAL_MASK_RT8211 0x30000000 675 #define MAC_PHYCFG2_QUAL_MASK_RT8201 0x30000000 676 #define MAC_PHYCFG2_QUAL_COMP_MASK 0xc0000000 677 #define MAC_PHYCFG2_QUAL_COMP_AC131 0x00000000 678 #define MAC_PHYCFG2_QUAL_COMP_50610 0x00000000 679 #define MAC_PHYCFG2_QUAL_COMP_RT8211 0x00000000 680 #define MAC_PHYCFG2_QUAL_COMP_RT8201 0x00000000 681 #define MAC_PHYCFG2_50610_LED_MODES \ 682 (MAC_PHYCFG2_EMODE_MASK_50610 | \ 683 MAC_PHYCFG2_EMODE_COMP_50610 | \ 684 MAC_PHYCFG2_FMODE_MASK_50610 | \ 685 MAC_PHYCFG2_FMODE_COMP_50610 | \ 686 MAC_PHYCFG2_GMODE_MASK_50610 | \ 687 MAC_PHYCFG2_GMODE_COMP_50610 | \ 688 MAC_PHYCFG2_ACT_MASK_50610 | \ 689 MAC_PHYCFG2_ACT_COMP_50610 | \ 690 MAC_PHYCFG2_QUAL_MASK_50610 | \ 691 MAC_PHYCFG2_QUAL_COMP_50610) 692 #define MAC_PHYCFG2_AC131_LED_MODES \ 693 (MAC_PHYCFG2_EMODE_MASK_AC131 | \ 694 MAC_PHYCFG2_EMODE_COMP_AC131 | \ 695 MAC_PHYCFG2_FMODE_MASK_AC131 | \ 696 MAC_PHYCFG2_FMODE_COMP_AC131 | \ 697 MAC_PHYCFG2_GMODE_MASK_AC131 | \ 698 MAC_PHYCFG2_GMODE_COMP_AC131 | \ 699 MAC_PHYCFG2_ACT_MASK_AC131 | \ 700 MAC_PHYCFG2_ACT_COMP_AC131 | \ 701 MAC_PHYCFG2_QUAL_MASK_AC131 | \ 702 MAC_PHYCFG2_QUAL_COMP_AC131) 703 #define MAC_PHYCFG2_RTL8211C_LED_MODES \ 704 (MAC_PHYCFG2_EMODE_MASK_RT8211 | \ 705 MAC_PHYCFG2_EMODE_COMP_RT8211 | \ 706 MAC_PHYCFG2_FMODE_MASK_RT8211 | \ 707 MAC_PHYCFG2_FMODE_COMP_RT8211 | \ 708 MAC_PHYCFG2_GMODE_MASK_RT8211 | \ 709 MAC_PHYCFG2_GMODE_COMP_RT8211 | \ 710 MAC_PHYCFG2_ACT_MASK_RT8211 | \ 711 MAC_PHYCFG2_ACT_COMP_RT8211 | \ 712 MAC_PHYCFG2_QUAL_MASK_RT8211 | \ 713 MAC_PHYCFG2_QUAL_COMP_RT8211) 714 #define MAC_PHYCFG2_RTL8201E_LED_MODES \ 715 (MAC_PHYCFG2_EMODE_MASK_RT8201 | \ 716 MAC_PHYCFG2_EMODE_COMP_RT8201 | \ 717 MAC_PHYCFG2_FMODE_MASK_RT8201 | \ 718 MAC_PHYCFG2_FMODE_COMP_RT8201 | \ 719 MAC_PHYCFG2_GMODE_MASK_RT8201 | \ 720 MAC_PHYCFG2_GMODE_COMP_RT8201 | \ 721 MAC_PHYCFG2_ACT_MASK_RT8201 | \ 722 MAC_PHYCFG2_ACT_COMP_RT8201 | \ 723 MAC_PHYCFG2_QUAL_MASK_RT8201 | \ 724 MAC_PHYCFG2_QUAL_COMP_RT8201) 725 #define MAC_EXT_RGMII_MODE 0x000005a8 726 #define MAC_RGMII_MODE_TX_ENABLE 0x00000001 727 #define MAC_RGMII_MODE_TX_LOWPWR 0x00000002 728 #define MAC_RGMII_MODE_TX_RESET 0x00000004 729 #define MAC_RGMII_MODE_RX_INT_B 0x00000100 730 #define MAC_RGMII_MODE_RX_QUALITY 0x00000200 731 #define MAC_RGMII_MODE_RX_ACTIVITY 0x00000400 732 #define MAC_RGMII_MODE_RX_ENG_DET 0x00000800 733 /* 0x5ac --> 0x5b0 unused */ 734 #define SERDES_RX_CTRL 0x000005b0 /* 5780/5714 only */ 735 #define SERDES_RX_SIG_DETECT 0x00000400 736 #define SG_DIG_CTRL 0x000005b0 737 #define SG_DIG_USING_HW_AUTONEG 0x80000000 738 #define SG_DIG_SOFT_RESET 0x40000000 739 #define SG_DIG_DISABLE_LINKRDY 0x20000000 740 #define SG_DIG_CRC16_CLEAR_N 0x01000000 741 #define SG_DIG_EN10B 0x00800000 742 #define SG_DIG_CLEAR_STATUS 0x00400000 743 #define SG_DIG_LOCAL_DUPLEX_STATUS 0x00200000 744 #define SG_DIG_LOCAL_LINK_STATUS 0x00100000 745 #define SG_DIG_SPEED_STATUS_MASK 0x000c0000 746 #define SG_DIG_SPEED_STATUS_SHIFT 18 747 #define SG_DIG_JUMBO_PACKET_DISABLE 0x00020000 748 #define SG_DIG_RESTART_AUTONEG 0x00010000 749 #define SG_DIG_FIBER_MODE 0x00008000 750 #define SG_DIG_REMOTE_FAULT_MASK 0x00006000 751 #define SG_DIG_PAUSE_MASK 0x00001800 752 #define SG_DIG_PAUSE_CAP 0x00000800 753 #define SG_DIG_ASYM_PAUSE 0x00001000 754 #define SG_DIG_GBIC_ENABLE 0x00000400 755 #define SG_DIG_CHECK_END_ENABLE 0x00000200 756 #define SG_DIG_SGMII_AUTONEG_TIMER 0x00000100 757 #define SG_DIG_CLOCK_PHASE_SELECT 0x00000080 758 #define SG_DIG_GMII_INPUT_SELECT 0x00000040 759 #define SG_DIG_MRADV_CRC16_SELECT 0x00000020 760 #define SG_DIG_COMMA_DETECT_ENABLE 0x00000010 761 #define SG_DIG_AUTONEG_TIMER_REDUCE 0x00000008 762 #define SG_DIG_AUTONEG_LOW_ENABLE 0x00000004 763 #define SG_DIG_REMOTE_LOOPBACK 0x00000002 764 #define SG_DIG_LOOPBACK 0x00000001 765 #define SG_DIG_COMMON_SETUP (SG_DIG_CRC16_CLEAR_N | \ 766 SG_DIG_LOCAL_DUPLEX_STATUS | \ 767 SG_DIG_LOCAL_LINK_STATUS | \ 768 (0x2 << SG_DIG_SPEED_STATUS_SHIFT) | \ 769 SG_DIG_FIBER_MODE | SG_DIG_GBIC_ENABLE) 770 #define SG_DIG_STATUS 0x000005b4 771 #define SG_DIG_CRC16_BUS_MASK 0xffff0000 772 #define SG_DIG_PARTNER_FAULT_MASK 0x00600000 /* If !MRADV_CRC16_SELECT */ 773 #define SG_DIG_PARTNER_ASYM_PAUSE 0x00100000 /* If !MRADV_CRC16_SELECT */ 774 #define SG_DIG_PARTNER_PAUSE_CAPABLE 0x00080000 /* If !MRADV_CRC16_SELECT */ 775 #define SG_DIG_PARTNER_HALF_DUPLEX 0x00040000 /* If !MRADV_CRC16_SELECT */ 776 #define SG_DIG_PARTNER_FULL_DUPLEX 0x00020000 /* If !MRADV_CRC16_SELECT */ 777 #define SG_DIG_PARTNER_NEXT_PAGE 0x00010000 /* If !MRADV_CRC16_SELECT */ 778 #define SG_DIG_AUTONEG_STATE_MASK 0x00000ff0 779 #define SG_DIG_IS_SERDES 0x00000100 780 #define SG_DIG_COMMA_DETECTOR 0x00000008 781 #define SG_DIG_MAC_ACK_STATUS 0x00000004 782 #define SG_DIG_AUTONEG_COMPLETE 0x00000002 783 #define SG_DIG_AUTONEG_ERROR 0x00000001 784 #define TG3_TX_TSTAMP_LSB 0x000005c0 785 #define TG3_TX_TSTAMP_MSB 0x000005c4 786 #define TG3_TSTAMP_MASK 0x7fffffffffffffffLL 787 /* 0x5c8 --> 0x600 unused */ 788 #define MAC_TX_MAC_STATE_BASE 0x00000600 /* 16 bytes */ 789 #define MAC_RX_MAC_STATE_BASE 0x00000610 /* 20 bytes */ 790 /* 0x624 --> 0x670 unused */ 791 792 #define MAC_RSS_INDIR_TBL_0 0x00000630 793 794 #define MAC_RSS_HASH_KEY_0 0x00000670 795 #define MAC_RSS_HASH_KEY_1 0x00000674 796 #define MAC_RSS_HASH_KEY_2 0x00000678 797 #define MAC_RSS_HASH_KEY_3 0x0000067c 798 #define MAC_RSS_HASH_KEY_4 0x00000680 799 #define MAC_RSS_HASH_KEY_5 0x00000684 800 #define MAC_RSS_HASH_KEY_6 0x00000688 801 #define MAC_RSS_HASH_KEY_7 0x0000068c 802 #define MAC_RSS_HASH_KEY_8 0x00000690 803 #define MAC_RSS_HASH_KEY_9 0x00000694 804 /* 0x698 --> 0x6b0 unused */ 805 806 #define TG3_RX_TSTAMP_LSB 0x000006b0 807 #define TG3_RX_TSTAMP_MSB 0x000006b4 808 /* 0x6b8 --> 0x6c8 unused */ 809 810 #define TG3_RX_PTP_CTL 0x000006c8 811 #define TG3_RX_PTP_CTL_SYNC_EVNT 0x00000001 812 #define TG3_RX_PTP_CTL_DELAY_REQ 0x00000002 813 #define TG3_RX_PTP_CTL_PDLAY_REQ 0x00000004 814 #define TG3_RX_PTP_CTL_PDLAY_RES 0x00000008 815 #define TG3_RX_PTP_CTL_ALL_V1_EVENTS (TG3_RX_PTP_CTL_SYNC_EVNT | \ 816 TG3_RX_PTP_CTL_DELAY_REQ) 817 #define TG3_RX_PTP_CTL_ALL_V2_EVENTS (TG3_RX_PTP_CTL_SYNC_EVNT | \ 818 TG3_RX_PTP_CTL_DELAY_REQ | \ 819 TG3_RX_PTP_CTL_PDLAY_REQ | \ 820 TG3_RX_PTP_CTL_PDLAY_RES) 821 #define TG3_RX_PTP_CTL_FOLLOW_UP 0x00000100 822 #define TG3_RX_PTP_CTL_DELAY_RES 0x00000200 823 #define TG3_RX_PTP_CTL_PDRES_FLW_UP 0x00000400 824 #define TG3_RX_PTP_CTL_ANNOUNCE 0x00000800 825 #define TG3_RX_PTP_CTL_SIGNALING 0x00001000 826 #define TG3_RX_PTP_CTL_MANAGEMENT 0x00002000 827 #define TG3_RX_PTP_CTL_RX_PTP_V2_L2_EN 0x00800000 828 #define TG3_RX_PTP_CTL_RX_PTP_V2_L4_EN 0x01000000 829 #define TG3_RX_PTP_CTL_RX_PTP_V2_EN (TG3_RX_PTP_CTL_RX_PTP_V2_L2_EN | \ 830 TG3_RX_PTP_CTL_RX_PTP_V2_L4_EN) 831 #define TG3_RX_PTP_CTL_RX_PTP_V1_EN 0x02000000 832 #define TG3_RX_PTP_CTL_HWTS_INTERLOCK 0x04000000 833 /* 0x6cc --> 0x800 unused */ 834 835 #define MAC_TX_STATS_OCTETS 0x00000800 836 #define MAC_TX_STATS_RESV1 0x00000804 837 #define MAC_TX_STATS_COLLISIONS 0x00000808 838 #define MAC_TX_STATS_XON_SENT 0x0000080c 839 #define MAC_TX_STATS_XOFF_SENT 0x00000810 840 #define MAC_TX_STATS_RESV2 0x00000814 841 #define MAC_TX_STATS_MAC_ERRORS 0x00000818 842 #define MAC_TX_STATS_SINGLE_COLLISIONS 0x0000081c 843 #define MAC_TX_STATS_MULT_COLLISIONS 0x00000820 844 #define MAC_TX_STATS_DEFERRED 0x00000824 845 #define MAC_TX_STATS_RESV3 0x00000828 846 #define MAC_TX_STATS_EXCESSIVE_COL 0x0000082c 847 #define MAC_TX_STATS_LATE_COL 0x00000830 848 #define MAC_TX_STATS_RESV4_1 0x00000834 849 #define MAC_TX_STATS_RESV4_2 0x00000838 850 #define MAC_TX_STATS_RESV4_3 0x0000083c 851 #define MAC_TX_STATS_RESV4_4 0x00000840 852 #define MAC_TX_STATS_RESV4_5 0x00000844 853 #define MAC_TX_STATS_RESV4_6 0x00000848 854 #define MAC_TX_STATS_RESV4_7 0x0000084c 855 #define MAC_TX_STATS_RESV4_8 0x00000850 856 #define MAC_TX_STATS_RESV4_9 0x00000854 857 #define MAC_TX_STATS_RESV4_10 0x00000858 858 #define MAC_TX_STATS_RESV4_11 0x0000085c 859 #define MAC_TX_STATS_RESV4_12 0x00000860 860 #define MAC_TX_STATS_RESV4_13 0x00000864 861 #define MAC_TX_STATS_RESV4_14 0x00000868 862 #define MAC_TX_STATS_UCAST 0x0000086c 863 #define MAC_TX_STATS_MCAST 0x00000870 864 #define MAC_TX_STATS_BCAST 0x00000874 865 #define MAC_TX_STATS_RESV5_1 0x00000878 866 #define MAC_TX_STATS_RESV5_2 0x0000087c 867 #define MAC_RX_STATS_OCTETS 0x00000880 868 #define MAC_RX_STATS_RESV1 0x00000884 869 #define MAC_RX_STATS_FRAGMENTS 0x00000888 870 #define MAC_RX_STATS_UCAST 0x0000088c 871 #define MAC_RX_STATS_MCAST 0x00000890 872 #define MAC_RX_STATS_BCAST 0x00000894 873 #define MAC_RX_STATS_FCS_ERRORS 0x00000898 874 #define MAC_RX_STATS_ALIGN_ERRORS 0x0000089c 875 #define MAC_RX_STATS_XON_PAUSE_RECVD 0x000008a0 876 #define MAC_RX_STATS_XOFF_PAUSE_RECVD 0x000008a4 877 #define MAC_RX_STATS_MAC_CTRL_RECVD 0x000008a8 878 #define MAC_RX_STATS_XOFF_ENTERED 0x000008ac 879 #define MAC_RX_STATS_FRAME_TOO_LONG 0x000008b0 880 #define MAC_RX_STATS_JABBERS 0x000008b4 881 #define MAC_RX_STATS_UNDERSIZE 0x000008b8 882 /* 0x8bc --> 0xc00 unused */ 883 884 /* Send data initiator control registers */ 885 #define SNDDATAI_MODE 0x00000c00 886 #define SNDDATAI_MODE_RESET 0x00000001 887 #define SNDDATAI_MODE_ENABLE 0x00000002 888 #define SNDDATAI_MODE_STAT_OFLOW_ENAB 0x00000004 889 #define SNDDATAI_STATUS 0x00000c04 890 #define SNDDATAI_STATUS_STAT_OFLOW 0x00000004 891 #define SNDDATAI_STATSCTRL 0x00000c08 892 #define SNDDATAI_SCTRL_ENABLE 0x00000001 893 #define SNDDATAI_SCTRL_FASTUPD 0x00000002 894 #define SNDDATAI_SCTRL_CLEAR 0x00000004 895 #define SNDDATAI_SCTRL_FLUSH 0x00000008 896 #define SNDDATAI_SCTRL_FORCE_ZERO 0x00000010 897 #define SNDDATAI_STATSENAB 0x00000c0c 898 #define SNDDATAI_STATSINCMASK 0x00000c10 899 #define ISO_PKT_TX 0x00000c20 900 /* 0xc24 --> 0xc80 unused */ 901 #define SNDDATAI_COS_CNT_0 0x00000c80 902 #define SNDDATAI_COS_CNT_1 0x00000c84 903 #define SNDDATAI_COS_CNT_2 0x00000c88 904 #define SNDDATAI_COS_CNT_3 0x00000c8c 905 #define SNDDATAI_COS_CNT_4 0x00000c90 906 #define SNDDATAI_COS_CNT_5 0x00000c94 907 #define SNDDATAI_COS_CNT_6 0x00000c98 908 #define SNDDATAI_COS_CNT_7 0x00000c9c 909 #define SNDDATAI_COS_CNT_8 0x00000ca0 910 #define SNDDATAI_COS_CNT_9 0x00000ca4 911 #define SNDDATAI_COS_CNT_10 0x00000ca8 912 #define SNDDATAI_COS_CNT_11 0x00000cac 913 #define SNDDATAI_COS_CNT_12 0x00000cb0 914 #define SNDDATAI_COS_CNT_13 0x00000cb4 915 #define SNDDATAI_COS_CNT_14 0x00000cb8 916 #define SNDDATAI_COS_CNT_15 0x00000cbc 917 #define SNDDATAI_DMA_RDQ_FULL_CNT 0x00000cc0 918 #define SNDDATAI_DMA_PRIO_RDQ_FULL_CNT 0x00000cc4 919 #define SNDDATAI_SDCQ_FULL_CNT 0x00000cc8 920 #define SNDDATAI_NICRNG_SSND_PIDX_CNT 0x00000ccc 921 #define SNDDATAI_STATS_UPDATED_CNT 0x00000cd0 922 #define SNDDATAI_INTERRUPTS_CNT 0x00000cd4 923 #define SNDDATAI_AVOID_INTERRUPTS_CNT 0x00000cd8 924 #define SNDDATAI_SND_THRESH_HIT_CNT 0x00000cdc 925 /* 0xce0 --> 0x1000 unused */ 926 927 /* Send data completion control registers */ 928 #define SNDDATAC_MODE 0x00001000 929 #define SNDDATAC_MODE_RESET 0x00000001 930 #define SNDDATAC_MODE_ENABLE 0x00000002 931 #define SNDDATAC_MODE_CDELAY 0x00000010 932 /* 0x1004 --> 0x1400 unused */ 933 934 /* Send BD ring selector */ 935 #define SNDBDS_MODE 0x00001400 936 #define SNDBDS_MODE_RESET 0x00000001 937 #define SNDBDS_MODE_ENABLE 0x00000002 938 #define SNDBDS_MODE_ATTN_ENABLE 0x00000004 939 #define SNDBDS_STATUS 0x00001404 940 #define SNDBDS_STATUS_ERROR_ATTN 0x00000004 941 #define SNDBDS_HWDIAG 0x00001408 942 /* 0x140c --> 0x1440 */ 943 #define SNDBDS_SEL_CON_IDX_0 0x00001440 944 #define SNDBDS_SEL_CON_IDX_1 0x00001444 945 #define SNDBDS_SEL_CON_IDX_2 0x00001448 946 #define SNDBDS_SEL_CON_IDX_3 0x0000144c 947 #define SNDBDS_SEL_CON_IDX_4 0x00001450 948 #define SNDBDS_SEL_CON_IDX_5 0x00001454 949 #define SNDBDS_SEL_CON_IDX_6 0x00001458 950 #define SNDBDS_SEL_CON_IDX_7 0x0000145c 951 #define SNDBDS_SEL_CON_IDX_8 0x00001460 952 #define SNDBDS_SEL_CON_IDX_9 0x00001464 953 #define SNDBDS_SEL_CON_IDX_10 0x00001468 954 #define SNDBDS_SEL_CON_IDX_11 0x0000146c 955 #define SNDBDS_SEL_CON_IDX_12 0x00001470 956 #define SNDBDS_SEL_CON_IDX_13 0x00001474 957 #define SNDBDS_SEL_CON_IDX_14 0x00001478 958 #define SNDBDS_SEL_CON_IDX_15 0x0000147c 959 /* 0x1480 --> 0x1800 unused */ 960 961 /* Send BD initiator control registers */ 962 #define SNDBDI_MODE 0x00001800 963 #define SNDBDI_MODE_RESET 0x00000001 964 #define SNDBDI_MODE_ENABLE 0x00000002 965 #define SNDBDI_MODE_ATTN_ENABLE 0x00000004 966 #define SNDBDI_MODE_MULTI_TXQ_EN 0x00000020 967 #define SNDBDI_STATUS 0x00001804 968 #define SNDBDI_STATUS_ERROR_ATTN 0x00000004 969 #define SNDBDI_IN_PROD_IDX_0 0x00001808 970 #define SNDBDI_IN_PROD_IDX_1 0x0000180c 971 #define SNDBDI_IN_PROD_IDX_2 0x00001810 972 #define SNDBDI_IN_PROD_IDX_3 0x00001814 973 #define SNDBDI_IN_PROD_IDX_4 0x00001818 974 #define SNDBDI_IN_PROD_IDX_5 0x0000181c 975 #define SNDBDI_IN_PROD_IDX_6 0x00001820 976 #define SNDBDI_IN_PROD_IDX_7 0x00001824 977 #define SNDBDI_IN_PROD_IDX_8 0x00001828 978 #define SNDBDI_IN_PROD_IDX_9 0x0000182c 979 #define SNDBDI_IN_PROD_IDX_10 0x00001830 980 #define SNDBDI_IN_PROD_IDX_11 0x00001834 981 #define SNDBDI_IN_PROD_IDX_12 0x00001838 982 #define SNDBDI_IN_PROD_IDX_13 0x0000183c 983 #define SNDBDI_IN_PROD_IDX_14 0x00001840 984 #define SNDBDI_IN_PROD_IDX_15 0x00001844 985 /* 0x1848 --> 0x1c00 unused */ 986 987 /* Send BD completion control registers */ 988 #define SNDBDC_MODE 0x00001c00 989 #define SNDBDC_MODE_RESET 0x00000001 990 #define SNDBDC_MODE_ENABLE 0x00000002 991 #define SNDBDC_MODE_ATTN_ENABLE 0x00000004 992 /* 0x1c04 --> 0x2000 unused */ 993 994 /* Receive list placement control registers */ 995 #define RCVLPC_MODE 0x00002000 996 #define RCVLPC_MODE_RESET 0x00000001 997 #define RCVLPC_MODE_ENABLE 0x00000002 998 #define RCVLPC_MODE_CLASS0_ATTN_ENAB 0x00000004 999 #define RCVLPC_MODE_MAPOOR_AATTN_ENAB 0x00000008 1000 #define RCVLPC_MODE_STAT_OFLOW_ENAB 0x00000010 1001 #define RCVLPC_STATUS 0x00002004 1002 #define RCVLPC_STATUS_CLASS0 0x00000004 1003 #define RCVLPC_STATUS_MAPOOR 0x00000008 1004 #define RCVLPC_STATUS_STAT_OFLOW 0x00000010 1005 #define RCVLPC_LOCK 0x00002008 1006 #define RCVLPC_LOCK_REQ_MASK 0x0000ffff 1007 #define RCVLPC_LOCK_REQ_SHIFT 0 1008 #define RCVLPC_LOCK_GRANT_MASK 0xffff0000 1009 #define RCVLPC_LOCK_GRANT_SHIFT 16 1010 #define RCVLPC_NON_EMPTY_BITS 0x0000200c 1011 #define RCVLPC_NON_EMPTY_BITS_MASK 0x0000ffff 1012 #define RCVLPC_CONFIG 0x00002010 1013 #define RCVLPC_STATSCTRL 0x00002014 1014 #define RCVLPC_STATSCTRL_ENABLE 0x00000001 1015 #define RCVLPC_STATSCTRL_FASTUPD 0x00000002 1016 #define RCVLPC_STATS_ENABLE 0x00002018 1017 #define RCVLPC_STATSENAB_ASF_FIX 0x00000002 1018 #define RCVLPC_STATSENAB_DACK_FIX 0x00040000 1019 #define RCVLPC_STATSENAB_LNGBRST_RFIX 0x00400000 1020 #define RCVLPC_STATS_INCMASK 0x0000201c 1021 /* 0x2020 --> 0x2100 unused */ 1022 #define RCVLPC_SELLST_BASE 0x00002100 /* 16 16-byte entries */ 1023 #define SELLST_TAIL 0x00000004 1024 #define SELLST_CONT 0x00000008 1025 #define SELLST_UNUSED 0x0000000c 1026 #define RCVLPC_COS_CNTL_BASE 0x00002200 /* 16 4-byte entries */ 1027 #define RCVLPC_DROP_FILTER_CNT 0x00002240 1028 #define RCVLPC_DMA_WQ_FULL_CNT 0x00002244 1029 #define RCVLPC_DMA_HIPRIO_WQ_FULL_CNT 0x00002248 1030 #define RCVLPC_NO_RCV_BD_CNT 0x0000224c 1031 #define RCVLPC_IN_DISCARDS_CNT 0x00002250 1032 #define RCVLPC_IN_ERRORS_CNT 0x00002254 1033 #define RCVLPC_RCV_THRESH_HIT_CNT 0x00002258 1034 /* 0x225c --> 0x2400 unused */ 1035 1036 /* Receive Data and Receive BD Initiator Control */ 1037 #define RCVDBDI_MODE 0x00002400 1038 #define RCVDBDI_MODE_RESET 0x00000001 1039 #define RCVDBDI_MODE_ENABLE 0x00000002 1040 #define RCVDBDI_MODE_JUMBOBD_NEEDED 0x00000004 1041 #define RCVDBDI_MODE_FRM_TOO_BIG 0x00000008 1042 #define RCVDBDI_MODE_INV_RING_SZ 0x00000010 1043 #define RCVDBDI_MODE_LRG_RING_SZ 0x00010000 1044 #define RCVDBDI_STATUS 0x00002404 1045 #define RCVDBDI_STATUS_JUMBOBD_NEEDED 0x00000004 1046 #define RCVDBDI_STATUS_FRM_TOO_BIG 0x00000008 1047 #define RCVDBDI_STATUS_INV_RING_SZ 0x00000010 1048 #define RCVDBDI_SPLIT_FRAME_MINSZ 0x00002408 1049 /* 0x240c --> 0x2440 unused */ 1050 #define RCVDBDI_JUMBO_BD 0x00002440 /* TG3_BDINFO_... */ 1051 #define RCVDBDI_STD_BD 0x00002450 /* TG3_BDINFO_... */ 1052 #define RCVDBDI_MINI_BD 0x00002460 /* TG3_BDINFO_... */ 1053 #define RCVDBDI_JUMBO_CON_IDX 0x00002470 1054 #define RCVDBDI_STD_CON_IDX 0x00002474 1055 #define RCVDBDI_MINI_CON_IDX 0x00002478 1056 /* 0x247c --> 0x2480 unused */ 1057 #define RCVDBDI_BD_PROD_IDX_0 0x00002480 1058 #define RCVDBDI_BD_PROD_IDX_1 0x00002484 1059 #define RCVDBDI_BD_PROD_IDX_2 0x00002488 1060 #define RCVDBDI_BD_PROD_IDX_3 0x0000248c 1061 #define RCVDBDI_BD_PROD_IDX_4 0x00002490 1062 #define RCVDBDI_BD_PROD_IDX_5 0x00002494 1063 #define RCVDBDI_BD_PROD_IDX_6 0x00002498 1064 #define RCVDBDI_BD_PROD_IDX_7 0x0000249c 1065 #define RCVDBDI_BD_PROD_IDX_8 0x000024a0 1066 #define RCVDBDI_BD_PROD_IDX_9 0x000024a4 1067 #define RCVDBDI_BD_PROD_IDX_10 0x000024a8 1068 #define RCVDBDI_BD_PROD_IDX_11 0x000024ac 1069 #define RCVDBDI_BD_PROD_IDX_12 0x000024b0 1070 #define RCVDBDI_BD_PROD_IDX_13 0x000024b4 1071 #define RCVDBDI_BD_PROD_IDX_14 0x000024b8 1072 #define RCVDBDI_BD_PROD_IDX_15 0x000024bc 1073 #define RCVDBDI_HWDIAG 0x000024c0 1074 /* 0x24c4 --> 0x2800 unused */ 1075 1076 /* Receive Data Completion Control */ 1077 #define RCVDCC_MODE 0x00002800 1078 #define RCVDCC_MODE_RESET 0x00000001 1079 #define RCVDCC_MODE_ENABLE 0x00000002 1080 #define RCVDCC_MODE_ATTN_ENABLE 0x00000004 1081 /* 0x2804 --> 0x2c00 unused */ 1082 1083 /* Receive BD Initiator Control Registers */ 1084 #define RCVBDI_MODE 0x00002c00 1085 #define RCVBDI_MODE_RESET 0x00000001 1086 #define RCVBDI_MODE_ENABLE 0x00000002 1087 #define RCVBDI_MODE_RCB_ATTN_ENAB 0x00000004 1088 #define RCVBDI_STATUS 0x00002c04 1089 #define RCVBDI_STATUS_RCB_ATTN 0x00000004 1090 #define RCVBDI_JUMBO_PROD_IDX 0x00002c08 1091 #define RCVBDI_STD_PROD_IDX 0x00002c0c 1092 #define RCVBDI_MINI_PROD_IDX 0x00002c10 1093 #define RCVBDI_MINI_THRESH 0x00002c14 1094 #define RCVBDI_STD_THRESH 0x00002c18 1095 #define RCVBDI_JUMBO_THRESH 0x00002c1c 1096 /* 0x2c20 --> 0x2d00 unused */ 1097 1098 #define STD_REPLENISH_LWM 0x00002d00 1099 #define JMB_REPLENISH_LWM 0x00002d04 1100 /* 0x2d08 --> 0x3000 unused */ 1101 1102 /* Receive BD Completion Control Registers */ 1103 #define RCVCC_MODE 0x00003000 1104 #define RCVCC_MODE_RESET 0x00000001 1105 #define RCVCC_MODE_ENABLE 0x00000002 1106 #define RCVCC_MODE_ATTN_ENABLE 0x00000004 1107 #define RCVCC_STATUS 0x00003004 1108 #define RCVCC_STATUS_ERROR_ATTN 0x00000004 1109 #define RCVCC_JUMP_PROD_IDX 0x00003008 1110 #define RCVCC_STD_PROD_IDX 0x0000300c 1111 #define RCVCC_MINI_PROD_IDX 0x00003010 1112 /* 0x3014 --> 0x3400 unused */ 1113 1114 /* Receive list selector control registers */ 1115 #define RCVLSC_MODE 0x00003400 1116 #define RCVLSC_MODE_RESET 0x00000001 1117 #define RCVLSC_MODE_ENABLE 0x00000002 1118 #define RCVLSC_MODE_ATTN_ENABLE 0x00000004 1119 #define RCVLSC_STATUS 0x00003404 1120 #define RCVLSC_STATUS_ERROR_ATTN 0x00000004 1121 /* 0x3408 --> 0x3600 unused */ 1122 1123 #define TG3_CPMU_DRV_STATUS 0x0000344c 1124 1125 /* CPMU registers */ 1126 #define TG3_CPMU_CTRL 0x00003600 1127 #define CPMU_CTRL_LINK_IDLE_MODE 0x00000200 1128 #define CPMU_CTRL_LINK_AWARE_MODE 0x00000400 1129 #define CPMU_CTRL_LINK_SPEED_MODE 0x00004000 1130 #define CPMU_CTRL_GPHY_10MB_RXONLY 0x00010000 1131 #define TG3_CPMU_LSPD_10MB_CLK 0x00003604 1132 #define CPMU_LSPD_10MB_MACCLK_MASK 0x001f0000 1133 #define CPMU_LSPD_10MB_MACCLK_6_25 0x00130000 1134 /* 0x3608 --> 0x360c unused */ 1135 1136 #define TG3_CPMU_LSPD_1000MB_CLK 0x0000360c 1137 #define CPMU_LSPD_1000MB_MACCLK_62_5 0x00000000 1138 #define CPMU_LSPD_1000MB_MACCLK_12_5 0x00110000 1139 #define CPMU_LSPD_1000MB_MACCLK_MASK 0x001f0000 1140 #define TG3_CPMU_LNK_AWARE_PWRMD 0x00003610 1141 #define CPMU_LNK_AWARE_MACCLK_MASK 0x001f0000 1142 #define CPMU_LNK_AWARE_MACCLK_6_25 0x00130000 1143 /* 0x3614 --> 0x361c unused */ 1144 1145 #define TG3_CPMU_HST_ACC 0x0000361c 1146 #define CPMU_HST_ACC_MACCLK_MASK 0x001f0000 1147 #define CPMU_HST_ACC_MACCLK_6_25 0x00130000 1148 /* 0x3620 --> 0x3630 unused */ 1149 1150 #define TG3_CPMU_CLCK_ORIDE 0x00003624 1151 #define CPMU_CLCK_ORIDE_MAC_ORIDE_EN 0x80000000 1152 1153 #define TG3_CPMU_CLCK_ORIDE_ENABLE 0x00003628 1154 #define TG3_CPMU_MAC_ORIDE_ENABLE (1 << 13) 1155 1156 #define TG3_CPMU_STATUS 0x0000362c 1157 #define TG3_CPMU_STATUS_FMSK_5717 0x20000000 1158 #define TG3_CPMU_STATUS_FMSK_5719 0xc0000000 1159 #define TG3_CPMU_STATUS_FSHFT_5719 30 1160 #define TG3_CPMU_STATUS_LINK_MASK 0x180000 1161 1162 #define TG3_CPMU_CLCK_STAT 0x00003630 1163 #define CPMU_CLCK_STAT_MAC_CLCK_MASK 0x001f0000 1164 #define CPMU_CLCK_STAT_MAC_CLCK_62_5 0x00000000 1165 #define CPMU_CLCK_STAT_MAC_CLCK_12_5 0x00110000 1166 #define CPMU_CLCK_STAT_MAC_CLCK_6_25 0x00130000 1167 /* 0x3634 --> 0x365c unused */ 1168 1169 #define TG3_CPMU_MUTEX_REQ 0x0000365c 1170 #define CPMU_MUTEX_REQ_DRIVER 0x00001000 1171 #define TG3_CPMU_MUTEX_GNT 0x00003660 1172 #define CPMU_MUTEX_GNT_DRIVER 0x00001000 1173 #define TG3_CPMU_PHY_STRAP 0x00003664 1174 #define TG3_CPMU_PHY_STRAP_IS_SERDES 0x00000020 1175 #define TG3_CPMU_PADRNG_CTL 0x00003668 1176 #define TG3_CPMU_PADRNG_CTL_RDIV2 0x00040000 1177 /* 0x3664 --> 0x36b0 unused */ 1178 1179 #define TG3_CPMU_EEE_MODE 0x000036b0 1180 #define TG3_CPMU_EEEMD_APE_TX_DET_EN 0x00000004 1181 #define TG3_CPMU_EEEMD_ERLY_L1_XIT_DET 0x00000008 1182 #define TG3_CPMU_EEEMD_SND_IDX_DET_EN 0x00000040 1183 #define TG3_CPMU_EEEMD_LPI_ENABLE 0x00000080 1184 #define TG3_CPMU_EEEMD_LPI_IN_TX 0x00000100 1185 #define TG3_CPMU_EEEMD_LPI_IN_RX 0x00000200 1186 #define TG3_CPMU_EEEMD_EEE_ENABLE 0x00100000 1187 #define TG3_CPMU_EEE_DBTMR1 0x000036b4 1188 #define TG3_CPMU_DBTMR1_PCIEXIT_2047US 0x07ff0000 1189 #define TG3_CPMU_DBTMR1_LNKIDLE_2047US 0x000007ff 1190 #define TG3_CPMU_DBTMR1_LNKIDLE_MAX 0x0000ffff 1191 #define TG3_CPMU_EEE_DBTMR2 0x000036b8 1192 #define TG3_CPMU_DBTMR2_APE_TX_2047US 0x07ff0000 1193 #define TG3_CPMU_DBTMR2_TXIDXEQ_2047US 0x000007ff 1194 #define TG3_CPMU_EEE_LNKIDL_CTRL 0x000036bc 1195 #define TG3_CPMU_EEE_LNKIDL_PCIE_NL0 0x01000000 1196 #define TG3_CPMU_EEE_LNKIDL_UART_IDL 0x00000004 1197 #define TG3_CPMU_EEE_LNKIDL_APE_TX_MT 0x00000002 1198 /* 0x36c0 --> 0x36d0 unused */ 1199 1200 #define TG3_CPMU_EEE_CTRL 0x000036d0 1201 #define TG3_CPMU_EEE_CTRL_EXIT_16_5_US 0x0000019d 1202 #define TG3_CPMU_EEE_CTRL_EXIT_36_US 0x00000384 1203 #define TG3_CPMU_EEE_CTRL_EXIT_20_1_US 0x000001f8 1204 /* 0x36d4 --> 0x3800 unused */ 1205 1206 /* Mbuf cluster free registers */ 1207 #define MBFREE_MODE 0x00003800 1208 #define MBFREE_MODE_RESET 0x00000001 1209 #define MBFREE_MODE_ENABLE 0x00000002 1210 #define MBFREE_STATUS 0x00003804 1211 /* 0x3808 --> 0x3c00 unused */ 1212 1213 /* Host coalescing control registers */ 1214 #define HOSTCC_MODE 0x00003c00 1215 #define HOSTCC_MODE_RESET 0x00000001 1216 #define HOSTCC_MODE_ENABLE 0x00000002 1217 #define HOSTCC_MODE_ATTN 0x00000004 1218 #define HOSTCC_MODE_NOW 0x00000008 1219 #define HOSTCC_MODE_FULL_STATUS 0x00000000 1220 #define HOSTCC_MODE_64BYTE 0x00000080 1221 #define HOSTCC_MODE_32BYTE 0x00000100 1222 #define HOSTCC_MODE_CLRTICK_RXBD 0x00000200 1223 #define HOSTCC_MODE_CLRTICK_TXBD 0x00000400 1224 #define HOSTCC_MODE_NOINT_ON_NOW 0x00000800 1225 #define HOSTCC_MODE_NOINT_ON_FORCE 0x00001000 1226 #define HOSTCC_MODE_COAL_VEC1_NOW 0x00002000 1227 #define HOSTCC_STATUS 0x00003c04 1228 #define HOSTCC_STATUS_ERROR_ATTN 0x00000004 1229 #define HOSTCC_RXCOL_TICKS 0x00003c08 1230 #define LOW_RXCOL_TICKS 0x00000032 1231 #define LOW_RXCOL_TICKS_CLRTCKS 0x00000014 1232 #define DEFAULT_RXCOL_TICKS 0x00000048 1233 #define HIGH_RXCOL_TICKS 0x00000096 1234 #define MAX_RXCOL_TICKS 0x000003ff 1235 #define HOSTCC_TXCOL_TICKS 0x00003c0c 1236 #define LOW_TXCOL_TICKS 0x00000096 1237 #define LOW_TXCOL_TICKS_CLRTCKS 0x00000048 1238 #define DEFAULT_TXCOL_TICKS 0x0000012c 1239 #define HIGH_TXCOL_TICKS 0x00000145 1240 #define MAX_TXCOL_TICKS 0x000003ff 1241 #define HOSTCC_RXMAX_FRAMES 0x00003c10 1242 #define LOW_RXMAX_FRAMES 0x00000005 1243 #define DEFAULT_RXMAX_FRAMES 0x00000008 1244 #define HIGH_RXMAX_FRAMES 0x00000012 1245 #define MAX_RXMAX_FRAMES 0x000000ff 1246 #define HOSTCC_TXMAX_FRAMES 0x00003c14 1247 #define LOW_TXMAX_FRAMES 0x00000035 1248 #define DEFAULT_TXMAX_FRAMES 0x0000004b 1249 #define HIGH_TXMAX_FRAMES 0x00000052 1250 #define MAX_TXMAX_FRAMES 0x000000ff 1251 #define HOSTCC_RXCOAL_TICK_INT 0x00003c18 1252 #define DEFAULT_RXCOAL_TICK_INT 0x00000019 1253 #define DEFAULT_RXCOAL_TICK_INT_CLRTCKS 0x00000014 1254 #define MAX_RXCOAL_TICK_INT 0x000003ff 1255 #define HOSTCC_TXCOAL_TICK_INT 0x00003c1c 1256 #define DEFAULT_TXCOAL_TICK_INT 0x00000019 1257 #define DEFAULT_TXCOAL_TICK_INT_CLRTCKS 0x00000014 1258 #define MAX_TXCOAL_TICK_INT 0x000003ff 1259 #define HOSTCC_RXCOAL_MAXF_INT 0x00003c20 1260 #define DEFAULT_RXCOAL_MAXF_INT 0x00000005 1261 #define MAX_RXCOAL_MAXF_INT 0x000000ff 1262 #define HOSTCC_TXCOAL_MAXF_INT 0x00003c24 1263 #define DEFAULT_TXCOAL_MAXF_INT 0x00000005 1264 #define MAX_TXCOAL_MAXF_INT 0x000000ff 1265 #define HOSTCC_STAT_COAL_TICKS 0x00003c28 1266 #define DEFAULT_STAT_COAL_TICKS 0x000f4240 1267 #define MAX_STAT_COAL_TICKS 0xd693d400 1268 #define MIN_STAT_COAL_TICKS 0x00000064 1269 /* 0x3c2c --> 0x3c30 unused */ 1270 #define HOSTCC_STATS_BLK_HOST_ADDR 0x00003c30 /* 64-bit */ 1271 #define HOSTCC_STATUS_BLK_HOST_ADDR 0x00003c38 /* 64-bit */ 1272 #define HOSTCC_STATS_BLK_NIC_ADDR 0x00003c40 1273 #define HOSTCC_STATUS_BLK_NIC_ADDR 0x00003c44 1274 #define HOSTCC_FLOW_ATTN 0x00003c48 1275 #define HOSTCC_FLOW_ATTN_MBUF_LWM 0x00000040 1276 /* 0x3c4c --> 0x3c50 unused */ 1277 #define HOSTCC_JUMBO_CON_IDX 0x00003c50 1278 #define HOSTCC_STD_CON_IDX 0x00003c54 1279 #define HOSTCC_MINI_CON_IDX 0x00003c58 1280 /* 0x3c5c --> 0x3c80 unused */ 1281 #define HOSTCC_RET_PROD_IDX_0 0x00003c80 1282 #define HOSTCC_RET_PROD_IDX_1 0x00003c84 1283 #define HOSTCC_RET_PROD_IDX_2 0x00003c88 1284 #define HOSTCC_RET_PROD_IDX_3 0x00003c8c 1285 #define HOSTCC_RET_PROD_IDX_4 0x00003c90 1286 #define HOSTCC_RET_PROD_IDX_5 0x00003c94 1287 #define HOSTCC_RET_PROD_IDX_6 0x00003c98 1288 #define HOSTCC_RET_PROD_IDX_7 0x00003c9c 1289 #define HOSTCC_RET_PROD_IDX_8 0x00003ca0 1290 #define HOSTCC_RET_PROD_IDX_9 0x00003ca4 1291 #define HOSTCC_RET_PROD_IDX_10 0x00003ca8 1292 #define HOSTCC_RET_PROD_IDX_11 0x00003cac 1293 #define HOSTCC_RET_PROD_IDX_12 0x00003cb0 1294 #define HOSTCC_RET_PROD_IDX_13 0x00003cb4 1295 #define HOSTCC_RET_PROD_IDX_14 0x00003cb8 1296 #define HOSTCC_RET_PROD_IDX_15 0x00003cbc 1297 #define HOSTCC_SND_CON_IDX_0 0x00003cc0 1298 #define HOSTCC_SND_CON_IDX_1 0x00003cc4 1299 #define HOSTCC_SND_CON_IDX_2 0x00003cc8 1300 #define HOSTCC_SND_CON_IDX_3 0x00003ccc 1301 #define HOSTCC_SND_CON_IDX_4 0x00003cd0 1302 #define HOSTCC_SND_CON_IDX_5 0x00003cd4 1303 #define HOSTCC_SND_CON_IDX_6 0x00003cd8 1304 #define HOSTCC_SND_CON_IDX_7 0x00003cdc 1305 #define HOSTCC_SND_CON_IDX_8 0x00003ce0 1306 #define HOSTCC_SND_CON_IDX_9 0x00003ce4 1307 #define HOSTCC_SND_CON_IDX_10 0x00003ce8 1308 #define HOSTCC_SND_CON_IDX_11 0x00003cec 1309 #define HOSTCC_SND_CON_IDX_12 0x00003cf0 1310 #define HOSTCC_SND_CON_IDX_13 0x00003cf4 1311 #define HOSTCC_SND_CON_IDX_14 0x00003cf8 1312 #define HOSTCC_SND_CON_IDX_15 0x00003cfc 1313 #define HOSTCC_STATBLCK_RING1 0x00003d00 1314 /* 0x3d00 --> 0x3d80 unused */ 1315 1316 #define HOSTCC_RXCOL_TICKS_VEC1 0x00003d80 1317 #define HOSTCC_TXCOL_TICKS_VEC1 0x00003d84 1318 #define HOSTCC_RXMAX_FRAMES_VEC1 0x00003d88 1319 #define HOSTCC_TXMAX_FRAMES_VEC1 0x00003d8c 1320 #define HOSTCC_RXCOAL_MAXF_INT_VEC1 0x00003d90 1321 #define HOSTCC_TXCOAL_MAXF_INT_VEC1 0x00003d94 1322 /* 0x3d98 --> 0x4000 unused */ 1323 1324 /* Memory arbiter control registers */ 1325 #define MEMARB_MODE 0x00004000 1326 #define MEMARB_MODE_RESET 0x00000001 1327 #define MEMARB_MODE_ENABLE 0x00000002 1328 #define MEMARB_STATUS 0x00004004 1329 #define MEMARB_TRAP_ADDR_LOW 0x00004008 1330 #define MEMARB_TRAP_ADDR_HIGH 0x0000400c 1331 /* 0x4010 --> 0x4400 unused */ 1332 1333 /* Buffer manager control registers */ 1334 #define BUFMGR_MODE 0x00004400 1335 #define BUFMGR_MODE_RESET 0x00000001 1336 #define BUFMGR_MODE_ENABLE 0x00000002 1337 #define BUFMGR_MODE_ATTN_ENABLE 0x00000004 1338 #define BUFMGR_MODE_BM_TEST 0x00000008 1339 #define BUFMGR_MODE_MBLOW_ATTN_ENAB 0x00000010 1340 #define BUFMGR_MODE_NO_TX_UNDERRUN 0x80000000 1341 #define BUFMGR_STATUS 0x00004404 1342 #define BUFMGR_STATUS_ERROR 0x00000004 1343 #define BUFMGR_STATUS_MBLOW 0x00000010 1344 #define BUFMGR_MB_POOL_ADDR 0x00004408 1345 #define BUFMGR_MB_POOL_SIZE 0x0000440c 1346 #define BUFMGR_MB_RDMA_LOW_WATER 0x00004410 1347 #define DEFAULT_MB_RDMA_LOW_WATER 0x00000050 1348 #define DEFAULT_MB_RDMA_LOW_WATER_5705 0x00000000 1349 #define DEFAULT_MB_RDMA_LOW_WATER_JUMBO 0x00000130 1350 #define DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780 0x00000000 1351 #define BUFMGR_MB_MACRX_LOW_WATER 0x00004414 1352 #define DEFAULT_MB_MACRX_LOW_WATER 0x00000020 1353 #define DEFAULT_MB_MACRX_LOW_WATER_5705 0x00000010 1354 #define DEFAULT_MB_MACRX_LOW_WATER_5906 0x00000004 1355 #define DEFAULT_MB_MACRX_LOW_WATER_57765 0x0000002a 1356 #define DEFAULT_MB_MACRX_LOW_WATER_JUMBO 0x00000098 1357 #define DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780 0x0000004b 1358 #define DEFAULT_MB_MACRX_LOW_WATER_JUMBO_57765 0x0000007e 1359 #define BUFMGR_MB_HIGH_WATER 0x00004418 1360 #define DEFAULT_MB_HIGH_WATER 0x00000060 1361 #define DEFAULT_MB_HIGH_WATER_5705 0x00000060 1362 #define DEFAULT_MB_HIGH_WATER_5906 0x00000010 1363 #define DEFAULT_MB_HIGH_WATER_57765 0x000000a0 1364 #define DEFAULT_MB_HIGH_WATER_JUMBO 0x0000017c 1365 #define DEFAULT_MB_HIGH_WATER_JUMBO_5780 0x00000096 1366 #define DEFAULT_MB_HIGH_WATER_JUMBO_57765 0x000000ea 1367 #define BUFMGR_RX_MB_ALLOC_REQ 0x0000441c 1368 #define BUFMGR_MB_ALLOC_BIT 0x10000000 1369 #define BUFMGR_RX_MB_ALLOC_RESP 0x00004420 1370 #define BUFMGR_TX_MB_ALLOC_REQ 0x00004424 1371 #define BUFMGR_TX_MB_ALLOC_RESP 0x00004428 1372 #define BUFMGR_DMA_DESC_POOL_ADDR 0x0000442c 1373 #define BUFMGR_DMA_DESC_POOL_SIZE 0x00004430 1374 #define BUFMGR_DMA_LOW_WATER 0x00004434 1375 #define DEFAULT_DMA_LOW_WATER 0x00000005 1376 #define BUFMGR_DMA_HIGH_WATER 0x00004438 1377 #define DEFAULT_DMA_HIGH_WATER 0x0000000a 1378 #define BUFMGR_RX_DMA_ALLOC_REQ 0x0000443c 1379 #define BUFMGR_RX_DMA_ALLOC_RESP 0x00004440 1380 #define BUFMGR_TX_DMA_ALLOC_REQ 0x00004444 1381 #define BUFMGR_TX_DMA_ALLOC_RESP 0x00004448 1382 #define BUFMGR_HWDIAG_0 0x0000444c 1383 #define BUFMGR_HWDIAG_1 0x00004450 1384 #define BUFMGR_HWDIAG_2 0x00004454 1385 /* 0x4458 --> 0x4800 unused */ 1386 1387 /* Read DMA control registers */ 1388 #define RDMAC_MODE 0x00004800 1389 #define RDMAC_MODE_RESET 0x00000001 1390 #define RDMAC_MODE_ENABLE 0x00000002 1391 #define RDMAC_MODE_TGTABORT_ENAB 0x00000004 1392 #define RDMAC_MODE_MSTABORT_ENAB 0x00000008 1393 #define RDMAC_MODE_PARITYERR_ENAB 0x00000010 1394 #define RDMAC_MODE_ADDROFLOW_ENAB 0x00000020 1395 #define RDMAC_MODE_FIFOOFLOW_ENAB 0x00000040 1396 #define RDMAC_MODE_FIFOURUN_ENAB 0x00000080 1397 #define RDMAC_MODE_FIFOOREAD_ENAB 0x00000100 1398 #define RDMAC_MODE_LNGREAD_ENAB 0x00000200 1399 #define RDMAC_MODE_SPLIT_ENABLE 0x00000800 1400 #define RDMAC_MODE_BD_SBD_CRPT_ENAB 0x00000800 1401 #define RDMAC_MODE_SPLIT_RESET 0x00001000 1402 #define RDMAC_MODE_MBUF_RBD_CRPT_ENAB 0x00001000 1403 #define RDMAC_MODE_MBUF_SBD_CRPT_ENAB 0x00002000 1404 #define RDMAC_MODE_FIFO_SIZE_128 0x00020000 1405 #define RDMAC_MODE_FIFO_LONG_BURST 0x00030000 1406 #define RDMAC_MODE_JMB_2K_MMRR 0x00800000 1407 #define RDMAC_MODE_MULT_DMA_RD_DIS 0x01000000 1408 #define RDMAC_MODE_IPV4_LSO_EN 0x08000000 1409 #define RDMAC_MODE_IPV6_LSO_EN 0x10000000 1410 #define RDMAC_MODE_H2BNC_VLAN_DET 0x20000000 1411 #define RDMAC_STATUS 0x00004804 1412 #define RDMAC_STATUS_TGTABORT 0x00000004 1413 #define RDMAC_STATUS_MSTABORT 0x00000008 1414 #define RDMAC_STATUS_PARITYERR 0x00000010 1415 #define RDMAC_STATUS_ADDROFLOW 0x00000020 1416 #define RDMAC_STATUS_FIFOOFLOW 0x00000040 1417 #define RDMAC_STATUS_FIFOURUN 0x00000080 1418 #define RDMAC_STATUS_FIFOOREAD 0x00000100 1419 #define RDMAC_STATUS_LNGREAD 0x00000200 1420 /* 0x4808 --> 0x4890 unused */ 1421 1422 #define TG3_RDMA_RSRVCTRL_REG2 0x00004890 1423 #define TG3_LSO_RD_DMA_CRPTEN_CTRL2 0x000048a0 1424 1425 #define TG3_RDMA_RSRVCTRL_REG 0x00004900 1426 #define TG3_RDMA_RSRVCTRL_FIFO_OFLW_FIX 0x00000004 1427 #define TG3_RDMA_RSRVCTRL_FIFO_LWM_1_5K 0x00000c00 1428 #define TG3_RDMA_RSRVCTRL_FIFO_LWM_MASK 0x00000ff0 1429 #define TG3_RDMA_RSRVCTRL_FIFO_HWM_1_5K 0x000c0000 1430 #define TG3_RDMA_RSRVCTRL_FIFO_HWM_MASK 0x000ff000 1431 #define TG3_RDMA_RSRVCTRL_TXMRGN_320B 0x28000000 1432 #define TG3_RDMA_RSRVCTRL_TXMRGN_MASK 0xffe00000 1433 /* 0x4904 --> 0x4910 unused */ 1434 1435 #define TG3_LSO_RD_DMA_CRPTEN_CTRL 0x00004910 1436 #define TG3_LSO_RD_DMA_CRPTEN_CTRL_BLEN_BD_4K 0x00030000 1437 #define TG3_LSO_RD_DMA_CRPTEN_CTRL_BLEN_LSO_4K 0x000c0000 1438 #define TG3_LSO_RD_DMA_TX_LENGTH_WA_5719 0x02000000 1439 #define TG3_LSO_RD_DMA_TX_LENGTH_WA_5720 0x00200000 1440 /* 0x4914 --> 0x4be0 unused */ 1441 1442 #define TG3_NUM_RDMA_CHANNELS 4 1443 #define TG3_RDMA_LENGTH 0x00004be0 1444 1445 /* Write DMA control registers */ 1446 #define WDMAC_MODE 0x00004c00 1447 #define WDMAC_MODE_RESET 0x00000001 1448 #define WDMAC_MODE_ENABLE 0x00000002 1449 #define WDMAC_MODE_TGTABORT_ENAB 0x00000004 1450 #define WDMAC_MODE_MSTABORT_ENAB 0x00000008 1451 #define WDMAC_MODE_PARITYERR_ENAB 0x00000010 1452 #define WDMAC_MODE_ADDROFLOW_ENAB 0x00000020 1453 #define WDMAC_MODE_FIFOOFLOW_ENAB 0x00000040 1454 #define WDMAC_MODE_FIFOURUN_ENAB 0x00000080 1455 #define WDMAC_MODE_FIFOOREAD_ENAB 0x00000100 1456 #define WDMAC_MODE_LNGREAD_ENAB 0x00000200 1457 #define WDMAC_MODE_RX_ACCEL 0x00000400 1458 #define WDMAC_MODE_STATUS_TAG_FIX 0x20000000 1459 #define WDMAC_MODE_BURST_ALL_DATA 0xc0000000 1460 #define WDMAC_STATUS 0x00004c04 1461 #define WDMAC_STATUS_TGTABORT 0x00000004 1462 #define WDMAC_STATUS_MSTABORT 0x00000008 1463 #define WDMAC_STATUS_PARITYERR 0x00000010 1464 #define WDMAC_STATUS_ADDROFLOW 0x00000020 1465 #define WDMAC_STATUS_FIFOOFLOW 0x00000040 1466 #define WDMAC_STATUS_FIFOURUN 0x00000080 1467 #define WDMAC_STATUS_FIFOOREAD 0x00000100 1468 #define WDMAC_STATUS_LNGREAD 0x00000200 1469 /* 0x4c08 --> 0x5000 unused */ 1470 1471 /* Per-cpu register offsets (arm9) */ 1472 #define CPU_MODE 0x00000000 1473 #define CPU_MODE_RESET 0x00000001 1474 #define CPU_MODE_HALT 0x00000400 1475 #define CPU_STATE 0x00000004 1476 #define CPU_EVTMASK 0x00000008 1477 /* 0xc --> 0x1c reserved */ 1478 #define CPU_PC 0x0000001c 1479 #define CPU_INSN 0x00000020 1480 #define CPU_SPAD_UFLOW 0x00000024 1481 #define CPU_WDOG_CLEAR 0x00000028 1482 #define CPU_WDOG_VECTOR 0x0000002c 1483 #define CPU_WDOG_PC 0x00000030 1484 #define CPU_HW_BP 0x00000034 1485 /* 0x38 --> 0x44 unused */ 1486 #define CPU_WDOG_SAVED_STATE 0x00000044 1487 #define CPU_LAST_BRANCH_ADDR 0x00000048 1488 #define CPU_SPAD_UFLOW_SET 0x0000004c 1489 /* 0x50 --> 0x200 unused */ 1490 #define CPU_R0 0x00000200 1491 #define CPU_R1 0x00000204 1492 #define CPU_R2 0x00000208 1493 #define CPU_R3 0x0000020c 1494 #define CPU_R4 0x00000210 1495 #define CPU_R5 0x00000214 1496 #define CPU_R6 0x00000218 1497 #define CPU_R7 0x0000021c 1498 #define CPU_R8 0x00000220 1499 #define CPU_R9 0x00000224 1500 #define CPU_R10 0x00000228 1501 #define CPU_R11 0x0000022c 1502 #define CPU_R12 0x00000230 1503 #define CPU_R13 0x00000234 1504 #define CPU_R14 0x00000238 1505 #define CPU_R15 0x0000023c 1506 #define CPU_R16 0x00000240 1507 #define CPU_R17 0x00000244 1508 #define CPU_R18 0x00000248 1509 #define CPU_R19 0x0000024c 1510 #define CPU_R20 0x00000250 1511 #define CPU_R21 0x00000254 1512 #define CPU_R22 0x00000258 1513 #define CPU_R23 0x0000025c 1514 #define CPU_R24 0x00000260 1515 #define CPU_R25 0x00000264 1516 #define CPU_R26 0x00000268 1517 #define CPU_R27 0x0000026c 1518 #define CPU_R28 0x00000270 1519 #define CPU_R29 0x00000274 1520 #define CPU_R30 0x00000278 1521 #define CPU_R31 0x0000027c 1522 /* 0x280 --> 0x400 unused */ 1523 1524 #define RX_CPU_BASE 0x00005000 1525 #define RX_CPU_MODE 0x00005000 1526 #define RX_CPU_STATE 0x00005004 1527 #define RX_CPU_PGMCTR 0x0000501c 1528 #define RX_CPU_HWBKPT 0x00005034 1529 #define TX_CPU_BASE 0x00005400 1530 #define TX_CPU_MODE 0x00005400 1531 #define TX_CPU_STATE 0x00005404 1532 #define TX_CPU_PGMCTR 0x0000541c 1533 1534 #define VCPU_STATUS 0x00005100 1535 #define VCPU_STATUS_INIT_DONE 0x04000000 1536 #define VCPU_STATUS_DRV_RESET 0x08000000 1537 1538 #define VCPU_CFGSHDW 0x00005104 1539 #define VCPU_CFGSHDW_WOL_ENABLE 0x00000001 1540 #define VCPU_CFGSHDW_WOL_MAGPKT 0x00000004 1541 #define VCPU_CFGSHDW_ASPM_DBNC 0x00001000 1542 1543 /* Mailboxes */ 1544 #define GRCMBOX_BASE 0x00005600 1545 #define GRCMBOX_INTERRUPT_0 0x00005800 /* 64-bit */ 1546 #define GRCMBOX_INTERRUPT_1 0x00005808 /* 64-bit */ 1547 #define GRCMBOX_INTERRUPT_2 0x00005810 /* 64-bit */ 1548 #define GRCMBOX_INTERRUPT_3 0x00005818 /* 64-bit */ 1549 #define GRCMBOX_GENERAL_0 0x00005820 /* 64-bit */ 1550 #define GRCMBOX_GENERAL_1 0x00005828 /* 64-bit */ 1551 #define GRCMBOX_GENERAL_2 0x00005830 /* 64-bit */ 1552 #define GRCMBOX_GENERAL_3 0x00005838 /* 64-bit */ 1553 #define GRCMBOX_GENERAL_4 0x00005840 /* 64-bit */ 1554 #define GRCMBOX_GENERAL_5 0x00005848 /* 64-bit */ 1555 #define GRCMBOX_GENERAL_6 0x00005850 /* 64-bit */ 1556 #define GRCMBOX_GENERAL_7 0x00005858 /* 64-bit */ 1557 #define GRCMBOX_RELOAD_STAT 0x00005860 /* 64-bit */ 1558 #define GRCMBOX_RCVSTD_PROD_IDX 0x00005868 /* 64-bit */ 1559 #define GRCMBOX_RCVJUMBO_PROD_IDX 0x00005870 /* 64-bit */ 1560 #define GRCMBOX_RCVMINI_PROD_IDX 0x00005878 /* 64-bit */ 1561 #define GRCMBOX_RCVRET_CON_IDX_0 0x00005880 /* 64-bit */ 1562 #define GRCMBOX_RCVRET_CON_IDX_1 0x00005888 /* 64-bit */ 1563 #define GRCMBOX_RCVRET_CON_IDX_2 0x00005890 /* 64-bit */ 1564 #define GRCMBOX_RCVRET_CON_IDX_3 0x00005898 /* 64-bit */ 1565 #define GRCMBOX_RCVRET_CON_IDX_4 0x000058a0 /* 64-bit */ 1566 #define GRCMBOX_RCVRET_CON_IDX_5 0x000058a8 /* 64-bit */ 1567 #define GRCMBOX_RCVRET_CON_IDX_6 0x000058b0 /* 64-bit */ 1568 #define GRCMBOX_RCVRET_CON_IDX_7 0x000058b8 /* 64-bit */ 1569 #define GRCMBOX_RCVRET_CON_IDX_8 0x000058c0 /* 64-bit */ 1570 #define GRCMBOX_RCVRET_CON_IDX_9 0x000058c8 /* 64-bit */ 1571 #define GRCMBOX_RCVRET_CON_IDX_10 0x000058d0 /* 64-bit */ 1572 #define GRCMBOX_RCVRET_CON_IDX_11 0x000058d8 /* 64-bit */ 1573 #define GRCMBOX_RCVRET_CON_IDX_12 0x000058e0 /* 64-bit */ 1574 #define GRCMBOX_RCVRET_CON_IDX_13 0x000058e8 /* 64-bit */ 1575 #define GRCMBOX_RCVRET_CON_IDX_14 0x000058f0 /* 64-bit */ 1576 #define GRCMBOX_RCVRET_CON_IDX_15 0x000058f8 /* 64-bit */ 1577 #define GRCMBOX_SNDHOST_PROD_IDX_0 0x00005900 /* 64-bit */ 1578 #define GRCMBOX_SNDHOST_PROD_IDX_1 0x00005908 /* 64-bit */ 1579 #define GRCMBOX_SNDHOST_PROD_IDX_2 0x00005910 /* 64-bit */ 1580 #define GRCMBOX_SNDHOST_PROD_IDX_3 0x00005918 /* 64-bit */ 1581 #define GRCMBOX_SNDHOST_PROD_IDX_4 0x00005920 /* 64-bit */ 1582 #define GRCMBOX_SNDHOST_PROD_IDX_5 0x00005928 /* 64-bit */ 1583 #define GRCMBOX_SNDHOST_PROD_IDX_6 0x00005930 /* 64-bit */ 1584 #define GRCMBOX_SNDHOST_PROD_IDX_7 0x00005938 /* 64-bit */ 1585 #define GRCMBOX_SNDHOST_PROD_IDX_8 0x00005940 /* 64-bit */ 1586 #define GRCMBOX_SNDHOST_PROD_IDX_9 0x00005948 /* 64-bit */ 1587 #define GRCMBOX_SNDHOST_PROD_IDX_10 0x00005950 /* 64-bit */ 1588 #define GRCMBOX_SNDHOST_PROD_IDX_11 0x00005958 /* 64-bit */ 1589 #define GRCMBOX_SNDHOST_PROD_IDX_12 0x00005960 /* 64-bit */ 1590 #define GRCMBOX_SNDHOST_PROD_IDX_13 0x00005968 /* 64-bit */ 1591 #define GRCMBOX_SNDHOST_PROD_IDX_14 0x00005970 /* 64-bit */ 1592 #define GRCMBOX_SNDHOST_PROD_IDX_15 0x00005978 /* 64-bit */ 1593 #define GRCMBOX_SNDNIC_PROD_IDX_0 0x00005980 /* 64-bit */ 1594 #define GRCMBOX_SNDNIC_PROD_IDX_1 0x00005988 /* 64-bit */ 1595 #define GRCMBOX_SNDNIC_PROD_IDX_2 0x00005990 /* 64-bit */ 1596 #define GRCMBOX_SNDNIC_PROD_IDX_3 0x00005998 /* 64-bit */ 1597 #define GRCMBOX_SNDNIC_PROD_IDX_4 0x000059a0 /* 64-bit */ 1598 #define GRCMBOX_SNDNIC_PROD_IDX_5 0x000059a8 /* 64-bit */ 1599 #define GRCMBOX_SNDNIC_PROD_IDX_6 0x000059b0 /* 64-bit */ 1600 #define GRCMBOX_SNDNIC_PROD_IDX_7 0x000059b8 /* 64-bit */ 1601 #define GRCMBOX_SNDNIC_PROD_IDX_8 0x000059c0 /* 64-bit */ 1602 #define GRCMBOX_SNDNIC_PROD_IDX_9 0x000059c8 /* 64-bit */ 1603 #define GRCMBOX_SNDNIC_PROD_IDX_10 0x000059d0 /* 64-bit */ 1604 #define GRCMBOX_SNDNIC_PROD_IDX_11 0x000059d8 /* 64-bit */ 1605 #define GRCMBOX_SNDNIC_PROD_IDX_12 0x000059e0 /* 64-bit */ 1606 #define GRCMBOX_SNDNIC_PROD_IDX_13 0x000059e8 /* 64-bit */ 1607 #define GRCMBOX_SNDNIC_PROD_IDX_14 0x000059f0 /* 64-bit */ 1608 #define GRCMBOX_SNDNIC_PROD_IDX_15 0x000059f8 /* 64-bit */ 1609 #define GRCMBOX_HIGH_PRIO_EV_VECTOR 0x00005a00 1610 #define GRCMBOX_HIGH_PRIO_EV_MASK 0x00005a04 1611 #define GRCMBOX_LOW_PRIO_EV_VEC 0x00005a08 1612 #define GRCMBOX_LOW_PRIO_EV_MASK 0x00005a0c 1613 /* 0x5a10 --> 0x5c00 */ 1614 1615 /* Flow Through queues */ 1616 #define FTQ_RESET 0x00005c00 1617 /* 0x5c04 --> 0x5c10 unused */ 1618 #define FTQ_DMA_NORM_READ_CTL 0x00005c10 1619 #define FTQ_DMA_NORM_READ_FULL_CNT 0x00005c14 1620 #define FTQ_DMA_NORM_READ_FIFO_ENQDEQ 0x00005c18 1621 #define FTQ_DMA_NORM_READ_WRITE_PEEK 0x00005c1c 1622 #define FTQ_DMA_HIGH_READ_CTL 0x00005c20 1623 #define FTQ_DMA_HIGH_READ_FULL_CNT 0x00005c24 1624 #define FTQ_DMA_HIGH_READ_FIFO_ENQDEQ 0x00005c28 1625 #define FTQ_DMA_HIGH_READ_WRITE_PEEK 0x00005c2c 1626 #define FTQ_DMA_COMP_DISC_CTL 0x00005c30 1627 #define FTQ_DMA_COMP_DISC_FULL_CNT 0x00005c34 1628 #define FTQ_DMA_COMP_DISC_FIFO_ENQDEQ 0x00005c38 1629 #define FTQ_DMA_COMP_DISC_WRITE_PEEK 0x00005c3c 1630 #define FTQ_SEND_BD_COMP_CTL 0x00005c40 1631 #define FTQ_SEND_BD_COMP_FULL_CNT 0x00005c44 1632 #define FTQ_SEND_BD_COMP_FIFO_ENQDEQ 0x00005c48 1633 #define FTQ_SEND_BD_COMP_WRITE_PEEK 0x00005c4c 1634 #define FTQ_SEND_DATA_INIT_CTL 0x00005c50 1635 #define FTQ_SEND_DATA_INIT_FULL_CNT 0x00005c54 1636 #define FTQ_SEND_DATA_INIT_FIFO_ENQDEQ 0x00005c58 1637 #define FTQ_SEND_DATA_INIT_WRITE_PEEK 0x00005c5c 1638 #define FTQ_DMA_NORM_WRITE_CTL 0x00005c60 1639 #define FTQ_DMA_NORM_WRITE_FULL_CNT 0x00005c64 1640 #define FTQ_DMA_NORM_WRITE_FIFO_ENQDEQ 0x00005c68 1641 #define FTQ_DMA_NORM_WRITE_WRITE_PEEK 0x00005c6c 1642 #define FTQ_DMA_HIGH_WRITE_CTL 0x00005c70 1643 #define FTQ_DMA_HIGH_WRITE_FULL_CNT 0x00005c74 1644 #define FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ 0x00005c78 1645 #define FTQ_DMA_HIGH_WRITE_WRITE_PEEK 0x00005c7c 1646 #define FTQ_SWTYPE1_CTL 0x00005c80 1647 #define FTQ_SWTYPE1_FULL_CNT 0x00005c84 1648 #define FTQ_SWTYPE1_FIFO_ENQDEQ 0x00005c88 1649 #define FTQ_SWTYPE1_WRITE_PEEK 0x00005c8c 1650 #define FTQ_SEND_DATA_COMP_CTL 0x00005c90 1651 #define FTQ_SEND_DATA_COMP_FULL_CNT 0x00005c94 1652 #define FTQ_SEND_DATA_COMP_FIFO_ENQDEQ 0x00005c98 1653 #define FTQ_SEND_DATA_COMP_WRITE_PEEK 0x00005c9c 1654 #define FTQ_HOST_COAL_CTL 0x00005ca0 1655 #define FTQ_HOST_COAL_FULL_CNT 0x00005ca4 1656 #define FTQ_HOST_COAL_FIFO_ENQDEQ 0x00005ca8 1657 #define FTQ_HOST_COAL_WRITE_PEEK 0x00005cac 1658 #define FTQ_MAC_TX_CTL 0x00005cb0 1659 #define FTQ_MAC_TX_FULL_CNT 0x00005cb4 1660 #define FTQ_MAC_TX_FIFO_ENQDEQ 0x00005cb8 1661 #define FTQ_MAC_TX_WRITE_PEEK 0x00005cbc 1662 #define FTQ_MB_FREE_CTL 0x00005cc0 1663 #define FTQ_MB_FREE_FULL_CNT 0x00005cc4 1664 #define FTQ_MB_FREE_FIFO_ENQDEQ 0x00005cc8 1665 #define FTQ_MB_FREE_WRITE_PEEK 0x00005ccc 1666 #define FTQ_RCVBD_COMP_CTL 0x00005cd0 1667 #define FTQ_RCVBD_COMP_FULL_CNT 0x00005cd4 1668 #define FTQ_RCVBD_COMP_FIFO_ENQDEQ 0x00005cd8 1669 #define FTQ_RCVBD_COMP_WRITE_PEEK 0x00005cdc 1670 #define FTQ_RCVLST_PLMT_CTL 0x00005ce0 1671 #define FTQ_RCVLST_PLMT_FULL_CNT 0x00005ce4 1672 #define FTQ_RCVLST_PLMT_FIFO_ENQDEQ 0x00005ce8 1673 #define FTQ_RCVLST_PLMT_WRITE_PEEK 0x00005cec 1674 #define FTQ_RCVDATA_INI_CTL 0x00005cf0 1675 #define FTQ_RCVDATA_INI_FULL_CNT 0x00005cf4 1676 #define FTQ_RCVDATA_INI_FIFO_ENQDEQ 0x00005cf8 1677 #define FTQ_RCVDATA_INI_WRITE_PEEK 0x00005cfc 1678 #define FTQ_RCVDATA_COMP_CTL 0x00005d00 1679 #define FTQ_RCVDATA_COMP_FULL_CNT 0x00005d04 1680 #define FTQ_RCVDATA_COMP_FIFO_ENQDEQ 0x00005d08 1681 #define FTQ_RCVDATA_COMP_WRITE_PEEK 0x00005d0c 1682 #define FTQ_SWTYPE2_CTL 0x00005d10 1683 #define FTQ_SWTYPE2_FULL_CNT 0x00005d14 1684 #define FTQ_SWTYPE2_FIFO_ENQDEQ 0x00005d18 1685 #define FTQ_SWTYPE2_WRITE_PEEK 0x00005d1c 1686 /* 0x5d20 --> 0x6000 unused */ 1687 1688 /* Message signaled interrupt registers */ 1689 #define MSGINT_MODE 0x00006000 1690 #define MSGINT_MODE_RESET 0x00000001 1691 #define MSGINT_MODE_ENABLE 0x00000002 1692 #define MSGINT_MODE_ONE_SHOT_DISABLE 0x00000020 1693 #define MSGINT_MODE_MULTIVEC_EN 0x00000080 1694 #define MSGINT_STATUS 0x00006004 1695 #define MSGINT_STATUS_MSI_REQ 0x00000001 1696 #define MSGINT_FIFO 0x00006008 1697 /* 0x600c --> 0x6400 unused */ 1698 1699 /* DMA completion registers */ 1700 #define DMAC_MODE 0x00006400 1701 #define DMAC_MODE_RESET 0x00000001 1702 #define DMAC_MODE_ENABLE 0x00000002 1703 /* 0x6404 --> 0x6800 unused */ 1704 1705 /* GRC registers */ 1706 #define GRC_MODE 0x00006800 1707 #define GRC_MODE_UPD_ON_COAL 0x00000001 1708 #define GRC_MODE_BSWAP_NONFRM_DATA 0x00000002 1709 #define GRC_MODE_WSWAP_NONFRM_DATA 0x00000004 1710 #define GRC_MODE_BSWAP_DATA 0x00000010 1711 #define GRC_MODE_WSWAP_DATA 0x00000020 1712 #define GRC_MODE_BYTE_SWAP_B2HRX_DATA 0x00000040 1713 #define GRC_MODE_WORD_SWAP_B2HRX_DATA 0x00000080 1714 #define GRC_MODE_SPLITHDR 0x00000100 1715 #define GRC_MODE_NOFRM_CRACKING 0x00000200 1716 #define GRC_MODE_INCL_CRC 0x00000400 1717 #define GRC_MODE_ALLOW_BAD_FRMS 0x00000800 1718 #define GRC_MODE_NOIRQ_ON_SENDS 0x00002000 1719 #define GRC_MODE_NOIRQ_ON_RCV 0x00004000 1720 #define GRC_MODE_FORCE_PCI32BIT 0x00008000 1721 #define GRC_MODE_B2HRX_ENABLE 0x00008000 1722 #define GRC_MODE_HOST_STACKUP 0x00010000 1723 #define GRC_MODE_HOST_SENDBDS 0x00020000 1724 #define GRC_MODE_HTX2B_ENABLE 0x00040000 1725 #define GRC_MODE_TIME_SYNC_ENABLE 0x00080000 1726 #define GRC_MODE_NO_TX_PHDR_CSUM 0x00100000 1727 #define GRC_MODE_NVRAM_WR_ENABLE 0x00200000 1728 #define GRC_MODE_PCIE_TL_SEL 0x00000000 1729 #define GRC_MODE_PCIE_PL_SEL 0x00400000 1730 #define GRC_MODE_NO_RX_PHDR_CSUM 0x00800000 1731 #define GRC_MODE_IRQ_ON_TX_CPU_ATTN 0x01000000 1732 #define GRC_MODE_IRQ_ON_RX_CPU_ATTN 0x02000000 1733 #define GRC_MODE_IRQ_ON_MAC_ATTN 0x04000000 1734 #define GRC_MODE_IRQ_ON_DMA_ATTN 0x08000000 1735 #define GRC_MODE_IRQ_ON_FLOW_ATTN 0x10000000 1736 #define GRC_MODE_4X_NIC_SEND_RINGS 0x20000000 1737 #define GRC_MODE_PCIE_DL_SEL 0x20000000 1738 #define GRC_MODE_MCAST_FRM_ENABLE 0x40000000 1739 #define GRC_MODE_PCIE_HI_1K_EN 0x80000000 1740 #define GRC_MODE_PCIE_PORT_MASK (GRC_MODE_PCIE_TL_SEL | \ 1741 GRC_MODE_PCIE_PL_SEL | \ 1742 GRC_MODE_PCIE_DL_SEL | \ 1743 GRC_MODE_PCIE_HI_1K_EN) 1744 #define GRC_MISC_CFG 0x00006804 1745 #define GRC_MISC_CFG_CORECLK_RESET 0x00000001 1746 #define GRC_MISC_CFG_PRESCALAR_MASK 0x000000fe 1747 #define GRC_MISC_CFG_PRESCALAR_SHIFT 1 1748 #define GRC_MISC_CFG_BOARD_ID_MASK 0x0001e000 1749 #define GRC_MISC_CFG_BOARD_ID_5700 0x0001e000 1750 #define GRC_MISC_CFG_BOARD_ID_5701 0x00000000 1751 #define GRC_MISC_CFG_BOARD_ID_5702FE 0x00004000 1752 #define GRC_MISC_CFG_BOARD_ID_5703 0x00000000 1753 #define GRC_MISC_CFG_BOARD_ID_5703S 0x00002000 1754 #define GRC_MISC_CFG_BOARD_ID_5704 0x00000000 1755 #define GRC_MISC_CFG_BOARD_ID_5704CIOBE 0x00004000 1756 #define GRC_MISC_CFG_BOARD_ID_5704_A2 0x00008000 1757 #define GRC_MISC_CFG_BOARD_ID_5788 0x00010000 1758 #define GRC_MISC_CFG_BOARD_ID_5788M 0x00018000 1759 #define GRC_MISC_CFG_BOARD_ID_AC91002A1 0x00018000 1760 #define GRC_MISC_CFG_EPHY_IDDQ 0x00200000 1761 #define GRC_MISC_CFG_KEEP_GPHY_POWER 0x04000000 1762 #define GRC_LOCAL_CTRL 0x00006808 1763 #define GRC_LCLCTRL_INT_ACTIVE 0x00000001 1764 #define GRC_LCLCTRL_CLEARINT 0x00000002 1765 #define GRC_LCLCTRL_SETINT 0x00000004 1766 #define GRC_LCLCTRL_INT_ON_ATTN 0x00000008 1767 #define GRC_LCLCTRL_GPIO_UART_SEL 0x00000010 /* 5755 only */ 1768 #define GRC_LCLCTRL_USE_SIG_DETECT 0x00000010 /* 5714/5780 only */ 1769 #define GRC_LCLCTRL_USE_EXT_SIG_DETECT 0x00000020 /* 5714/5780 only */ 1770 #define GRC_LCLCTRL_GPIO_INPUT3 0x00000020 1771 #define GRC_LCLCTRL_GPIO_OE3 0x00000040 1772 #define GRC_LCLCTRL_GPIO_OUTPUT3 0x00000080 1773 #define GRC_LCLCTRL_GPIO_INPUT0 0x00000100 1774 #define GRC_LCLCTRL_GPIO_INPUT1 0x00000200 1775 #define GRC_LCLCTRL_GPIO_INPUT2 0x00000400 1776 #define GRC_LCLCTRL_GPIO_OE0 0x00000800 1777 #define GRC_LCLCTRL_GPIO_OE1 0x00001000 1778 #define GRC_LCLCTRL_GPIO_OE2 0x00002000 1779 #define GRC_LCLCTRL_GPIO_OUTPUT0 0x00004000 1780 #define GRC_LCLCTRL_GPIO_OUTPUT1 0x00008000 1781 #define GRC_LCLCTRL_GPIO_OUTPUT2 0x00010000 1782 #define GRC_LCLCTRL_EXTMEM_ENABLE 0x00020000 1783 #define GRC_LCLCTRL_MEMSZ_MASK 0x001c0000 1784 #define GRC_LCLCTRL_MEMSZ_256K 0x00000000 1785 #define GRC_LCLCTRL_MEMSZ_512K 0x00040000 1786 #define GRC_LCLCTRL_MEMSZ_1M 0x00080000 1787 #define GRC_LCLCTRL_MEMSZ_2M 0x000c0000 1788 #define GRC_LCLCTRL_MEMSZ_4M 0x00100000 1789 #define GRC_LCLCTRL_MEMSZ_8M 0x00140000 1790 #define GRC_LCLCTRL_MEMSZ_16M 0x00180000 1791 #define GRC_LCLCTRL_BANK_SELECT 0x00200000 1792 #define GRC_LCLCTRL_SSRAM_TYPE 0x00400000 1793 #define GRC_LCLCTRL_AUTO_SEEPROM 0x01000000 1794 #define GRC_TIMER 0x0000680c 1795 #define GRC_RX_CPU_EVENT 0x00006810 1796 #define GRC_RX_CPU_DRIVER_EVENT 0x00004000 1797 #define GRC_RX_TIMER_REF 0x00006814 1798 #define GRC_RX_CPU_SEM 0x00006818 1799 #define GRC_REMOTE_RX_CPU_ATTN 0x0000681c 1800 #define GRC_TX_CPU_EVENT 0x00006820 1801 #define GRC_TX_TIMER_REF 0x00006824 1802 #define GRC_TX_CPU_SEM 0x00006828 1803 #define GRC_REMOTE_TX_CPU_ATTN 0x0000682c 1804 #define GRC_MEM_POWER_UP 0x00006830 /* 64-bit */ 1805 #define GRC_EEPROM_ADDR 0x00006838 1806 #define EEPROM_ADDR_WRITE 0x00000000 1807 #define EEPROM_ADDR_READ 0x80000000 1808 #define EEPROM_ADDR_COMPLETE 0x40000000 1809 #define EEPROM_ADDR_FSM_RESET 0x20000000 1810 #define EEPROM_ADDR_DEVID_MASK 0x1c000000 1811 #define EEPROM_ADDR_DEVID_SHIFT 26 1812 #define EEPROM_ADDR_START 0x02000000 1813 #define EEPROM_ADDR_CLKPERD_SHIFT 16 1814 #define EEPROM_ADDR_ADDR_MASK 0x0000ffff 1815 #define EEPROM_ADDR_ADDR_SHIFT 0 1816 #define EEPROM_DEFAULT_CLOCK_PERIOD 0x60 1817 #define EEPROM_CHIP_SIZE (64 * 1024) 1818 #define GRC_EEPROM_DATA 0x0000683c 1819 #define GRC_EEPROM_CTRL 0x00006840 1820 #define GRC_MDI_CTRL 0x00006844 1821 #define GRC_SEEPROM_DELAY 0x00006848 1822 /* 0x684c --> 0x6890 unused */ 1823 #define GRC_VCPU_EXT_CTRL 0x00006890 1824 #define GRC_VCPU_EXT_CTRL_HALT_CPU 0x00400000 1825 #define GRC_VCPU_EXT_CTRL_DISABLE_WOL 0x20000000 1826 #define GRC_FASTBOOT_PC 0x00006894 /* 5752, 5755, 5787 */ 1827 1828 #define TG3_EAV_REF_CLCK_LSB 0x00006900 1829 #define TG3_EAV_REF_CLCK_MSB 0x00006904 1830 #define TG3_EAV_REF_CLCK_CTL 0x00006908 1831 #define TG3_EAV_REF_CLCK_CTL_STOP 0x00000002 1832 #define TG3_EAV_REF_CLCK_CTL_RESUME 0x00000004 1833 #define TG3_EAV_CTL_TSYNC_GPIO_MASK (0x3 << 16) 1834 #define TG3_EAV_CTL_TSYNC_WDOG0 (1 << 17) 1835 1836 #define TG3_EAV_WATCHDOG0_LSB 0x00006918 1837 #define TG3_EAV_WATCHDOG0_MSB 0x0000691c 1838 #define TG3_EAV_WATCHDOG0_EN (1 << 31) 1839 #define TG3_EAV_WATCHDOG_MSB_MASK 0x7fffffff 1840 1841 #define TG3_EAV_REF_CLK_CORRECT_CTL 0x00006928 1842 #define TG3_EAV_REF_CLK_CORRECT_EN (1 << 31) 1843 #define TG3_EAV_REF_CLK_CORRECT_NEG (1 << 30) 1844 1845 #define TG3_EAV_REF_CLK_CORRECT_MASK 0xffffff 1846 1847 /* 0x692c --> 0x7000 unused */ 1848 1849 /* NVRAM Control registers */ 1850 #define NVRAM_CMD 0x00007000 1851 #define NVRAM_CMD_RESET 0x00000001 1852 #define NVRAM_CMD_DONE 0x00000008 1853 #define NVRAM_CMD_GO 0x00000010 1854 #define NVRAM_CMD_WR 0x00000020 1855 #define NVRAM_CMD_RD 0x00000000 1856 #define NVRAM_CMD_ERASE 0x00000040 1857 #define NVRAM_CMD_FIRST 0x00000080 1858 #define NVRAM_CMD_LAST 0x00000100 1859 #define NVRAM_CMD_WREN 0x00010000 1860 #define NVRAM_CMD_WRDI 0x00020000 1861 #define NVRAM_STAT 0x00007004 1862 #define NVRAM_WRDATA 0x00007008 1863 #define NVRAM_ADDR 0x0000700c 1864 #define NVRAM_ADDR_MSK 0x00ffffff 1865 #define NVRAM_RDDATA 0x00007010 1866 #define NVRAM_CFG1 0x00007014 1867 #define NVRAM_CFG1_FLASHIF_ENAB 0x00000001 1868 #define NVRAM_CFG1_BUFFERED_MODE 0x00000002 1869 #define NVRAM_CFG1_PASS_THRU 0x00000004 1870 #define NVRAM_CFG1_STATUS_BITS 0x00000070 1871 #define NVRAM_CFG1_BIT_BANG 0x00000008 1872 #define NVRAM_CFG1_FLASH_SIZE 0x02000000 1873 #define NVRAM_CFG1_COMPAT_BYPASS 0x80000000 1874 #define NVRAM_CFG1_VENDOR_MASK 0x03000003 1875 #define FLASH_VENDOR_ATMEL_EEPROM 0x02000000 1876 #define FLASH_VENDOR_ATMEL_FLASH_BUFFERED 0x02000003 1877 #define FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED 0x00000003 1878 #define FLASH_VENDOR_ST 0x03000001 1879 #define FLASH_VENDOR_SAIFUN 0x01000003 1880 #define FLASH_VENDOR_SST_SMALL 0x00000001 1881 #define FLASH_VENDOR_SST_LARGE 0x02000001 1882 #define NVRAM_CFG1_5752VENDOR_MASK 0x03c00003 1883 #define NVRAM_CFG1_5762VENDOR_MASK 0x03e00003 1884 #define FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ 0x00000000 1885 #define FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ 0x02000000 1886 #define FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED 0x02000003 1887 #define FLASH_5752VENDOR_ST_M45PE10 0x02400000 1888 #define FLASH_5752VENDOR_ST_M45PE20 0x02400002 1889 #define FLASH_5752VENDOR_ST_M45PE40 0x02400001 1890 #define FLASH_5755VENDOR_ATMEL_FLASH_1 0x03400001 1891 #define FLASH_5755VENDOR_ATMEL_FLASH_2 0x03400002 1892 #define FLASH_5755VENDOR_ATMEL_FLASH_3 0x03400000 1893 #define FLASH_5755VENDOR_ATMEL_FLASH_4 0x00000003 1894 #define FLASH_5755VENDOR_ATMEL_FLASH_5 0x02000003 1895 #define FLASH_5755VENDOR_ATMEL_EEPROM_64KHZ 0x03c00003 1896 #define FLASH_5755VENDOR_ATMEL_EEPROM_376KHZ 0x03c00002 1897 #define FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ 0x03000003 1898 #define FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ 0x03000002 1899 #define FLASH_5787VENDOR_MICRO_EEPROM_64KHZ 0x03000000 1900 #define FLASH_5787VENDOR_MICRO_EEPROM_376KHZ 0x02000000 1901 #define FLASH_5761VENDOR_ATMEL_MDB021D 0x00800003 1902 #define FLASH_5761VENDOR_ATMEL_MDB041D 0x00800000 1903 #define FLASH_5761VENDOR_ATMEL_MDB081D 0x00800002 1904 #define FLASH_5761VENDOR_ATMEL_MDB161D 0x00800001 1905 #define FLASH_5761VENDOR_ATMEL_ADB021D 0x00000003 1906 #define FLASH_5761VENDOR_ATMEL_ADB041D 0x00000000 1907 #define FLASH_5761VENDOR_ATMEL_ADB081D 0x00000002 1908 #define FLASH_5761VENDOR_ATMEL_ADB161D 0x00000001 1909 #define FLASH_5761VENDOR_ST_M_M45PE20 0x02800001 1910 #define FLASH_5761VENDOR_ST_M_M45PE40 0x02800000 1911 #define FLASH_5761VENDOR_ST_M_M45PE80 0x02800002 1912 #define FLASH_5761VENDOR_ST_M_M45PE16 0x02800003 1913 #define FLASH_5761VENDOR_ST_A_M45PE20 0x02000001 1914 #define FLASH_5761VENDOR_ST_A_M45PE40 0x02000000 1915 #define FLASH_5761VENDOR_ST_A_M45PE80 0x02000002 1916 #define FLASH_5761VENDOR_ST_A_M45PE16 0x02000003 1917 #define FLASH_57780VENDOR_ATMEL_AT45DB011D 0x00400000 1918 #define FLASH_57780VENDOR_ATMEL_AT45DB011B 0x03400000 1919 #define FLASH_57780VENDOR_ATMEL_AT45DB021D 0x00400002 1920 #define FLASH_57780VENDOR_ATMEL_AT45DB021B 0x03400002 1921 #define FLASH_57780VENDOR_ATMEL_AT45DB041D 0x00400001 1922 #define FLASH_57780VENDOR_ATMEL_AT45DB041B 0x03400001 1923 #define FLASH_5717VENDOR_ATMEL_EEPROM 0x02000001 1924 #define FLASH_5717VENDOR_MICRO_EEPROM 0x02000003 1925 #define FLASH_5717VENDOR_ATMEL_MDB011D 0x01000001 1926 #define FLASH_5717VENDOR_ATMEL_MDB021D 0x01000003 1927 #define FLASH_5717VENDOR_ST_M_M25PE10 0x02000000 1928 #define FLASH_5717VENDOR_ST_M_M25PE20 0x02000002 1929 #define FLASH_5717VENDOR_ST_M_M45PE10 0x00000001 1930 #define FLASH_5717VENDOR_ST_M_M45PE20 0x00000003 1931 #define FLASH_5717VENDOR_ATMEL_ADB011B 0x01400000 1932 #define FLASH_5717VENDOR_ATMEL_ADB021B 0x01400002 1933 #define FLASH_5717VENDOR_ATMEL_ADB011D 0x01400001 1934 #define FLASH_5717VENDOR_ATMEL_ADB021D 0x01400003 1935 #define FLASH_5717VENDOR_ST_A_M25PE10 0x02400000 1936 #define FLASH_5717VENDOR_ST_A_M25PE20 0x02400002 1937 #define FLASH_5717VENDOR_ST_A_M45PE10 0x02400001 1938 #define FLASH_5717VENDOR_ST_A_M45PE20 0x02400003 1939 #define FLASH_5717VENDOR_ATMEL_45USPT 0x03400000 1940 #define FLASH_5717VENDOR_ST_25USPT 0x03400002 1941 #define FLASH_5717VENDOR_ST_45USPT 0x03400001 1942 #define FLASH_5720_EEPROM_HD 0x00000001 1943 #define FLASH_5720_EEPROM_LD 0x00000003 1944 #define FLASH_5762_EEPROM_HD 0x02000001 1945 #define FLASH_5762_EEPROM_LD 0x02000003 1946 #define FLASH_5720VENDOR_M_ATMEL_DB011D 0x01000000 1947 #define FLASH_5720VENDOR_M_ATMEL_DB021D 0x01000002 1948 #define FLASH_5720VENDOR_M_ATMEL_DB041D 0x01000001 1949 #define FLASH_5720VENDOR_M_ATMEL_DB081D 0x01000003 1950 #define FLASH_5720VENDOR_M_ST_M25PE10 0x02000000 1951 #define FLASH_5720VENDOR_M_ST_M25PE20 0x02000002 1952 #define FLASH_5720VENDOR_M_ST_M25PE40 0x02000001 1953 #define FLASH_5720VENDOR_M_ST_M25PE80 0x02000003 1954 #define FLASH_5720VENDOR_M_ST_M45PE10 0x03000000 1955 #define FLASH_5720VENDOR_M_ST_M45PE20 0x03000002 1956 #define FLASH_5720VENDOR_M_ST_M45PE40 0x03000001 1957 #define FLASH_5720VENDOR_M_ST_M45PE80 0x03000003 1958 #define FLASH_5720VENDOR_A_ATMEL_DB011B 0x01800000 1959 #define FLASH_5720VENDOR_A_ATMEL_DB021B 0x01800002 1960 #define FLASH_5720VENDOR_A_ATMEL_DB041B 0x01800001 1961 #define FLASH_5720VENDOR_A_ATMEL_DB011D 0x01c00000 1962 #define FLASH_5720VENDOR_A_ATMEL_DB021D 0x01c00002 1963 #define FLASH_5720VENDOR_A_ATMEL_DB041D 0x01c00001 1964 #define FLASH_5720VENDOR_A_ATMEL_DB081D 0x01c00003 1965 #define FLASH_5720VENDOR_A_ST_M25PE10 0x02800000 1966 #define FLASH_5720VENDOR_A_ST_M25PE20 0x02800002 1967 #define FLASH_5720VENDOR_A_ST_M25PE40 0x02800001 1968 #define FLASH_5720VENDOR_A_ST_M25PE80 0x02800003 1969 #define FLASH_5720VENDOR_A_ST_M45PE10 0x02c00000 1970 #define FLASH_5720VENDOR_A_ST_M45PE20 0x02c00002 1971 #define FLASH_5720VENDOR_A_ST_M45PE40 0x02c00001 1972 #define FLASH_5720VENDOR_A_ST_M45PE80 0x02c00003 1973 #define FLASH_5720VENDOR_ATMEL_45USPT 0x03c00000 1974 #define FLASH_5720VENDOR_ST_25USPT 0x03c00002 1975 #define FLASH_5720VENDOR_ST_45USPT 0x03c00001 1976 #define NVRAM_CFG1_5752PAGE_SIZE_MASK 0x70000000 1977 #define FLASH_5752PAGE_SIZE_256 0x00000000 1978 #define FLASH_5752PAGE_SIZE_512 0x10000000 1979 #define FLASH_5752PAGE_SIZE_1K 0x20000000 1980 #define FLASH_5752PAGE_SIZE_2K 0x30000000 1981 #define FLASH_5752PAGE_SIZE_4K 0x40000000 1982 #define FLASH_5752PAGE_SIZE_264 0x50000000 1983 #define FLASH_5752PAGE_SIZE_528 0x60000000 1984 #define NVRAM_CFG2 0x00007018 1985 #define NVRAM_CFG3 0x0000701c 1986 #define NVRAM_SWARB 0x00007020 1987 #define SWARB_REQ_SET0 0x00000001 1988 #define SWARB_REQ_SET1 0x00000002 1989 #define SWARB_REQ_SET2 0x00000004 1990 #define SWARB_REQ_SET3 0x00000008 1991 #define SWARB_REQ_CLR0 0x00000010 1992 #define SWARB_REQ_CLR1 0x00000020 1993 #define SWARB_REQ_CLR2 0x00000040 1994 #define SWARB_REQ_CLR3 0x00000080 1995 #define SWARB_GNT0 0x00000100 1996 #define SWARB_GNT1 0x00000200 1997 #define SWARB_GNT2 0x00000400 1998 #define SWARB_GNT3 0x00000800 1999 #define SWARB_REQ0 0x00001000 2000 #define SWARB_REQ1 0x00002000 2001 #define SWARB_REQ2 0x00004000 2002 #define SWARB_REQ3 0x00008000 2003 #define NVRAM_ACCESS 0x00007024 2004 #define ACCESS_ENABLE 0x00000001 2005 #define ACCESS_WR_ENABLE 0x00000002 2006 #define NVRAM_WRITE1 0x00007028 2007 /* 0x702c unused */ 2008 2009 #define NVRAM_ADDR_LOCKOUT 0x00007030 2010 /* 0x7034 --> 0x7500 unused */ 2011 2012 #define OTP_MODE 0x00007500 2013 #define OTP_MODE_OTP_THRU_GRC 0x00000001 2014 #define OTP_CTRL 0x00007504 2015 #define OTP_CTRL_OTP_PROG_ENABLE 0x00200000 2016 #define OTP_CTRL_OTP_CMD_READ 0x00000000 2017 #define OTP_CTRL_OTP_CMD_INIT 0x00000008 2018 #define OTP_CTRL_OTP_CMD_START 0x00000001 2019 #define OTP_STATUS 0x00007508 2020 #define OTP_STATUS_CMD_DONE 0x00000001 2021 #define OTP_ADDRESS 0x0000750c 2022 #define OTP_ADDRESS_MAGIC1 0x000000a0 2023 #define OTP_ADDRESS_MAGIC2 0x00000080 2024 /* 0x7510 unused */ 2025 2026 #define OTP_READ_DATA 0x00007514 2027 /* 0x7518 --> 0x7c04 unused */ 2028 2029 #define PCIE_TRANSACTION_CFG 0x00007c04 2030 #define PCIE_TRANS_CFG_1SHOT_MSI 0x20000000 2031 #define PCIE_TRANS_CFG_LOM 0x00000020 2032 /* 0x7c08 --> 0x7d28 unused */ 2033 2034 #define PCIE_PWR_MGMT_THRESH 0x00007d28 2035 #define PCIE_PWR_MGMT_L1_THRESH_MSK 0x0000ff00 2036 #define PCIE_PWR_MGMT_L1_THRESH_4MS 0x0000ff00 2037 #define PCIE_PWR_MGMT_EXT_ASPM_TMR_EN 0x01000000 2038 /* 0x7d2c --> 0x7d54 unused */ 2039 2040 #define TG3_PCIE_LNKCTL 0x00007d54 2041 #define TG3_PCIE_LNKCTL_L1_PLL_PD_EN 0x00000008 2042 #define TG3_PCIE_LNKCTL_L1_PLL_PD_DIS 0x00000080 2043 /* 0x7d58 --> 0x7e70 unused */ 2044 2045 #define TG3_PCIE_PHY_TSTCTL 0x00007e2c 2046 #define TG3_PCIE_PHY_TSTCTL_PCIE10 0x00000040 2047 #define TG3_PCIE_PHY_TSTCTL_PSCRAM 0x00000020 2048 2049 #define TG3_PCIE_EIDLE_DELAY 0x00007e70 2050 #define TG3_PCIE_EIDLE_DELAY_MASK 0x0000001f 2051 #define TG3_PCIE_EIDLE_DELAY_13_CLKS 0x0000000c 2052 /* 0x7e74 --> 0x8000 unused */ 2053 2054 2055 /* Alternate PCIE definitions */ 2056 #define TG3_PCIE_TLDLPL_PORT 0x00007c00 2057 #define TG3_PCIE_DL_LO_FTSMAX 0x0000000c 2058 #define TG3_PCIE_DL_LO_FTSMAX_MSK 0x000000ff 2059 #define TG3_PCIE_DL_LO_FTSMAX_VAL 0x0000002c 2060 #define TG3_PCIE_PL_LO_PHYCTL1 0x00000004 2061 #define TG3_PCIE_PL_LO_PHYCTL1_L1PLLPD_EN 0x00001000 2062 #define TG3_PCIE_PL_LO_PHYCTL5 0x00000014 2063 #define TG3_PCIE_PL_LO_PHYCTL5_DIS_L2CLKREQ 0x80000000 2064 2065 #define TG3_REG_BLK_SIZE 0x00008000 2066 2067 /* OTP bit definitions */ 2068 #define TG3_OTP_AGCTGT_MASK 0x000000e0 2069 #define TG3_OTP_AGCTGT_SHIFT 1 2070 #define TG3_OTP_HPFFLTR_MASK 0x00000300 2071 #define TG3_OTP_HPFFLTR_SHIFT 1 2072 #define TG3_OTP_HPFOVER_MASK 0x00000400 2073 #define TG3_OTP_HPFOVER_SHIFT 1 2074 #define TG3_OTP_LPFDIS_MASK 0x00000800 2075 #define TG3_OTP_LPFDIS_SHIFT 11 2076 #define TG3_OTP_VDAC_MASK 0xff000000 2077 #define TG3_OTP_VDAC_SHIFT 24 2078 #define TG3_OTP_10BTAMP_MASK 0x0000f000 2079 #define TG3_OTP_10BTAMP_SHIFT 8 2080 #define TG3_OTP_ROFF_MASK 0x00e00000 2081 #define TG3_OTP_ROFF_SHIFT 11 2082 #define TG3_OTP_RCOFF_MASK 0x001c0000 2083 #define TG3_OTP_RCOFF_SHIFT 16 2084 2085 #define TG3_OTP_DEFAULT 0x286c1640 2086 2087 2088 /* Hardware Legacy NVRAM layout */ 2089 #define TG3_NVM_VPD_OFF 0x100 2090 #define TG3_NVM_VPD_LEN 256 2091 2092 /* Hardware Selfboot NVRAM layout */ 2093 #define TG3_NVM_HWSB_CFG1 0x00000004 2094 #define TG3_NVM_HWSB_CFG1_MAJMSK 0xf8000000 2095 #define TG3_NVM_HWSB_CFG1_MAJSFT 27 2096 #define TG3_NVM_HWSB_CFG1_MINMSK 0x07c00000 2097 #define TG3_NVM_HWSB_CFG1_MINSFT 22 2098 2099 #define TG3_EEPROM_MAGIC 0x669955aa 2100 #define TG3_EEPROM_MAGIC_FW 0xa5000000 2101 #define TG3_EEPROM_MAGIC_FW_MSK 0xff000000 2102 #define TG3_EEPROM_SB_FORMAT_MASK 0x00e00000 2103 #define TG3_EEPROM_SB_FORMAT_1 0x00200000 2104 #define TG3_EEPROM_SB_REVISION_MASK 0x001f0000 2105 #define TG3_EEPROM_SB_REVISION_0 0x00000000 2106 #define TG3_EEPROM_SB_REVISION_2 0x00020000 2107 #define TG3_EEPROM_SB_REVISION_3 0x00030000 2108 #define TG3_EEPROM_SB_REVISION_4 0x00040000 2109 #define TG3_EEPROM_SB_REVISION_5 0x00050000 2110 #define TG3_EEPROM_SB_REVISION_6 0x00060000 2111 #define TG3_EEPROM_MAGIC_HW 0xabcd 2112 #define TG3_EEPROM_MAGIC_HW_MSK 0xffff 2113 2114 #define TG3_NVM_DIR_START 0x18 2115 #define TG3_NVM_DIR_END 0x78 2116 #define TG3_NVM_DIRENT_SIZE 0xc 2117 #define TG3_NVM_DIRTYPE_SHIFT 24 2118 #define TG3_NVM_DIRTYPE_LENMSK 0x003fffff 2119 #define TG3_NVM_DIRTYPE_ASFINI 1 2120 #define TG3_NVM_DIRTYPE_EXTVPD 20 2121 #define TG3_NVM_PTREV_BCVER 0x94 2122 #define TG3_NVM_BCVER_MAJMSK 0x0000ff00 2123 #define TG3_NVM_BCVER_MAJSFT 8 2124 #define TG3_NVM_BCVER_MINMSK 0x000000ff 2125 2126 #define TG3_EEPROM_SB_F1R0_EDH_OFF 0x10 2127 #define TG3_EEPROM_SB_F1R2_EDH_OFF 0x14 2128 #define TG3_EEPROM_SB_F1R2_MBA_OFF 0x10 2129 #define TG3_EEPROM_SB_F1R3_EDH_OFF 0x18 2130 #define TG3_EEPROM_SB_F1R4_EDH_OFF 0x1c 2131 #define TG3_EEPROM_SB_F1R5_EDH_OFF 0x20 2132 #define TG3_EEPROM_SB_F1R6_EDH_OFF 0x4c 2133 #define TG3_EEPROM_SB_EDH_MAJ_MASK 0x00000700 2134 #define TG3_EEPROM_SB_EDH_MAJ_SHFT 8 2135 #define TG3_EEPROM_SB_EDH_MIN_MASK 0x000000ff 2136 #define TG3_EEPROM_SB_EDH_BLD_MASK 0x0000f800 2137 #define TG3_EEPROM_SB_EDH_BLD_SHFT 11 2138 2139 2140 /* 32K Window into NIC internal memory */ 2141 #define NIC_SRAM_WIN_BASE 0x00008000 2142 2143 /* Offsets into first 32k of NIC internal memory. */ 2144 #define NIC_SRAM_PAGE_ZERO 0x00000000 2145 #define NIC_SRAM_SEND_RCB 0x00000100 /* 16 * TG3_BDINFO_... */ 2146 #define NIC_SRAM_RCV_RET_RCB 0x00000200 /* 16 * TG3_BDINFO_... */ 2147 #define NIC_SRAM_STATS_BLK 0x00000300 2148 #define NIC_SRAM_STATUS_BLK 0x00000b00 2149 2150 #define NIC_SRAM_FIRMWARE_MBOX 0x00000b50 2151 #define NIC_SRAM_FIRMWARE_MBOX_MAGIC1 0x4B657654 2152 #define NIC_SRAM_FIRMWARE_MBOX_MAGIC2 0x4861764b /* !dma on linkchg */ 2153 2154 #define NIC_SRAM_DATA_SIG 0x00000b54 2155 #define NIC_SRAM_DATA_SIG_MAGIC 0x4b657654 /* ascii for 'KevT' */ 2156 2157 #define NIC_SRAM_DATA_CFG 0x00000b58 2158 #define NIC_SRAM_DATA_CFG_LED_MODE_MASK 0x0000000c 2159 #define NIC_SRAM_DATA_CFG_LED_MODE_MAC 0x00000000 2160 #define NIC_SRAM_DATA_CFG_LED_MODE_PHY_1 0x00000004 2161 #define NIC_SRAM_DATA_CFG_LED_MODE_PHY_2 0x00000008 2162 #define NIC_SRAM_DATA_CFG_PHY_TYPE_MASK 0x00000030 2163 #define NIC_SRAM_DATA_CFG_PHY_TYPE_UNKNOWN 0x00000000 2164 #define NIC_SRAM_DATA_CFG_PHY_TYPE_COPPER 0x00000010 2165 #define NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER 0x00000020 2166 #define NIC_SRAM_DATA_CFG_WOL_ENABLE 0x00000040 2167 #define NIC_SRAM_DATA_CFG_ASF_ENABLE 0x00000080 2168 #define NIC_SRAM_DATA_CFG_EEPROM_WP 0x00000100 2169 #define NIC_SRAM_DATA_CFG_MINI_PCI 0x00001000 2170 #define NIC_SRAM_DATA_CFG_FIBER_WOL 0x00004000 2171 #define NIC_SRAM_DATA_CFG_NO_GPIO2 0x00100000 2172 #define NIC_SRAM_DATA_CFG_APE_ENABLE 0x00200000 2173 2174 #define NIC_SRAM_DATA_VER 0x00000b5c 2175 #define NIC_SRAM_DATA_VER_SHIFT 16 2176 2177 #define NIC_SRAM_DATA_PHY_ID 0x00000b74 2178 #define NIC_SRAM_DATA_PHY_ID1_MASK 0xffff0000 2179 #define NIC_SRAM_DATA_PHY_ID2_MASK 0x0000ffff 2180 2181 #define NIC_SRAM_FW_CMD_MBOX 0x00000b78 2182 #define FWCMD_NICDRV_ALIVE 0x00000001 2183 #define FWCMD_NICDRV_PAUSE_FW 0x00000002 2184 #define FWCMD_NICDRV_IPV4ADDR_CHG 0x00000003 2185 #define FWCMD_NICDRV_IPV6ADDR_CHG 0x00000004 2186 #define FWCMD_NICDRV_FIX_DMAR 0x00000005 2187 #define FWCMD_NICDRV_FIX_DMAW 0x00000006 2188 #define FWCMD_NICDRV_LINK_UPDATE 0x0000000c 2189 #define FWCMD_NICDRV_ALIVE2 0x0000000d 2190 #define FWCMD_NICDRV_ALIVE3 0x0000000e 2191 #define NIC_SRAM_FW_CMD_LEN_MBOX 0x00000b7c 2192 #define NIC_SRAM_FW_CMD_DATA_MBOX 0x00000b80 2193 #define NIC_SRAM_FW_ASF_STATUS_MBOX 0x00000c00 2194 #define NIC_SRAM_FW_DRV_STATE_MBOX 0x00000c04 2195 #define DRV_STATE_START 0x00000001 2196 #define DRV_STATE_START_DONE 0x80000001 2197 #define DRV_STATE_UNLOAD 0x00000002 2198 #define DRV_STATE_UNLOAD_DONE 0x80000002 2199 #define DRV_STATE_WOL 0x00000003 2200 #define DRV_STATE_SUSPEND 0x00000004 2201 2202 #define NIC_SRAM_FW_RESET_TYPE_MBOX 0x00000c08 2203 2204 #define NIC_SRAM_MAC_ADDR_HIGH_MBOX 0x00000c14 2205 #define NIC_SRAM_MAC_ADDR_LOW_MBOX 0x00000c18 2206 2207 #define NIC_SRAM_WOL_MBOX 0x00000d30 2208 #define WOL_SIGNATURE 0x474c0000 2209 #define WOL_DRV_STATE_SHUTDOWN 0x00000001 2210 #define WOL_DRV_WOL 0x00000002 2211 #define WOL_SET_MAGIC_PKT 0x00000004 2212 2213 #define NIC_SRAM_DATA_CFG_2 0x00000d38 2214 2215 #define NIC_SRAM_DATA_CFG_2_APD_EN 0x00004000 2216 #define SHASTA_EXT_LED_MODE_MASK 0x00018000 2217 #define SHASTA_EXT_LED_LEGACY 0x00000000 2218 #define SHASTA_EXT_LED_SHARED 0x00008000 2219 #define SHASTA_EXT_LED_MAC 0x00010000 2220 #define SHASTA_EXT_LED_COMBO 0x00018000 2221 2222 #define NIC_SRAM_DATA_CFG_3 0x00000d3c 2223 #define NIC_SRAM_ASPM_DEBOUNCE 0x00000002 2224 #define NIC_SRAM_LNK_FLAP_AVOID 0x00400000 2225 #define NIC_SRAM_1G_ON_VAUX_OK 0x00800000 2226 2227 #define NIC_SRAM_DATA_CFG_4 0x00000d60 2228 #define NIC_SRAM_GMII_MODE 0x00000002 2229 #define NIC_SRAM_RGMII_INBAND_DISABLE 0x00000004 2230 #define NIC_SRAM_RGMII_EXT_IBND_RX_EN 0x00000008 2231 #define NIC_SRAM_RGMII_EXT_IBND_TX_EN 0x00000010 2232 2233 #define NIC_SRAM_CPMU_STATUS 0x00000e00 2234 #define NIC_SRAM_CPMUSTAT_SIG 0x0000362c 2235 #define NIC_SRAM_CPMUSTAT_SIG_MSK 0x0000ffff 2236 2237 #define NIC_SRAM_DATA_CFG_5 0x00000e0c 2238 #define NIC_SRAM_DISABLE_1G_HALF_ADV 0x00000002 2239 2240 #define NIC_SRAM_RX_MINI_BUFFER_DESC 0x00001000 2241 2242 #define NIC_SRAM_DMA_DESC_POOL_BASE 0x00002000 2243 #define NIC_SRAM_DMA_DESC_POOL_SIZE 0x00002000 2244 #define NIC_SRAM_TX_BUFFER_DESC 0x00004000 /* 512 entries */ 2245 #define NIC_SRAM_RX_BUFFER_DESC 0x00006000 /* 256 entries */ 2246 #define NIC_SRAM_RX_JUMBO_BUFFER_DESC 0x00007000 /* 256 entries */ 2247 #define NIC_SRAM_MBUF_POOL_BASE 0x00008000 2248 #define NIC_SRAM_MBUF_POOL_SIZE96 0x00018000 2249 #define NIC_SRAM_MBUF_POOL_SIZE64 0x00010000 2250 #define NIC_SRAM_MBUF_POOL_BASE5705 0x00010000 2251 #define NIC_SRAM_MBUF_POOL_SIZE5705 0x0000e000 2252 2253 #define TG3_SRAM_RXCPU_SCRATCH_BASE_57766 0x00030000 2254 #define TG3_SRAM_RXCPU_SCRATCH_SIZE_57766 0x00010000 2255 #define TG3_57766_FW_BASE_ADDR 0x00030000 2256 #define TG3_57766_FW_HANDSHAKE 0x0003fccc 2257 #define TG3_SBROM_IN_SERVICE_LOOP 0x51 2258 2259 #define TG3_SRAM_RX_STD_BDCACHE_SIZE_5700 128 2260 #define TG3_SRAM_RX_STD_BDCACHE_SIZE_5755 64 2261 #define TG3_SRAM_RX_STD_BDCACHE_SIZE_5906 32 2262 2263 #define TG3_SRAM_RX_JMB_BDCACHE_SIZE_5700 64 2264 #define TG3_SRAM_RX_JMB_BDCACHE_SIZE_5717 16 2265 2266 2267 /* Currently this is fixed. */ 2268 #define TG3_PHY_MII_ADDR 0x01 2269 2270 2271 /*** Tigon3 specific PHY MII registers. ***/ 2272 #define MII_TG3_MMD_CTRL 0x0d /* MMD Access Control register */ 2273 #define MII_TG3_MMD_CTRL_DATA_NOINC 0x4000 2274 #define MII_TG3_MMD_ADDRESS 0x0e /* MMD Address Data register */ 2275 2276 #define MII_TG3_EXT_CTRL 0x10 /* Extended control register */ 2277 #define MII_TG3_EXT_CTRL_FIFO_ELASTIC 0x0001 2278 #define MII_TG3_EXT_CTRL_LNK3_LED_MODE 0x0002 2279 #define MII_TG3_EXT_CTRL_FORCE_LED_OFF 0x0008 2280 #define MII_TG3_EXT_CTRL_TBI 0x8000 2281 2282 #define MII_TG3_EXT_STAT 0x11 /* Extended status register */ 2283 #define MII_TG3_EXT_STAT_MDIX 0x2000 2284 #define MII_TG3_EXT_STAT_LPASS 0x0100 2285 2286 #define MII_TG3_RXR_COUNTERS 0x14 /* Local/Remote Receiver Counts */ 2287 #define MII_TG3_DSP_RW_PORT 0x15 /* DSP coefficient read/write port */ 2288 #define MII_TG3_DSP_CONTROL 0x16 /* DSP control register */ 2289 #define MII_TG3_DSP_ADDRESS 0x17 /* DSP address register */ 2290 2291 #define MII_TG3_DSP_TAP1 0x0001 2292 #define MII_TG3_DSP_TAP1_AGCTGT_DFLT 0x0007 2293 #define MII_TG3_DSP_TAP26 0x001a 2294 #define MII_TG3_DSP_TAP26_ALNOKO 0x0001 2295 #define MII_TG3_DSP_TAP26_RMRXSTO 0x0002 2296 #define MII_TG3_DSP_TAP26_OPCSINPT 0x0004 2297 #define MII_TG3_DSP_AADJ1CH0 0x001f 2298 #define MII_TG3_DSP_CH34TP2 0x4022 2299 #define MII_TG3_DSP_CH34TP2_HIBW01 0x01ff 2300 #define MII_TG3_DSP_AADJ1CH3 0x601f 2301 #define MII_TG3_DSP_AADJ1CH3_ADCCKADJ 0x0002 2302 #define MII_TG3_DSP_EXP1_INT_STAT 0x0f01 2303 #define MII_TG3_DSP_EXP8 0x0f08 2304 #define MII_TG3_DSP_EXP8_REJ2MHz 0x0001 2305 #define MII_TG3_DSP_EXP8_AEDW 0x0200 2306 #define MII_TG3_DSP_EXP75 0x0f75 2307 #define MII_TG3_DSP_EXP96 0x0f96 2308 #define MII_TG3_DSP_EXP97 0x0f97 2309 2310 #define MII_TG3_AUX_CTRL 0x18 /* auxiliary control register */ 2311 2312 #define MII_TG3_AUXCTL_SHDWSEL_AUXCTL 0x0000 2313 #define MII_TG3_AUXCTL_ACTL_TX_6DB 0x0400 2314 #define MII_TG3_AUXCTL_ACTL_SMDSP_ENA 0x0800 2315 #define MII_TG3_AUXCTL_ACTL_EXTPKTLEN 0x4000 2316 #define MII_TG3_AUXCTL_ACTL_EXTLOOPBK 0x8000 2317 2318 #define MII_TG3_AUXCTL_SHDWSEL_PWRCTL 0x0002 2319 #define MII_TG3_AUXCTL_PCTL_WOL_EN 0x0008 2320 #define MII_TG3_AUXCTL_PCTL_100TX_LPWR 0x0010 2321 #define MII_TG3_AUXCTL_PCTL_SPR_ISOLATE 0x0020 2322 #define MII_TG3_AUXCTL_PCTL_CL_AB_TXDAC 0x0040 2323 #define MII_TG3_AUXCTL_PCTL_VREG_11V 0x0180 2324 2325 #define MII_TG3_AUXCTL_SHDWSEL_MISCTEST 0x0004 2326 2327 #define MII_TG3_AUXCTL_SHDWSEL_MISC 0x0007 2328 #define MII_TG3_AUXCTL_MISC_WIRESPD_EN 0x0010 2329 #define MII_TG3_AUXCTL_MISC_FORCE_AMDIX 0x0200 2330 #define MII_TG3_AUXCTL_MISC_RDSEL_SHIFT 12 2331 #define MII_TG3_AUXCTL_MISC_WREN 0x8000 2332 2333 2334 #define MII_TG3_AUX_STAT 0x19 /* auxiliary status register */ 2335 #define MII_TG3_AUX_STAT_LPASS 0x0004 2336 #define MII_TG3_AUX_STAT_SPDMASK 0x0700 2337 #define MII_TG3_AUX_STAT_10HALF 0x0100 2338 #define MII_TG3_AUX_STAT_10FULL 0x0200 2339 #define MII_TG3_AUX_STAT_100HALF 0x0300 2340 #define MII_TG3_AUX_STAT_100_4 0x0400 2341 #define MII_TG3_AUX_STAT_100FULL 0x0500 2342 #define MII_TG3_AUX_STAT_1000HALF 0x0600 2343 #define MII_TG3_AUX_STAT_1000FULL 0x0700 2344 #define MII_TG3_AUX_STAT_100 0x0008 2345 #define MII_TG3_AUX_STAT_FULL 0x0001 2346 2347 #define MII_TG3_ISTAT 0x1a /* IRQ status register */ 2348 #define MII_TG3_IMASK 0x1b /* IRQ mask register */ 2349 2350 /* ISTAT/IMASK event bits */ 2351 #define MII_TG3_INT_LINKCHG 0x0002 2352 #define MII_TG3_INT_SPEEDCHG 0x0004 2353 #define MII_TG3_INT_DUPLEXCHG 0x0008 2354 #define MII_TG3_INT_ANEG_PAGE_RX 0x0400 2355 2356 #define MII_TG3_MISC_SHDW 0x1c 2357 #define MII_TG3_MISC_SHDW_WREN 0x8000 2358 2359 #define MII_TG3_MISC_SHDW_APD_WKTM_84MS 0x0001 2360 #define MII_TG3_MISC_SHDW_APD_ENABLE 0x0020 2361 #define MII_TG3_MISC_SHDW_APD_SEL 0x2800 2362 2363 #define MII_TG3_MISC_SHDW_SCR5_C125OE 0x0001 2364 #define MII_TG3_MISC_SHDW_SCR5_DLLAPD 0x0002 2365 #define MII_TG3_MISC_SHDW_SCR5_SDTL 0x0004 2366 #define MII_TG3_MISC_SHDW_SCR5_DLPTLM 0x0008 2367 #define MII_TG3_MISC_SHDW_SCR5_LPED 0x0010 2368 #define MII_TG3_MISC_SHDW_SCR5_SEL 0x1400 2369 2370 #define MII_TG3_TEST1 0x1e 2371 #define MII_TG3_TEST1_TRIM_EN 0x0010 2372 #define MII_TG3_TEST1_CRC_EN 0x8000 2373 2374 /* Clause 45 expansion registers */ 2375 #define TG3_CL45_D7_EEERES_STAT 0x803e 2376 #define TG3_CL45_D7_EEERES_STAT_LP_100TX 0x0002 2377 #define TG3_CL45_D7_EEERES_STAT_LP_1000T 0x0004 2378 2379 2380 /* Fast Ethernet Tranceiver definitions */ 2381 #define MII_TG3_FET_PTEST 0x17 2382 #define MII_TG3_FET_PTEST_TRIM_SEL 0x0010 2383 #define MII_TG3_FET_PTEST_TRIM_2 0x0002 2384 #define MII_TG3_FET_PTEST_FRC_TX_LINK 0x1000 2385 #define MII_TG3_FET_PTEST_FRC_TX_LOCK 0x0800 2386 2387 #define MII_TG3_FET_GEN_STAT 0x1c 2388 #define MII_TG3_FET_GEN_STAT_MDIXSTAT 0x2000 2389 2390 #define MII_TG3_FET_TEST 0x1f 2391 #define MII_TG3_FET_SHADOW_EN 0x0080 2392 2393 #define MII_TG3_FET_SHDW_MISCCTRL 0x10 2394 #define MII_TG3_FET_SHDW_MISCCTRL_MDIX 0x4000 2395 2396 #define MII_TG3_FET_SHDW_AUXMODE4 0x1a 2397 #define MII_TG3_FET_SHDW_AUXMODE4_SBPD 0x0008 2398 2399 #define MII_TG3_FET_SHDW_AUXSTAT2 0x1b 2400 #define MII_TG3_FET_SHDW_AUXSTAT2_APD 0x0020 2401 2402 /* Serdes PHY Register Definitions */ 2403 #define SERDES_TG3_1000X_STATUS 0x14 2404 #define SERDES_TG3_SGMII_MODE 0x0001 2405 #define SERDES_TG3_LINK_UP 0x0002 2406 #define SERDES_TG3_FULL_DUPLEX 0x0004 2407 #define SERDES_TG3_SPEED_100 0x0008 2408 #define SERDES_TG3_SPEED_1000 0x0010 2409 2410 /* APE registers. Accessible through BAR1 */ 2411 #define TG3_APE_GPIO_MSG 0x0008 2412 #define TG3_APE_GPIO_MSG_SHIFT 4 2413 #define TG3_APE_EVENT 0x000c 2414 #define APE_EVENT_1 0x00000001 2415 #define TG3_APE_LOCK_REQ 0x002c 2416 #define APE_LOCK_REQ_DRIVER 0x00001000 2417 #define TG3_APE_LOCK_GRANT 0x004c 2418 #define APE_LOCK_GRANT_DRIVER 0x00001000 2419 #define TG3_APE_OTP_CTRL 0x00e8 2420 #define APE_OTP_CTRL_PROG_EN 0x200000 2421 #define APE_OTP_CTRL_CMD_RD 0x000000 2422 #define APE_OTP_CTRL_START 0x000001 2423 #define TG3_APE_OTP_STATUS 0x00ec 2424 #define APE_OTP_STATUS_CMD_DONE 0x000001 2425 #define TG3_APE_OTP_ADDR 0x00f0 2426 #define APE_OTP_ADDR_CPU_ENABLE 0x80000000 2427 #define TG3_APE_OTP_RD_DATA 0x00f8 2428 2429 #define OTP_ADDRESS_MAGIC0 0x00000050 2430 #define TG3_OTP_MAGIC0_VALID(val) \ 2431 ((((val) & 0xf0000000) == 0xa0000000) ||\ 2432 (((val) & 0x0f000000) == 0x0a000000)) 2433 2434 /* APE shared memory. Accessible through BAR1 */ 2435 #define TG3_APE_SHMEM_BASE 0x4000 2436 #define TG3_APE_SEG_SIG 0x4000 2437 #define APE_SEG_SIG_MAGIC 0x41504521 2438 #define TG3_APE_FW_STATUS 0x400c 2439 #define APE_FW_STATUS_READY 0x00000100 2440 #define TG3_APE_FW_FEATURES 0x4010 2441 #define TG3_APE_FW_FEATURE_NCSI 0x00000002 2442 #define TG3_APE_FW_VERSION 0x4018 2443 #define APE_FW_VERSION_MAJMSK 0xff000000 2444 #define APE_FW_VERSION_MAJSFT 24 2445 #define APE_FW_VERSION_MINMSK 0x00ff0000 2446 #define APE_FW_VERSION_MINSFT 16 2447 #define APE_FW_VERSION_REVMSK 0x0000ff00 2448 #define APE_FW_VERSION_REVSFT 8 2449 #define APE_FW_VERSION_BLDMSK 0x000000ff 2450 #define TG3_APE_SEG_MSG_BUF_OFF 0x401c 2451 #define TG3_APE_SEG_MSG_BUF_LEN 0x4020 2452 #define TG3_APE_HOST_SEG_SIG 0x4200 2453 #define APE_HOST_SEG_SIG_MAGIC 0x484f5354 2454 #define TG3_APE_HOST_SEG_LEN 0x4204 2455 #define APE_HOST_SEG_LEN_MAGIC 0x00000020 2456 #define TG3_APE_HOST_INIT_COUNT 0x4208 2457 #define TG3_APE_HOST_DRIVER_ID 0x420c 2458 #define APE_HOST_DRIVER_ID_LINUX 0xf0000000 2459 #define APE_HOST_DRIVER_ID_MAGIC(maj, min) \ 2460 (APE_HOST_DRIVER_ID_LINUX | (maj & 0xff) << 16 | (min & 0xff) << 8) 2461 #define TG3_APE_HOST_BEHAVIOR 0x4210 2462 #define APE_HOST_BEHAV_NO_PHYLOCK 0x00000001 2463 #define TG3_APE_HOST_HEARTBEAT_INT_MS 0x4214 2464 #define APE_HOST_HEARTBEAT_INT_DISABLE 0 2465 #define APE_HOST_HEARTBEAT_INT_5SEC 5000 2466 #define TG3_APE_HOST_HEARTBEAT_COUNT 0x4218 2467 #define TG3_APE_HOST_DRVR_STATE 0x421c 2468 #define TG3_APE_HOST_DRVR_STATE_START 0x00000001 2469 #define TG3_APE_HOST_DRVR_STATE_UNLOAD 0x00000002 2470 #define TG3_APE_HOST_DRVR_STATE_WOL 0x00000003 2471 #define TG3_APE_HOST_WOL_SPEED 0x4224 2472 #define TG3_APE_HOST_WOL_SPEED_AUTO 0x00008000 2473 2474 #define TG3_APE_EVENT_STATUS 0x4300 2475 2476 #define APE_EVENT_STATUS_DRIVER_EVNT 0x00000010 2477 #define APE_EVENT_STATUS_STATE_CHNGE 0x00000500 2478 #define APE_EVENT_STATUS_SCRTCHPD_READ 0x00001600 2479 #define APE_EVENT_STATUS_SCRTCHPD_WRITE 0x00001700 2480 #define APE_EVENT_STATUS_STATE_START 0x00010000 2481 #define APE_EVENT_STATUS_STATE_UNLOAD 0x00020000 2482 #define APE_EVENT_STATUS_STATE_WOL 0x00030000 2483 #define APE_EVENT_STATUS_STATE_SUSPEND 0x00040000 2484 #define APE_EVENT_STATUS_EVENT_PENDING 0x80000000 2485 2486 #define TG3_APE_PER_LOCK_REQ 0x8400 2487 #define APE_LOCK_PER_REQ_DRIVER 0x00001000 2488 #define TG3_APE_PER_LOCK_GRANT 0x8420 2489 #define APE_PER_LOCK_GRANT_DRIVER 0x00001000 2490 2491 /* APE convenience enumerations. */ 2492 #define TG3_APE_LOCK_PHY0 0 2493 #define TG3_APE_LOCK_GRC 1 2494 #define TG3_APE_LOCK_PHY1 2 2495 #define TG3_APE_LOCK_PHY2 3 2496 #define TG3_APE_LOCK_MEM 4 2497 #define TG3_APE_LOCK_PHY3 5 2498 #define TG3_APE_LOCK_GPIO 7 2499 2500 #define TG3_EEPROM_SB_F1R2_MBA_OFF 0x10 2501 2502 2503 /* There are two ways to manage the TX descriptors on the tigon3. 2504 * Either the descriptors are in host DMA'able memory, or they 2505 * exist only in the cards on-chip SRAM. All 16 send bds are under 2506 * the same mode, they may not be configured individually. 2507 * 2508 * This driver always uses host memory TX descriptors. 2509 * 2510 * To use host memory TX descriptors: 2511 * 1) Set GRC_MODE_HOST_SENDBDS in GRC_MODE register. 2512 * Make sure GRC_MODE_4X_NIC_SEND_RINGS is clear. 2513 * 2) Allocate DMA'able memory. 2514 * 3) In NIC_SRAM_SEND_RCB (of desired index) of on-chip SRAM: 2515 * a) Set TG3_BDINFO_HOST_ADDR to DMA address of memory 2516 * obtained in step 2 2517 * b) Set TG3_BDINFO_NIC_ADDR to NIC_SRAM_TX_BUFFER_DESC. 2518 * c) Set len field of TG3_BDINFO_MAXLEN_FLAGS to number 2519 * of TX descriptors. Leave flags field clear. 2520 * 4) Access TX descriptors via host memory. The chip 2521 * will refetch into local SRAM as needed when producer 2522 * index mailboxes are updated. 2523 * 2524 * To use on-chip TX descriptors: 2525 * 1) Set GRC_MODE_4X_NIC_SEND_RINGS in GRC_MODE register. 2526 * Make sure GRC_MODE_HOST_SENDBDS is clear. 2527 * 2) In NIC_SRAM_SEND_RCB (of desired index) of on-chip SRAM: 2528 * a) Set TG3_BDINFO_HOST_ADDR to zero. 2529 * b) Set TG3_BDINFO_NIC_ADDR to NIC_SRAM_TX_BUFFER_DESC 2530 * c) TG3_BDINFO_MAXLEN_FLAGS is don't care. 2531 * 3) Access TX descriptors directly in on-chip SRAM 2532 * using normal {read,write}l(). (and not using 2533 * pointer dereferencing of ioremap()'d memory like 2534 * the broken Broadcom driver does) 2535 * 2536 * Note that BDINFO_FLAGS_DISABLED should be set in the flags field of 2537 * TG3_BDINFO_MAXLEN_FLAGS of all unused SEND_RCB indices. 2538 */ 2539 struct tg3_tx_buffer_desc { 2540 u32 addr_hi; 2541 u32 addr_lo; 2542 2543 u32 len_flags; 2544 #define TXD_FLAG_TCPUDP_CSUM 0x0001 2545 #define TXD_FLAG_IP_CSUM 0x0002 2546 #define TXD_FLAG_END 0x0004 2547 #define TXD_FLAG_IP_FRAG 0x0008 2548 #define TXD_FLAG_JMB_PKT 0x0008 2549 #define TXD_FLAG_IP_FRAG_END 0x0010 2550 #define TXD_FLAG_HWTSTAMP 0x0020 2551 #define TXD_FLAG_VLAN 0x0040 2552 #define TXD_FLAG_COAL_NOW 0x0080 2553 #define TXD_FLAG_CPU_PRE_DMA 0x0100 2554 #define TXD_FLAG_CPU_POST_DMA 0x0200 2555 #define TXD_FLAG_ADD_SRC_ADDR 0x1000 2556 #define TXD_FLAG_CHOOSE_SRC_ADDR 0x6000 2557 #define TXD_FLAG_NO_CRC 0x8000 2558 #define TXD_LEN_SHIFT 16 2559 2560 u32 vlan_tag; 2561 #define TXD_VLAN_TAG_SHIFT 0 2562 #define TXD_MSS_SHIFT 16 2563 }; 2564 2565 #define TXD_ADDR 0x00UL /* 64-bit */ 2566 #define TXD_LEN_FLAGS 0x08UL /* 32-bit (upper 16-bits are len) */ 2567 #define TXD_VLAN_TAG 0x0cUL /* 32-bit (upper 16-bits are tag) */ 2568 #define TXD_SIZE 0x10UL 2569 2570 struct tg3_rx_buffer_desc { 2571 u32 addr_hi; 2572 u32 addr_lo; 2573 2574 u32 idx_len; 2575 #define RXD_IDX_MASK 0xffff0000 2576 #define RXD_IDX_SHIFT 16 2577 #define RXD_LEN_MASK 0x0000ffff 2578 #define RXD_LEN_SHIFT 0 2579 2580 u32 type_flags; 2581 #define RXD_TYPE_SHIFT 16 2582 #define RXD_FLAGS_SHIFT 0 2583 2584 #define RXD_FLAG_END 0x0004 2585 #define RXD_FLAG_MINI 0x0800 2586 #define RXD_FLAG_JUMBO 0x0020 2587 #define RXD_FLAG_VLAN 0x0040 2588 #define RXD_FLAG_ERROR 0x0400 2589 #define RXD_FLAG_IP_CSUM 0x1000 2590 #define RXD_FLAG_TCPUDP_CSUM 0x2000 2591 #define RXD_FLAG_IS_TCP 0x4000 2592 #define RXD_FLAG_PTPSTAT_MASK 0x0210 2593 #define RXD_FLAG_PTPSTAT_PTPV1 0x0010 2594 #define RXD_FLAG_PTPSTAT_PTPV2 0x0200 2595 2596 u32 ip_tcp_csum; 2597 #define RXD_IPCSUM_MASK 0xffff0000 2598 #define RXD_IPCSUM_SHIFT 16 2599 #define RXD_TCPCSUM_MASK 0x0000ffff 2600 #define RXD_TCPCSUM_SHIFT 0 2601 2602 u32 err_vlan; 2603 2604 #define RXD_VLAN_MASK 0x0000ffff 2605 2606 #define RXD_ERR_BAD_CRC 0x00010000 2607 #define RXD_ERR_COLLISION 0x00020000 2608 #define RXD_ERR_LINK_LOST 0x00040000 2609 #define RXD_ERR_PHY_DECODE 0x00080000 2610 #define RXD_ERR_ODD_NIBBLE_RCVD_MII 0x00100000 2611 #define RXD_ERR_MAC_ABRT 0x00200000 2612 #define RXD_ERR_TOO_SMALL 0x00400000 2613 #define RXD_ERR_NO_RESOURCES 0x00800000 2614 #define RXD_ERR_HUGE_FRAME 0x01000000 2615 2616 #define RXD_ERR_MASK (RXD_ERR_BAD_CRC | RXD_ERR_COLLISION | \ 2617 RXD_ERR_LINK_LOST | RXD_ERR_PHY_DECODE | \ 2618 RXD_ERR_MAC_ABRT | RXD_ERR_TOO_SMALL | \ 2619 RXD_ERR_NO_RESOURCES | RXD_ERR_HUGE_FRAME) 2620 2621 u32 reserved; 2622 u32 opaque; 2623 #define RXD_OPAQUE_INDEX_MASK 0x0000ffff 2624 #define RXD_OPAQUE_INDEX_SHIFT 0 2625 #define RXD_OPAQUE_RING_STD 0x00010000 2626 #define RXD_OPAQUE_RING_JUMBO 0x00020000 2627 #define RXD_OPAQUE_RING_MINI 0x00040000 2628 #define RXD_OPAQUE_RING_MASK 0x00070000 2629 }; 2630 2631 struct tg3_ext_rx_buffer_desc { 2632 struct { 2633 u32 addr_hi; 2634 u32 addr_lo; 2635 } addrlist[3]; 2636 u32 len2_len1; 2637 u32 resv_len3; 2638 struct tg3_rx_buffer_desc std; 2639 }; 2640 2641 /* We only use this when testing out the DMA engine 2642 * at probe time. This is the internal format of buffer 2643 * descriptors used by the chip at NIC_SRAM_DMA_DESCS. 2644 */ 2645 struct tg3_internal_buffer_desc { 2646 u32 addr_hi; 2647 u32 addr_lo; 2648 u32 nic_mbuf; 2649 /* XXX FIX THIS */ 2650 #ifdef __BIG_ENDIAN 2651 u16 cqid_sqid; 2652 u16 len; 2653 #else 2654 u16 len; 2655 u16 cqid_sqid; 2656 #endif 2657 u32 flags; 2658 u32 __cookie1; 2659 u32 __cookie2; 2660 u32 __cookie3; 2661 }; 2662 2663 #define TG3_HW_STATUS_SIZE 0x50 2664 struct tg3_hw_status { 2665 u32 status; 2666 #define SD_STATUS_UPDATED 0x00000001 2667 #define SD_STATUS_LINK_CHG 0x00000002 2668 #define SD_STATUS_ERROR 0x00000004 2669 2670 u32 status_tag; 2671 2672 #ifdef __BIG_ENDIAN 2673 u16 rx_consumer; 2674 u16 rx_jumbo_consumer; 2675 #else 2676 u16 rx_jumbo_consumer; 2677 u16 rx_consumer; 2678 #endif 2679 2680 #ifdef __BIG_ENDIAN 2681 u16 reserved; 2682 u16 rx_mini_consumer; 2683 #else 2684 u16 rx_mini_consumer; 2685 u16 reserved; 2686 #endif 2687 struct { 2688 #ifdef __BIG_ENDIAN 2689 u16 tx_consumer; 2690 u16 rx_producer; 2691 #else 2692 u16 rx_producer; 2693 u16 tx_consumer; 2694 #endif 2695 } idx[16]; 2696 }; 2697 2698 typedef struct { 2699 u32 high, low; 2700 } tg3_stat64_t; 2701 2702 struct tg3_hw_stats { 2703 u8 __reserved0[0x400-0x300]; 2704 2705 /* Statistics maintained by Receive MAC. */ 2706 tg3_stat64_t rx_octets; 2707 u64 __reserved1; 2708 tg3_stat64_t rx_fragments; 2709 tg3_stat64_t rx_ucast_packets; 2710 tg3_stat64_t rx_mcast_packets; 2711 tg3_stat64_t rx_bcast_packets; 2712 tg3_stat64_t rx_fcs_errors; 2713 tg3_stat64_t rx_align_errors; 2714 tg3_stat64_t rx_xon_pause_rcvd; 2715 tg3_stat64_t rx_xoff_pause_rcvd; 2716 tg3_stat64_t rx_mac_ctrl_rcvd; 2717 tg3_stat64_t rx_xoff_entered; 2718 tg3_stat64_t rx_frame_too_long_errors; 2719 tg3_stat64_t rx_jabbers; 2720 tg3_stat64_t rx_undersize_packets; 2721 tg3_stat64_t rx_in_length_errors; 2722 tg3_stat64_t rx_out_length_errors; 2723 tg3_stat64_t rx_64_or_less_octet_packets; 2724 tg3_stat64_t rx_65_to_127_octet_packets; 2725 tg3_stat64_t rx_128_to_255_octet_packets; 2726 tg3_stat64_t rx_256_to_511_octet_packets; 2727 tg3_stat64_t rx_512_to_1023_octet_packets; 2728 tg3_stat64_t rx_1024_to_1522_octet_packets; 2729 tg3_stat64_t rx_1523_to_2047_octet_packets; 2730 tg3_stat64_t rx_2048_to_4095_octet_packets; 2731 tg3_stat64_t rx_4096_to_8191_octet_packets; 2732 tg3_stat64_t rx_8192_to_9022_octet_packets; 2733 2734 u64 __unused0[37]; 2735 2736 /* Statistics maintained by Transmit MAC. */ 2737 tg3_stat64_t tx_octets; 2738 u64 __reserved2; 2739 tg3_stat64_t tx_collisions; 2740 tg3_stat64_t tx_xon_sent; 2741 tg3_stat64_t tx_xoff_sent; 2742 tg3_stat64_t tx_flow_control; 2743 tg3_stat64_t tx_mac_errors; 2744 tg3_stat64_t tx_single_collisions; 2745 tg3_stat64_t tx_mult_collisions; 2746 tg3_stat64_t tx_deferred; 2747 u64 __reserved3; 2748 tg3_stat64_t tx_excessive_collisions; 2749 tg3_stat64_t tx_late_collisions; 2750 tg3_stat64_t tx_collide_2times; 2751 tg3_stat64_t tx_collide_3times; 2752 tg3_stat64_t tx_collide_4times; 2753 tg3_stat64_t tx_collide_5times; 2754 tg3_stat64_t tx_collide_6times; 2755 tg3_stat64_t tx_collide_7times; 2756 tg3_stat64_t tx_collide_8times; 2757 tg3_stat64_t tx_collide_9times; 2758 tg3_stat64_t tx_collide_10times; 2759 tg3_stat64_t tx_collide_11times; 2760 tg3_stat64_t tx_collide_12times; 2761 tg3_stat64_t tx_collide_13times; 2762 tg3_stat64_t tx_collide_14times; 2763 tg3_stat64_t tx_collide_15times; 2764 tg3_stat64_t tx_ucast_packets; 2765 tg3_stat64_t tx_mcast_packets; 2766 tg3_stat64_t tx_bcast_packets; 2767 tg3_stat64_t tx_carrier_sense_errors; 2768 tg3_stat64_t tx_discards; 2769 tg3_stat64_t tx_errors; 2770 2771 u64 __unused1[31]; 2772 2773 /* Statistics maintained by Receive List Placement. */ 2774 tg3_stat64_t COS_rx_packets[16]; 2775 tg3_stat64_t COS_rx_filter_dropped; 2776 tg3_stat64_t dma_writeq_full; 2777 tg3_stat64_t dma_write_prioq_full; 2778 tg3_stat64_t rxbds_empty; 2779 tg3_stat64_t rx_discards; 2780 tg3_stat64_t rx_errors; 2781 tg3_stat64_t rx_threshold_hit; 2782 2783 u64 __unused2[9]; 2784 2785 /* Statistics maintained by Send Data Initiator. */ 2786 tg3_stat64_t COS_out_packets[16]; 2787 tg3_stat64_t dma_readq_full; 2788 tg3_stat64_t dma_read_prioq_full; 2789 tg3_stat64_t tx_comp_queue_full; 2790 2791 /* Statistics maintained by Host Coalescing. */ 2792 tg3_stat64_t ring_set_send_prod_index; 2793 tg3_stat64_t ring_status_update; 2794 tg3_stat64_t nic_irqs; 2795 tg3_stat64_t nic_avoided_irqs; 2796 tg3_stat64_t nic_tx_threshold_hit; 2797 2798 /* NOT a part of the hardware statistics block format. 2799 * These stats are here as storage for tg3_periodic_fetch_stats(). 2800 */ 2801 tg3_stat64_t mbuf_lwm_thresh_hit; 2802 2803 u8 __reserved4[0xb00-0x9c8]; 2804 }; 2805 2806 #define TG3_SD_NUM_RECS 3 2807 #define TG3_OCIR_LEN (sizeof(struct tg3_ocir)) 2808 #define TG3_OCIR_SIG_MAGIC 0x5253434f 2809 #define TG3_OCIR_FLAG_ACTIVE 0x00000001 2810 2811 #define TG3_TEMP_CAUTION_OFFSET 0xc8 2812 #define TG3_TEMP_MAX_OFFSET 0xcc 2813 #define TG3_TEMP_SENSOR_OFFSET 0xd4 2814 2815 2816 struct tg3_ocir { 2817 u32 signature; 2818 u16 version_flags; 2819 u16 refresh_int; 2820 u32 refresh_tmr; 2821 u32 update_tmr; 2822 u32 dst_base_addr; 2823 u16 src_hdr_offset; 2824 u16 src_hdr_length; 2825 u16 src_data_offset; 2826 u16 src_data_length; 2827 u16 dst_hdr_offset; 2828 u16 dst_data_offset; 2829 u16 dst_reg_upd_offset; 2830 u16 dst_sem_offset; 2831 u32 reserved1[2]; 2832 u32 port0_flags; 2833 u32 port1_flags; 2834 u32 port2_flags; 2835 u32 port3_flags; 2836 u32 reserved2[1]; 2837 }; 2838 2839 2840 /* 'mapping' is superfluous as the chip does not write into 2841 * the tx/rx post rings so we could just fetch it from there. 2842 * But the cache behavior is better how we are doing it now. 2843 * 2844 * This driver uses new build_skb() API : 2845 * RX ring buffer contains pointer to kmalloc() data only, 2846 * skb are built only after Hardware filled the frame. 2847 */ 2848 struct ring_info { 2849 u8 *data; 2850 DEFINE_DMA_UNMAP_ADDR(mapping); 2851 }; 2852 2853 struct tg3_tx_ring_info { 2854 struct sk_buff *skb; 2855 DEFINE_DMA_UNMAP_ADDR(mapping); 2856 bool fragmented; 2857 }; 2858 2859 struct tg3_link_config { 2860 /* Describes what we're trying to get. */ 2861 u32 advertising; 2862 u16 speed; 2863 u8 duplex; 2864 u8 autoneg; 2865 u8 flowctrl; 2866 2867 /* Describes what we actually have. */ 2868 u8 active_flowctrl; 2869 2870 u8 active_duplex; 2871 u16 active_speed; 2872 u32 rmt_adv; 2873 }; 2874 2875 struct tg3_bufmgr_config { 2876 u32 mbuf_read_dma_low_water; 2877 u32 mbuf_mac_rx_low_water; 2878 u32 mbuf_high_water; 2879 2880 u32 mbuf_read_dma_low_water_jumbo; 2881 u32 mbuf_mac_rx_low_water_jumbo; 2882 u32 mbuf_high_water_jumbo; 2883 2884 u32 dma_low_water; 2885 u32 dma_high_water; 2886 }; 2887 2888 struct tg3_ethtool_stats { 2889 /* Statistics maintained by Receive MAC. */ 2890 u64 rx_octets; 2891 u64 rx_fragments; 2892 u64 rx_ucast_packets; 2893 u64 rx_mcast_packets; 2894 u64 rx_bcast_packets; 2895 u64 rx_fcs_errors; 2896 u64 rx_align_errors; 2897 u64 rx_xon_pause_rcvd; 2898 u64 rx_xoff_pause_rcvd; 2899 u64 rx_mac_ctrl_rcvd; 2900 u64 rx_xoff_entered; 2901 u64 rx_frame_too_long_errors; 2902 u64 rx_jabbers; 2903 u64 rx_undersize_packets; 2904 u64 rx_in_length_errors; 2905 u64 rx_out_length_errors; 2906 u64 rx_64_or_less_octet_packets; 2907 u64 rx_65_to_127_octet_packets; 2908 u64 rx_128_to_255_octet_packets; 2909 u64 rx_256_to_511_octet_packets; 2910 u64 rx_512_to_1023_octet_packets; 2911 u64 rx_1024_to_1522_octet_packets; 2912 u64 rx_1523_to_2047_octet_packets; 2913 u64 rx_2048_to_4095_octet_packets; 2914 u64 rx_4096_to_8191_octet_packets; 2915 u64 rx_8192_to_9022_octet_packets; 2916 2917 /* Statistics maintained by Transmit MAC. */ 2918 u64 tx_octets; 2919 u64 tx_collisions; 2920 u64 tx_xon_sent; 2921 u64 tx_xoff_sent; 2922 u64 tx_flow_control; 2923 u64 tx_mac_errors; 2924 u64 tx_single_collisions; 2925 u64 tx_mult_collisions; 2926 u64 tx_deferred; 2927 u64 tx_excessive_collisions; 2928 u64 tx_late_collisions; 2929 u64 tx_collide_2times; 2930 u64 tx_collide_3times; 2931 u64 tx_collide_4times; 2932 u64 tx_collide_5times; 2933 u64 tx_collide_6times; 2934 u64 tx_collide_7times; 2935 u64 tx_collide_8times; 2936 u64 tx_collide_9times; 2937 u64 tx_collide_10times; 2938 u64 tx_collide_11times; 2939 u64 tx_collide_12times; 2940 u64 tx_collide_13times; 2941 u64 tx_collide_14times; 2942 u64 tx_collide_15times; 2943 u64 tx_ucast_packets; 2944 u64 tx_mcast_packets; 2945 u64 tx_bcast_packets; 2946 u64 tx_carrier_sense_errors; 2947 u64 tx_discards; 2948 u64 tx_errors; 2949 2950 /* Statistics maintained by Receive List Placement. */ 2951 u64 dma_writeq_full; 2952 u64 dma_write_prioq_full; 2953 u64 rxbds_empty; 2954 u64 rx_discards; 2955 u64 rx_errors; 2956 u64 rx_threshold_hit; 2957 2958 /* Statistics maintained by Send Data Initiator. */ 2959 u64 dma_readq_full; 2960 u64 dma_read_prioq_full; 2961 u64 tx_comp_queue_full; 2962 2963 /* Statistics maintained by Host Coalescing. */ 2964 u64 ring_set_send_prod_index; 2965 u64 ring_status_update; 2966 u64 nic_irqs; 2967 u64 nic_avoided_irqs; 2968 u64 nic_tx_threshold_hit; 2969 2970 u64 mbuf_lwm_thresh_hit; 2971 }; 2972 2973 struct tg3_rx_prodring_set { 2974 u32 rx_std_prod_idx; 2975 u32 rx_std_cons_idx; 2976 u32 rx_jmb_prod_idx; 2977 u32 rx_jmb_cons_idx; 2978 struct tg3_rx_buffer_desc *rx_std; 2979 struct tg3_ext_rx_buffer_desc *rx_jmb; 2980 struct ring_info *rx_std_buffers; 2981 struct ring_info *rx_jmb_buffers; 2982 dma_addr_t rx_std_mapping; 2983 dma_addr_t rx_jmb_mapping; 2984 }; 2985 2986 #define TG3_RSS_MAX_NUM_QS 4 2987 #define TG3_IRQ_MAX_VECS_RSS (TG3_RSS_MAX_NUM_QS + 1) 2988 #define TG3_IRQ_MAX_VECS TG3_IRQ_MAX_VECS_RSS 2989 2990 struct tg3_napi { 2991 struct napi_struct napi ____cacheline_aligned; 2992 struct tg3 *tp; 2993 struct tg3_hw_status *hw_status; 2994 2995 u32 chk_msi_cnt; 2996 u32 last_tag; 2997 u32 last_irq_tag; 2998 u32 int_mbox; 2999 u32 coal_now; 3000 3001 u32 consmbox ____cacheline_aligned; 3002 u32 rx_rcb_ptr; 3003 u32 last_rx_cons; 3004 u16 *rx_rcb_prod_idx; 3005 struct tg3_rx_prodring_set prodring; 3006 struct tg3_rx_buffer_desc *rx_rcb; 3007 3008 u32 tx_prod ____cacheline_aligned; 3009 u32 tx_cons; 3010 u32 tx_pending; 3011 u32 last_tx_cons; 3012 u32 prodmbox; 3013 struct tg3_tx_buffer_desc *tx_ring; 3014 struct tg3_tx_ring_info *tx_buffers; 3015 3016 dma_addr_t status_mapping; 3017 dma_addr_t rx_rcb_mapping; 3018 dma_addr_t tx_desc_mapping; 3019 3020 char irq_lbl[IFNAMSIZ]; 3021 unsigned int irq_vec; 3022 }; 3023 3024 enum TG3_FLAGS { 3025 TG3_FLAG_TAGGED_STATUS = 0, 3026 TG3_FLAG_TXD_MBOX_HWBUG, 3027 TG3_FLAG_USE_LINKCHG_REG, 3028 TG3_FLAG_ERROR_PROCESSED, 3029 TG3_FLAG_ENABLE_ASF, 3030 TG3_FLAG_ASPM_WORKAROUND, 3031 TG3_FLAG_POLL_SERDES, 3032 TG3_FLAG_POLL_CPMU_LINK, 3033 TG3_FLAG_MBOX_WRITE_REORDER, 3034 TG3_FLAG_PCIX_TARGET_HWBUG, 3035 TG3_FLAG_WOL_SPEED_100MB, 3036 TG3_FLAG_WOL_ENABLE, 3037 TG3_FLAG_EEPROM_WRITE_PROT, 3038 TG3_FLAG_NVRAM, 3039 TG3_FLAG_NVRAM_BUFFERED, 3040 TG3_FLAG_SUPPORT_MSI, 3041 TG3_FLAG_SUPPORT_MSIX, 3042 TG3_FLAG_USING_MSI, 3043 TG3_FLAG_USING_MSIX, 3044 TG3_FLAG_PCIX_MODE, 3045 TG3_FLAG_PCI_HIGH_SPEED, 3046 TG3_FLAG_PCI_32BIT, 3047 TG3_FLAG_SRAM_USE_CONFIG, 3048 TG3_FLAG_TX_RECOVERY_PENDING, 3049 TG3_FLAG_WOL_CAP, 3050 TG3_FLAG_JUMBO_RING_ENABLE, 3051 TG3_FLAG_PAUSE_AUTONEG, 3052 TG3_FLAG_CPMU_PRESENT, 3053 TG3_FLAG_40BIT_DMA_BUG, 3054 TG3_FLAG_BROKEN_CHECKSUMS, 3055 TG3_FLAG_JUMBO_CAPABLE, 3056 TG3_FLAG_CHIP_RESETTING, 3057 TG3_FLAG_INIT_COMPLETE, 3058 TG3_FLAG_MAX_RXPEND_64, 3059 TG3_FLAG_PCI_EXPRESS, /* BCM5785 + pci_is_pcie() */ 3060 TG3_FLAG_ASF_NEW_HANDSHAKE, 3061 TG3_FLAG_HW_AUTONEG, 3062 TG3_FLAG_IS_NIC, 3063 TG3_FLAG_FLASH, 3064 TG3_FLAG_FW_TSO, 3065 TG3_FLAG_HW_TSO_1, 3066 TG3_FLAG_HW_TSO_2, 3067 TG3_FLAG_HW_TSO_3, 3068 TG3_FLAG_TSO_CAPABLE, 3069 TG3_FLAG_TSO_BUG, 3070 TG3_FLAG_ICH_WORKAROUND, 3071 TG3_FLAG_1SHOT_MSI, 3072 TG3_FLAG_NO_FWARE_REPORTED, 3073 TG3_FLAG_NO_NVRAM_ADDR_TRANS, 3074 TG3_FLAG_ENABLE_APE, 3075 TG3_FLAG_PROTECTED_NVRAM, 3076 TG3_FLAG_5701_DMA_BUG, 3077 TG3_FLAG_USE_PHYLIB, 3078 TG3_FLAG_MDIOBUS_INITED, 3079 TG3_FLAG_LRG_PROD_RING_CAP, 3080 TG3_FLAG_RGMII_INBAND_DISABLE, 3081 TG3_FLAG_RGMII_EXT_IBND_RX_EN, 3082 TG3_FLAG_RGMII_EXT_IBND_TX_EN, 3083 TG3_FLAG_CLKREQ_BUG, 3084 TG3_FLAG_NO_NVRAM, 3085 TG3_FLAG_ENABLE_RSS, 3086 TG3_FLAG_ENABLE_TSS, 3087 TG3_FLAG_SHORT_DMA_BUG, 3088 TG3_FLAG_USE_JUMBO_BDFLAG, 3089 TG3_FLAG_L1PLLPD_EN, 3090 TG3_FLAG_APE_HAS_NCSI, 3091 TG3_FLAG_TX_TSTAMP_EN, 3092 TG3_FLAG_4K_FIFO_LIMIT, 3093 TG3_FLAG_5719_5720_RDMA_BUG, 3094 TG3_FLAG_RESET_TASK_PENDING, 3095 TG3_FLAG_PTP_CAPABLE, 3096 TG3_FLAG_5705_PLUS, 3097 TG3_FLAG_IS_5788, 3098 TG3_FLAG_5750_PLUS, 3099 TG3_FLAG_5780_CLASS, 3100 TG3_FLAG_5755_PLUS, 3101 TG3_FLAG_57765_PLUS, 3102 TG3_FLAG_57765_CLASS, 3103 TG3_FLAG_5717_PLUS, 3104 TG3_FLAG_IS_SSB_CORE, 3105 TG3_FLAG_FLUSH_POSTED_WRITES, 3106 TG3_FLAG_ROBOSWITCH, 3107 TG3_FLAG_ONE_DMA_AT_ONCE, 3108 TG3_FLAG_RGMII_MODE, 3109 3110 /* Add new flags before this comment and TG3_FLAG_NUMBER_OF_FLAGS */ 3111 TG3_FLAG_NUMBER_OF_FLAGS, /* Last entry in enum TG3_FLAGS */ 3112 }; 3113 3114 struct tg3_firmware_hdr { 3115 __be32 version; /* unused for fragments */ 3116 __be32 base_addr; 3117 __be32 len; 3118 }; 3119 #define TG3_FW_HDR_LEN (sizeof(struct tg3_firmware_hdr)) 3120 3121 struct tg3 { 3122 /* begin "general, frequently-used members" cacheline section */ 3123 3124 /* If the IRQ handler (which runs lockless) needs to be 3125 * quiesced, the following bitmask state is used. The 3126 * SYNC flag is set by non-IRQ context code to initiate 3127 * the quiescence. 3128 * 3129 * When the IRQ handler notices that SYNC is set, it 3130 * disables interrupts and returns. 3131 * 3132 * When all outstanding IRQ handlers have returned after 3133 * the SYNC flag has been set, the setter can be assured 3134 * that interrupts will no longer get run. 3135 * 3136 * In this way all SMP driver locks are never acquired 3137 * in hw IRQ context, only sw IRQ context or lower. 3138 */ 3139 unsigned int irq_sync; 3140 3141 /* SMP locking strategy: 3142 * 3143 * lock: Held during reset, PHY access, timer, and when 3144 * updating tg3_flags. 3145 * 3146 * netif_tx_lock: Held during tg3_start_xmit. tg3_tx holds 3147 * netif_tx_lock when it needs to call 3148 * netif_wake_queue. 3149 * 3150 * Both of these locks are to be held with BH safety. 3151 * 3152 * Because the IRQ handler, tg3_poll, and tg3_start_xmit 3153 * are running lockless, it is necessary to completely 3154 * quiesce the chip with tg3_netif_stop and tg3_full_lock 3155 * before reconfiguring the device. 3156 * 3157 * indirect_lock: Held when accessing registers indirectly 3158 * with IRQ disabling. 3159 */ 3160 spinlock_t lock; 3161 spinlock_t indirect_lock; 3162 3163 u32 (*read32) (struct tg3 *, u32); 3164 void (*write32) (struct tg3 *, u32, u32); 3165 u32 (*read32_mbox) (struct tg3 *, u32); 3166 void (*write32_mbox) (struct tg3 *, u32, 3167 u32); 3168 void __iomem *regs; 3169 void __iomem *aperegs; 3170 struct net_device *dev; 3171 struct pci_dev *pdev; 3172 3173 u32 coal_now; 3174 u32 msg_enable; 3175 3176 struct ptp_clock_info ptp_info; 3177 struct ptp_clock *ptp_clock; 3178 s64 ptp_adjust; 3179 3180 /* begin "tx thread" cacheline section */ 3181 void (*write32_tx_mbox) (struct tg3 *, u32, 3182 u32); 3183 u32 dma_limit; 3184 u32 txq_req; 3185 u32 txq_cnt; 3186 u32 txq_max; 3187 3188 /* begin "rx thread" cacheline section */ 3189 struct tg3_napi napi[TG3_IRQ_MAX_VECS]; 3190 void (*write32_rx_mbox) (struct tg3 *, u32, 3191 u32); 3192 u32 rx_copy_thresh; 3193 u32 rx_std_ring_mask; 3194 u32 rx_jmb_ring_mask; 3195 u32 rx_ret_ring_mask; 3196 u32 rx_pending; 3197 u32 rx_jumbo_pending; 3198 u32 rx_std_max_post; 3199 u32 rx_offset; 3200 u32 rx_pkt_map_sz; 3201 u32 rxq_req; 3202 u32 rxq_cnt; 3203 u32 rxq_max; 3204 bool rx_refill; 3205 3206 3207 /* begin "everything else" cacheline(s) section */ 3208 unsigned long rx_dropped; 3209 unsigned long tx_dropped; 3210 struct rtnl_link_stats64 net_stats_prev; 3211 struct tg3_ethtool_stats estats_prev; 3212 3213 DECLARE_BITMAP(tg3_flags, TG3_FLAG_NUMBER_OF_FLAGS); 3214 3215 union { 3216 unsigned long phy_crc_errors; 3217 unsigned long last_event_jiffies; 3218 }; 3219 3220 struct timer_list timer; 3221 u16 timer_counter; 3222 u16 timer_multiplier; 3223 u32 timer_offset; 3224 u16 asf_counter; 3225 u16 asf_multiplier; 3226 3227 /* 1 second counter for transient serdes link events */ 3228 u32 serdes_counter; 3229 #define SERDES_AN_TIMEOUT_5704S 2 3230 #define SERDES_PARALLEL_DET_TIMEOUT 1 3231 #define SERDES_AN_TIMEOUT_5714S 1 3232 3233 struct tg3_link_config link_config; 3234 struct tg3_bufmgr_config bufmgr_config; 3235 3236 /* cache h/w values, often passed straight to h/w */ 3237 u32 rx_mode; 3238 u32 tx_mode; 3239 u32 mac_mode; 3240 u32 mi_mode; 3241 u32 misc_host_ctrl; 3242 u32 grc_mode; 3243 u32 grc_local_ctrl; 3244 u32 dma_rwctrl; 3245 u32 coalesce_mode; 3246 u32 pwrmgmt_thresh; 3247 u32 rxptpctl; 3248 3249 /* PCI block */ 3250 u32 pci_chip_rev_id; 3251 u16 pci_cmd; 3252 u8 pci_cacheline_sz; 3253 u8 pci_lat_timer; 3254 3255 int pci_fn; 3256 int msi_cap; 3257 int pcix_cap; 3258 int pcie_readrq; 3259 3260 struct mii_bus *mdio_bus; 3261 int mdio_irq[PHY_MAX_ADDR]; 3262 int old_link; 3263 3264 u8 phy_addr; 3265 u8 phy_ape_lock; 3266 3267 /* PHY info */ 3268 u32 phy_id; 3269 #define TG3_PHY_ID_MASK 0xfffffff0 3270 #define TG3_PHY_ID_BCM5400 0x60008040 3271 #define TG3_PHY_ID_BCM5401 0x60008050 3272 #define TG3_PHY_ID_BCM5411 0x60008070 3273 #define TG3_PHY_ID_BCM5701 0x60008110 3274 #define TG3_PHY_ID_BCM5703 0x60008160 3275 #define TG3_PHY_ID_BCM5704 0x60008190 3276 #define TG3_PHY_ID_BCM5705 0x600081a0 3277 #define TG3_PHY_ID_BCM5750 0x60008180 3278 #define TG3_PHY_ID_BCM5752 0x60008100 3279 #define TG3_PHY_ID_BCM5714 0x60008340 3280 #define TG3_PHY_ID_BCM5780 0x60008350 3281 #define TG3_PHY_ID_BCM5755 0xbc050cc0 3282 #define TG3_PHY_ID_BCM5787 0xbc050ce0 3283 #define TG3_PHY_ID_BCM5756 0xbc050ed0 3284 #define TG3_PHY_ID_BCM5784 0xbc050fa0 3285 #define TG3_PHY_ID_BCM5761 0xbc050fd0 3286 #define TG3_PHY_ID_BCM5718C 0x5c0d8a00 3287 #define TG3_PHY_ID_BCM5718S 0xbc050ff0 3288 #define TG3_PHY_ID_BCM57765 0x5c0d8a40 3289 #define TG3_PHY_ID_BCM5719C 0x5c0d8a20 3290 #define TG3_PHY_ID_BCM5720C 0x5c0d8b60 3291 #define TG3_PHY_ID_BCM5762 0x85803780 3292 #define TG3_PHY_ID_BCM5906 0xdc00ac40 3293 #define TG3_PHY_ID_BCM8002 0x60010140 3294 #define TG3_PHY_ID_INVALID 0xffffffff 3295 3296 #define PHY_ID_RTL8211C 0x001cc910 3297 #define PHY_ID_RTL8201E 0x00008200 3298 3299 #define TG3_PHY_ID_REV_MASK 0x0000000f 3300 #define TG3_PHY_REV_BCM5401_B0 0x1 3301 3302 /* This macro assumes the passed PHY ID is 3303 * already masked with TG3_PHY_ID_MASK. 3304 */ 3305 #define TG3_KNOWN_PHY_ID(X) \ 3306 ((X) == TG3_PHY_ID_BCM5400 || (X) == TG3_PHY_ID_BCM5401 || \ 3307 (X) == TG3_PHY_ID_BCM5411 || (X) == TG3_PHY_ID_BCM5701 || \ 3308 (X) == TG3_PHY_ID_BCM5703 || (X) == TG3_PHY_ID_BCM5704 || \ 3309 (X) == TG3_PHY_ID_BCM5705 || (X) == TG3_PHY_ID_BCM5750 || \ 3310 (X) == TG3_PHY_ID_BCM5752 || (X) == TG3_PHY_ID_BCM5714 || \ 3311 (X) == TG3_PHY_ID_BCM5780 || (X) == TG3_PHY_ID_BCM5787 || \ 3312 (X) == TG3_PHY_ID_BCM5755 || (X) == TG3_PHY_ID_BCM5756 || \ 3313 (X) == TG3_PHY_ID_BCM5906 || (X) == TG3_PHY_ID_BCM5761 || \ 3314 (X) == TG3_PHY_ID_BCM5718C || (X) == TG3_PHY_ID_BCM5718S || \ 3315 (X) == TG3_PHY_ID_BCM57765 || (X) == TG3_PHY_ID_BCM5719C || \ 3316 (X) == TG3_PHY_ID_BCM5720C || (X) == TG3_PHY_ID_BCM5762 || \ 3317 (X) == TG3_PHY_ID_BCM8002) 3318 3319 u32 phy_flags; 3320 #define TG3_PHYFLG_IS_LOW_POWER 0x00000001 3321 #define TG3_PHYFLG_IS_CONNECTED 0x00000002 3322 #define TG3_PHYFLG_USE_MI_INTERRUPT 0x00000004 3323 #define TG3_PHYFLG_USER_CONFIGURED 0x00000008 3324 #define TG3_PHYFLG_PHY_SERDES 0x00000010 3325 #define TG3_PHYFLG_MII_SERDES 0x00000020 3326 #define TG3_PHYFLG_ANY_SERDES (TG3_PHYFLG_PHY_SERDES | \ 3327 TG3_PHYFLG_MII_SERDES) 3328 #define TG3_PHYFLG_IS_FET 0x00000040 3329 #define TG3_PHYFLG_10_100_ONLY 0x00000080 3330 #define TG3_PHYFLG_ENABLE_APD 0x00000100 3331 #define TG3_PHYFLG_CAPACITIVE_COUPLING 0x00000200 3332 #define TG3_PHYFLG_NO_ETH_WIRE_SPEED 0x00000400 3333 #define TG3_PHYFLG_JITTER_BUG 0x00000800 3334 #define TG3_PHYFLG_ADJUST_TRIM 0x00001000 3335 #define TG3_PHYFLG_ADC_BUG 0x00002000 3336 #define TG3_PHYFLG_5704_A0_BUG 0x00004000 3337 #define TG3_PHYFLG_BER_BUG 0x00008000 3338 #define TG3_PHYFLG_SERDES_PREEMPHASIS 0x00010000 3339 #define TG3_PHYFLG_PARALLEL_DETECT 0x00020000 3340 #define TG3_PHYFLG_EEE_CAP 0x00040000 3341 #define TG3_PHYFLG_1G_ON_VAUX_OK 0x00080000 3342 #define TG3_PHYFLG_KEEP_LINK_ON_PWRDN 0x00100000 3343 #define TG3_PHYFLG_MDIX_STATE 0x00200000 3344 #define TG3_PHYFLG_DISABLE_1G_HD_ADV 0x00400000 3345 3346 u32 led_ctrl; 3347 u32 phy_otp; 3348 u32 setlpicnt; 3349 u8 rss_ind_tbl[TG3_RSS_INDIR_TBL_SIZE]; 3350 3351 #define TG3_BPN_SIZE 24 3352 char board_part_number[TG3_BPN_SIZE]; 3353 #define TG3_VER_SIZE ETHTOOL_FWVERS_LEN 3354 char fw_ver[TG3_VER_SIZE]; 3355 u32 nic_sram_data_cfg; 3356 u32 pci_clock_ctrl; 3357 struct pci_dev *pdev_peer; 3358 3359 struct tg3_hw_stats *hw_stats; 3360 dma_addr_t stats_mapping; 3361 struct work_struct reset_task; 3362 3363 int nvram_lock_cnt; 3364 u32 nvram_size; 3365 #define TG3_NVRAM_SIZE_2KB 0x00000800 3366 #define TG3_NVRAM_SIZE_64KB 0x00010000 3367 #define TG3_NVRAM_SIZE_128KB 0x00020000 3368 #define TG3_NVRAM_SIZE_256KB 0x00040000 3369 #define TG3_NVRAM_SIZE_512KB 0x00080000 3370 #define TG3_NVRAM_SIZE_1MB 0x00100000 3371 #define TG3_NVRAM_SIZE_2MB 0x00200000 3372 3373 u32 nvram_pagesize; 3374 u32 nvram_jedecnum; 3375 3376 #define JEDEC_ATMEL 0x1f 3377 #define JEDEC_ST 0x20 3378 #define JEDEC_SAIFUN 0x4f 3379 #define JEDEC_SST 0xbf 3380 3381 #define ATMEL_AT24C02_CHIP_SIZE TG3_NVRAM_SIZE_2KB 3382 #define ATMEL_AT24C02_PAGE_SIZE (8) 3383 3384 #define ATMEL_AT24C64_CHIP_SIZE TG3_NVRAM_SIZE_64KB 3385 #define ATMEL_AT24C64_PAGE_SIZE (32) 3386 3387 #define ATMEL_AT24C512_CHIP_SIZE TG3_NVRAM_SIZE_512KB 3388 #define ATMEL_AT24C512_PAGE_SIZE (128) 3389 3390 #define ATMEL_AT45DB0X1B_PAGE_POS 9 3391 #define ATMEL_AT45DB0X1B_PAGE_SIZE 264 3392 3393 #define ATMEL_AT25F512_PAGE_SIZE 256 3394 3395 #define ST_M45PEX0_PAGE_SIZE 256 3396 3397 #define SAIFUN_SA25F0XX_PAGE_SIZE 256 3398 3399 #define SST_25VF0X0_PAGE_SIZE 4098 3400 3401 unsigned int irq_max; 3402 unsigned int irq_cnt; 3403 3404 struct ethtool_coalesce coal; 3405 struct ethtool_eee eee; 3406 3407 /* firmware info */ 3408 const char *fw_needed; 3409 const struct firmware *fw; 3410 u32 fw_len; /* includes BSS */ 3411 3412 struct device *hwmon_dev; 3413 bool link_up; 3414 bool pcierr_recovery; 3415 }; 3416 3417 /* Accessor macros for chip and asic attributes 3418 * 3419 * nb: Using static inlines equivalent to the accessor macros generates 3420 * larger object code with gcc 4.7. 3421 * Using statement expression macros to check tp with 3422 * typecheck(struct tg3 *, tp) also creates larger objects. 3423 */ 3424 #define tg3_chip_rev_id(tp) \ 3425 ((tp)->pci_chip_rev_id) 3426 #define tg3_asic_rev(tp) \ 3427 ((tp)->pci_chip_rev_id >> 12) 3428 #define tg3_chip_rev(tp) \ 3429 ((tp)->pci_chip_rev_id >> 8) 3430 3431 #endif /* !(_T3_H) */ 3432