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Searched refs:CP_HQD_PQ_CONTROL (Results 1 – 4 of 4) sorted by relevance

/drivers/gpu/drm/amd/amdgpu/
Dgfx_v8_0.c3874 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE, in gfx_v8_0_cp_compute_resume()
3876 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE, in gfx_v8_0_cp_compute_resume()
3879 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1); in gfx_v8_0_cp_compute_resume()
3881 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0); in gfx_v8_0_cp_compute_resume()
3882 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ROQ_PQ_IB_FLIP, 0); in gfx_v8_0_cp_compute_resume()
3883 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); in gfx_v8_0_cp_compute_resume()
3884 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1); in gfx_v8_0_cp_compute_resume()
/drivers/gpu/drm/radeon/
Dradeon_kfd.c499 write_register(kgd, CP_HQD_PQ_CONTROL, m->cp_hqd_pq_control); in kgd_hqd_load()
Dcikd.h1521 #define CP_HQD_PQ_CONTROL 0xC958 macro
Dcik.c5044 mqd->queue_state.cp_hqd_pq_control = RREG32(CP_HQD_PQ_CONTROL); in cik_cp_compute_resume()
5059 WREG32(CP_HQD_PQ_CONTROL, mqd->queue_state.cp_hqd_pq_control); in cik_cp_compute_resume()