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Searched refs:DC_HPD1_INT_CONTROL (Results 1 – 8 of 8) sorted by relevance

/drivers/gpu/drm/radeon/
Devergreen.c1764 tmp = RREG32(DC_HPD1_INT_CONTROL); in evergreen_hpd_set_polarity()
1769 WREG32(DC_HPD1_INT_CONTROL, tmp); in evergreen_hpd_set_polarity()
4585 tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY; in evergreen_disable_interrupt_state()
4586 WREG32(DC_HPD1_INT_CONTROL, tmp); in evergreen_disable_interrupt_state()
4623 hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~(DC_HPDx_INT_EN | DC_HPDx_RX_INT_EN); in evergreen_irq_set()
4806 WREG32(DC_HPD1_INT_CONTROL, hpd1); in evergreen_irq_set()
4902 tmp = RREG32(DC_HPD1_INT_CONTROL); in evergreen_irq_ack()
4904 WREG32(DC_HPD1_INT_CONTROL, tmp); in evergreen_irq_ack()
4933 tmp = RREG32(DC_HPD1_INT_CONTROL); in evergreen_irq_ack()
4935 WREG32(DC_HPD1_INT_CONTROL, tmp); in evergreen_irq_ack()
Dr600.c862 tmp = RREG32(DC_HPD1_INT_CONTROL); in r600_hpd_set_polarity()
867 WREG32(DC_HPD1_INT_CONTROL, tmp); in r600_hpd_set_polarity()
3586 tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY; in r600_disable_interrupt_state()
3587 WREG32(DC_HPD1_INT_CONTROL, tmp); in r600_disable_interrupt_state()
3738 hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~DC_HPDx_INT_EN; in r600_irq_set()
3834 WREG32(DC_HPD1_INT_CONTROL, hpd1); in r600_irq_set()
3905 tmp = RREG32(DC_HPD1_INT_CONTROL); in r600_irq_ack()
3907 WREG32(DC_HPD1_INT_CONTROL, tmp); in r600_irq_ack()
Dsi.c5979 tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY; in si_disable_interrupt_state()
5980 WREG32(DC_HPD1_INT_CONTROL, tmp); in si_disable_interrupt_state()
6091 hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~(DC_HPDx_INT_EN | DC_HPDx_RX_INT_EN); in si_irq_set()
6229 WREG32(DC_HPD1_INT_CONTROL, hpd1); in si_irq_set()
6313 tmp = RREG32(DC_HPD1_INT_CONTROL); in si_irq_ack()
6315 WREG32(DC_HPD1_INT_CONTROL, tmp); in si_irq_ack()
6344 tmp = RREG32(DC_HPD1_INT_CONTROL); in si_irq_ack()
6346 WREG32(DC_HPD1_INT_CONTROL, tmp); in si_irq_ack()
Dcik.c7327 tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY; in cik_disable_interrupt_state()
7328 WREG32(DC_HPD1_INT_CONTROL, tmp); in cik_disable_interrupt_state()
7458 hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~(DC_HPDx_INT_EN | DC_HPDx_RX_INT_EN); in cik_irq_set()
7612 WREG32(DC_HPD1_INT_CONTROL, hpd1); in cik_irq_set()
7713 tmp = RREG32(DC_HPD1_INT_CONTROL); in cik_irq_ack()
7715 WREG32(DC_HPD1_INT_CONTROL, tmp); in cik_irq_ack()
7743 tmp = RREG32(DC_HPD1_INT_CONTROL); in cik_irq_ack()
7745 WREG32(DC_HPD1_INT_CONTROL, tmp); in cik_irq_ack()
Dsid.h880 #define DC_HPD1_INT_CONTROL 0x6020 macro
Dcikd.h956 #define DC_HPD1_INT_CONTROL 0x6020 macro
Devergreend.h1346 #define DC_HPD1_INT_CONTROL 0x6020 macro
Dr600d.h856 #define DC_HPD1_INT_CONTROL 0x7d04 macro