Searched refs:DDR (Results 1 – 7 of 7) sorted by relevance
/drivers/gpio/ |
D | gpio-mb86s7x.c | 35 #define DDR(x) (0x10 + x / 8 * 4) macro 97 val = readl(gchip->base + DDR(gpio)); in mb86s70_gpio_direction_input() 99 writel(val, gchip->base + DDR(gpio)); in mb86s70_gpio_direction_input() 122 val = readl(gchip->base + DDR(gpio)); in mb86s70_gpio_direction_output() 124 writel(val, gchip->base + DDR(gpio)); in mb86s70_gpio_direction_output()
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/drivers/memory/ |
D | Kconfig | 19 bool "Atmel (Multi-port DDR-)SDRAM Controller" 24 DDR-SDRAM Controller available on Atmel AT91SAM9 and SAMA5 SoCs. 25 Starting with the at91sam9g45, this controller supports SDR, DDR and 26 LP-DDR memories. 42 select DDR
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/drivers/mtd/lpddr/ |
D | Kconfig | 9 flash chips. Synonymous with Mobile-DDR. It is a new standard for 10 DDR memories, intended for battery-operated systems.
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/drivers/pinctrl/ |
D | pinctrl-tegra30.c | 2207 …PINGROUP(vi_d1_pd5, DDR, SDMMC2, VI, RSVD4, 0x3128, N, … 2208 …PINGROUP(vi_vsync_pd6, DDR, RSVD2, VI, RSVD4, 0x315c, N, … 2209 …PINGROUP(vi_hsync_pd7, DDR, RSVD2, VI, RSVD4, 0x3160, N, … 2266 …PINGROUP(vi_d2_pl0, DDR, SDMMC2, VI, RSVD4, 0x312c, N, … 2267 …PINGROUP(vi_d3_pl1, DDR, SDMMC2, VI, RSVD4, 0x3130, N, … 2268 …PINGROUP(vi_d4_pl2, DDR, SDMMC2, VI, RSVD4, 0x3134, N, … 2269 …PINGROUP(vi_d5_pl3, DDR, SDMMC2, VI, RSVD4, 0x3138, N, … 2270 …PINGROUP(vi_d6_pl4, DDR, SDMMC2, VI, RSVD4, 0x313c, N, … 2271 …PINGROUP(vi_d7_pl5, DDR, SDMMC2, VI, RSVD4, 0x3140, N, … 2272 …PINGROUP(vi_d8_pl6, DDR, SDMMC2, VI, RSVD4, 0x3144, N, … [all …]
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/drivers/edac/ |
D | Kconfig | 380 tristate "Synopsys DDR Memory Controller" 383 Support for error detection and correction on the Synopsys DDR
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/drivers/mmc/host/ |
D | omap_hsmmc.c | 100 #define DDR (1 << 19) macro 687 con |= DDR; /* configure in DDR mode */ in omap_hsmmc_set_bus_width() 689 con &= ~DDR; in omap_hsmmc_set_bus_width()
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/drivers/hid/ |
D | Kconfig | 797 Note that DDR (Dance Dance Revolution) mode is not supported, nor
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