Searched refs:DPLL (Results 1 – 7 of 7) sorted by relevance
/drivers/gpu/drm/i915/ |
D | intel_dvo.c | 488 dpll[pipe] = I915_READ(DPLL(pipe)); in intel_dvo_init() 489 I915_WRITE(DPLL(pipe), dpll[pipe] | DPLL_DVO_2X_MODE); in intel_dvo_init() 496 I915_WRITE(DPLL(pipe), dpll[pipe]); in intel_dvo_init()
|
D | intel_runtime_pm.c | 877 u32 val = I915_READ(DPLL(pipe)); in vlv_display_power_well_init() 883 I915_WRITE(DPLL(pipe), val); in vlv_display_power_well_init() 1044 (I915_READ(DPLL(PIPE_B)) & DPLL_VCO_ENABLE) == 0) in assert_chv_phy_status() 1954 uint32_t status = I915_READ(DPLL(PIPE_A)); in chv_phy_control_init()
|
D | intel_display.c | 1164 val = I915_READ(DPLL(pipe)); in assert_pll() 1603 int reg = DPLL(crtc->pipe); in vlv_enable_pll() 1665 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll); in chv_enable_pll() 1668 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1)) in chv_enable_pll() 1692 int reg = DPLL(crtc->pipe); in i9xx_enable_pll() 1713 I915_WRITE(DPLL(!crtc->pipe), in i9xx_enable_pll() 1714 I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE); in i9xx_enable_pll() 1773 I915_WRITE(DPLL(PIPE_B), in i9xx_disable_pll() 1774 I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE); in i9xx_disable_pll() 1775 I915_WRITE(DPLL(PIPE_A), in i9xx_disable_pll() [all …]
|
D | intel_dsi.c | 484 tmp = I915_READ(DPLL(pipe)); in intel_dsi_pre_enable() 486 I915_WRITE(DPLL(pipe), tmp); in intel_dsi_pre_enable()
|
D | i915_reg.h | 2217 #define DPLL(pipe) _PIPE3((pipe), _DPLL_A, _DPLL_B, _CHV_DPLL_C) macro
|
D | intel_dp.c | 333 pll_enabled = I915_READ(DPLL(pipe)) & DPLL_VCO_ENABLE; in vlv_power_sequencer_kick()
|
/drivers/net/wireless/realtek/rtlwifi/rtl8192se/ |
D | reg.h | 281 #define DPLL 0x034A macro
|