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Searched refs:EDP_INTR_MASK1 (Results 1 – 1 of 1) sorted by relevance

/drivers/gpu/drm/msm/edp/
Dedp_ctrl.c57 #define EDP_INTR_MASK1 (EDP_INTR_STATUS1 << 2) macro
404 edp_write(ctrl->base + REG_EDP_INTERRUPT_REG_1, EDP_INTR_MASK1); in edp_ctrl_irq_enable()
1051 mask1 = isr1 & EDP_INTR_MASK1; in msm_edp_ctrl_irq()