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Searched refs:EDP_INTR_MASK2 (Results 1 – 1 of 1) sorted by relevance

/drivers/gpu/drm/msm/edp/
Dedp_ctrl.c62 #define EDP_INTR_MASK2 (EDP_INTR_STATUS2 << 2) macro
405 edp_write(ctrl->base + REG_EDP_INTERRUPT_REG_2, EDP_INTR_MASK2); in edp_ctrl_irq_enable()
1052 mask2 = isr2 & EDP_INTR_MASK2; in msm_edp_ctrl_irq()