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Searched refs:GENMASK (Results 1 – 25 of 109) sorted by relevance

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/drivers/net/wireless/mediatek/mt7601u/
Dregs.h20 #ifndef GENMASK
21 #define GENMASK(h, l) (((U32_C(1) << ((h) - (l) + 1)) - 1) << (l)) macro
34 #define MT_EFUSE_CTRL_AOUT GENMASK(5, 0)
35 #define MT_EFUSE_CTRL_MODE GENMASK(7, 6)
36 #define MT_EFUSE_CTRL_LDO_OFF_TIME GENMASK(13, 8)
37 #define MT_EFUSE_CTRL_LDO_ON_TIME GENMASK(15, 14)
38 #define MT_EFUSE_CTRL_AIN GENMASK(25, 16)
64 #define MT_WLAN_FUN_CTRL_GPIO_IN GENMASK(15, 8) /* MT76x0 */
65 #define MT_WLAN_FUN_CTRL_GPIO_OUT GENMASK(23, 16) /* MT76x0 */
66 #define MT_WLAN_FUN_CTRL_GPIO_OUT_EN GENMASK(31, 24) /* MT76x0 */
[all …]
Dmac.h73 #define MT_RXINFO_PN_LEN GENMASK(21, 19)
80 #define MT_RXWI_CTL_WCID GENMASK(7, 0)
81 #define MT_RXWI_CTL_KEY_IDX GENMASK(9, 8)
82 #define MT_RXWI_CTL_BSS_IDX GENMASK(12, 10)
83 #define MT_RXWI_CTL_UDF GENMASK(15, 13)
84 #define MT_RXWI_CTL_MPDU_LEN GENMASK(27, 16)
85 #define MT_RXWI_CTL_TID GENMASK(31, 28)
87 #define MT_RXWI_FRAG GENMASK(3, 0)
88 #define MT_RXWI_SN GENMASK(15, 4)
90 #define MT_RXWI_RATE_MCS GENMASK(6, 0)
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Ddma.h29 #define MT_TXD_INFO_LEN GENMASK(15, 0)
30 #define MT_TXD_INFO_D_PORT GENMASK(29, 27)
31 #define MT_TXD_INFO_TYPE GENMASK(31, 30)
55 #define MT_TXD_PKT_INFO_QSEL GENMASK(26, 25)
65 #define MT_TXD_CMD_INFO_SEQ GENMASK(19, 16)
66 #define MT_TXD_CMD_INFO_TYPE GENMASK(26, 20)
98 #define MT_RXD_INFO_LEN GENMASK(13, 0)
100 #define MT_RXD_INFO_QSEL GENMASK(26, 25)
101 #define MT_RXD_INFO_PORT GENMASK(29, 27)
102 #define MT_RXD_INFO_TYPE GENMASK(31, 30)
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Deeprom.h55 #define MT_EE_NIC_CONF_0_RX_PATH GENMASK(3, 0)
56 #define MT_EE_NIC_CONF_0_TX_PATH GENMASK(7, 4)
57 #define MT_EE_NIC_CONF_0_BOARD_TYPE GENMASK(13, 12)
65 #define MT_EE_NIC_CONF_2_RX_STREAM GENMASK(3, 0)
66 #define MT_EE_NIC_CONF_2_TX_STREAM GENMASK(7, 4)
68 #define MT_EE_NIC_CONF_2_XTAL_OPTION GENMASK(10, 9)
70 #define MT_EE_NIC_CONF_2_COEX_METHOD GENMASK(15, 13)
126 WARN_ON(reg & ~GENMASK(5, 0)); in s6_validate()
127 return reg & GENMASK(5, 0); in s6_validate()
/drivers/crypto/qce/
Dregs-v5.h115 #define CORE_STEP_REV_MASK GENMASK(15, 0)
117 #define CORE_MINOR_REV_MASK GENMASK(23, 16)
119 #define CORE_MAJOR_REV_MASK GENMASK(31, 24)
124 #define DOUT_SIZE_AVAIL_MASK GENMASK(30, 26)
126 #define DIN_SIZE_AVAIL_MASK GENMASK(25, 21)
135 #define CRYPTO_STATE_MASK GENMASK(13, 10)
153 #define REQ_SIZE_MASK GENMASK(20, 17)
172 #define MAX_QUEUED_REQ_MASK GENMASK(24, 16)
178 #define IRQ_ENABLES_MASK GENMASK(13, 10)
182 #define PIPE_SET_SELECT_MASK GENMASK(8, 5)
[all …]
/drivers/soc/mediatek/
Dmtk-scpsys.c83 .sram_pdn_bits = GENMASK(11, 8),
84 .sram_pdn_ack_bits = GENMASK(12, 12),
91 .sram_pdn_bits = GENMASK(11, 8),
92 .sram_pdn_ack_bits = GENMASK(15, 12),
99 .sram_pdn_bits = GENMASK(11, 8),
100 .sram_pdn_ack_bits = GENMASK(13, 12),
107 .sram_pdn_bits = GENMASK(11, 8),
108 .sram_pdn_ack_bits = GENMASK(12, 12),
117 .sram_pdn_bits = GENMASK(11, 8),
118 .sram_pdn_ack_bits = GENMASK(15, 12),
[all …]
/drivers/phy/
Dphy-qcom-ipq806x-sata.c32 #define __set(v, a, b) (((v) << (b)) & GENMASK(a, b))
36 #define SATA_PHY_P0_PARAM0_P0_TX_PREEMPH_GEN3_MASK GENMASK(17, 12)
38 #define SATA_PHY_P0_PARAM0_P0_TX_PREEMPH_GEN2_MASK GENMASK(11, 6)
40 #define SATA_PHY_P0_PARAM0_P0_TX_PREEMPH_GEN1_MASK GENMASK(5, 0)
45 #define SATA_PHY_P0_PARAM1_P0_TX_AMPLITUDE_GEN3_MASK GENMASK(20, 14)
47 #define SATA_PHY_P0_PARAM1_P0_TX_AMPLITUDE_GEN2_MASK GENMASK(13, 7)
49 #define SATA_PHY_P0_PARAM1_P0_TX_AMPLITUDE_GEN1_MASK GENMASK(6, 0)
53 #define SATA_PHY_P0_PARAM2_RX_EQ_MASK GENMASK(20, 18)
Dphy-mt65xx-usb3.c44 #define PA5_RG_U2_HSTX_SRCTRL GENMASK(14, 12)
69 #define P2C_RG_DATAIN GENMASK(13, 10)
73 #define P2C_RG_XCVRSEL GENMASK(5, 4)
93 #define P3A_RG_TX_EIDLE_CM GENMASK(31, 28)
97 #define P3A_RG_RX_DAC_MUX GENMASK(5, 1)
101 #define P3A_RG_XTAL_EXT_EN_U3 GENMASK(11, 10)
105 #define P3D_RG_CDR_BIR_LTD1 GENMASK(28, 24)
107 #define P3D_RG_CDR_BIR_LTD0 GENMASK(12, 8)
/drivers/crypto/marvell/
Dcesa.h19 #define CESA_TDMA_DST_BURST GENMASK(2, 0)
23 #define CESA_TDMA_SRC_BURST GENMASK(8, 6)
53 #define CESA_SA_CFG_STOP_DIG_ERR GENMASK(1, 0)
94 #define CESA_SA_DESC_CFG_OP_MSK GENMASK(1, 0)
101 #define CESA_SA_DESC_CFG_MACM_MSK GENMASK(6, 4)
105 #define CESA_SA_DESC_CFG_CRYPTM_MSK GENMASK(9, 8)
116 #define CESA_SA_DESC_CFG_AES_LEN_MSK GENMASK(25, 24)
121 #define CESA_SA_DESC_CFG_FRAG_MSK GENMASK(31, 30)
177 #define CESA_SA_DESC_MAC_DATA_MSK cpu_to_le32(GENMASK(15, 0))
180 #define CESA_SA_DESC_MAC_TOTAL_LEN_MSK cpu_to_le32(GENMASK(31, 16))
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/drivers/net/ethernet/apm/xgene/
Dxgene_enet_hw.h35 u32 mask = GENMASK(end, start); in xgene_set_bits()
43 return (val & GENMASK(end, start)) >> start; in xgene_get_bits()
66 #define CREATE_MASK(pos, len) GENMASK((pos)+(len)-1, (pos))
76 #define RING_OWNER_MASK GENMASK(9, 6)
77 #define RING_BUFNUM_MASK GENMASK(5, 0)
155 #define CFG_CLE_DSTQID0(val) (val & GENMASK(11, 0))
156 #define CFG_CLE_FPSEL0(val) ((val << 16) & GENMASK(19, 16))
235 #define DATALEN_MASK GENMASK(11, 0)
Dxgene_enet_sgmac.h24 #define PHY_ADDR(src) (((src)<<8) & GENMASK(12, 8))
25 #define REG_ADDR(src) ((src) & GENMASK(4, 0))
26 #define PHY_CONTROL(src) ((src) & GENMASK(15, 0))
Dxgene_enet_ring2.c117 ring_id_val = ring->id & GENMASK(9, 0); in xgene_enet_set_ring_id()
120 ring_id_buf = (ring->num << 9) & GENMASK(18, 9); in xgene_enet_set_ring_id()
177 data |= (count & GENMASK(16, 0)); in xgene_enet_wr_cmd()
/drivers/clk/
Dclk-fractional-divider.c75 GENMASK(fd->mwidth - 1, 0), GENMASK(fd->nwidth - 1, 0), in clk_fd_round_rate()
93 GENMASK(fd->mwidth - 1, 0), GENMASK(fd->nwidth - 1, 0), in clk_fd_set_rate()
143 fd->mmask = GENMASK(mwidth - 1, 0) << mshift; in clk_register_fractional_divider()
146 fd->nmask = GENMASK(nwidth - 1, 0) << nshift; in clk_register_fractional_divider()
/drivers/iio/adc/
Dberlin2-adc.c30 #define BERLIN2_SM_CTRL_ADC_SEL_MASK GENMASK(8, 5)
36 #define BERLIN2_SM_CTRL_ADC_CLKSEL_MASK GENMASK(11, 10)
53 #define BERLIN2_SM_ADC_MASK GENMASK(9, 0)
56 #define BERLIN2_SM_ADC_STATUS_DATA_RDY_MASK GENMASK(15, 0)
58 #define BERLIN2_SM_ADC_STATUS_INT_EN_MASK GENMASK(31, 16)
63 #define BERLIN2_SM_TSEN_MASK GENMASK(9, 0)
70 #define BERLIN2_SM_TSEN_CTRL_TRIM_MASK GENMASK(25, 22)
/drivers/mmc/host/
Dmmci_qcom_dml.c24 #define PRODUCER_CRCI_MSK GENMASK(1, 0)
28 #define CONSUMER_CRCI_MSK GENMASK(3, 2)
44 #define PRODUCER_PIPE_ID_MSK GENMASK(4, 0)
46 #define CONSUMER_PIPE_ID_MSK GENMASK(20, 16)
/drivers/nvmem/
Dvf610-ocotp.c43 #define OCOTP_CTRL_WR_UNLOCK_MASK GENMASK(31, 16)
45 #define OCOTP_CTRL_ADDR_MASK GENMASK(6, 0)
51 #define OCOTP_TIMING_STROBE_READ_MASK GENMASK(21, 16)
53 #define OCOTP_TIMING_RELAX_MASK GENMASK(15, 12)
55 #define OCOTP_TIMING_STROBE_PROG_MASK GENMASK(11, 0)
/drivers/clk/ingenic/
Dcgu.c97 m = (ctl >> pll_info->m_shift) & GENMASK(pll_info->m_bits - 1, 0); in ingenic_pll_recalc_rate()
99 n = (ctl >> pll_info->n_shift) & GENMASK(pll_info->n_bits - 1, 0); in ingenic_pll_recalc_rate()
102 od_enc &= GENMASK(pll_info->od_bits - 1, 0); in ingenic_pll_recalc_rate()
195 ctl &= ~(GENMASK(pll_info->m_bits - 1, 0) << pll_info->m_shift); in ingenic_pll_set_rate()
198 ctl &= ~(GENMASK(pll_info->n_bits - 1, 0) << pll_info->n_shift); in ingenic_pll_set_rate()
201 ctl &= ~(GENMASK(pll_info->od_bits - 1, 0) << pll_info->od_shift); in ingenic_pll_set_rate()
248 GENMASK(clk_info->mux.bits - 1, 0); in ingenic_clk_get_parent()
294 mask = GENMASK(clk_info->mux.bits - 1, 0); in ingenic_clk_set_parent()
326 GENMASK(clk_info->div.bits - 1, 0); in ingenic_clk_recalc_rate()
396 mask = GENMASK(clk_info->div.bits - 1, 0); in ingenic_clk_set_rate()
/drivers/net/ethernet/stmicro/stmmac/
Ddwmac-sti.c77 #define STIH4XX_RETIME_SRC_MASK GENMASK(8, 6)
99 #define STID127_RETIME_SRC_MASK GENMASK(7, 6)
103 #define ENMII_MASK GENMASK(5, 5)
105 #define EN_MASK GENMASK(1, 1)
115 #define MII_PHY_SEL_MASK GENMASK(4, 2)
/drivers/tty/serial/
Dstm32-usart.c58 #define USART_DR_MASK GENMASK(8, 0)
61 #define USART_BRR_DIV_F_MASK GENMASK(3, 0)
62 #define USART_BRR_DIV_M_MASK GENMASK(15, 4)
81 #define USART_CR1_IE_MASK GENMASK(8, 4)
84 #define USART_CR2_ADD_MASK GENMASK(3, 0)
92 #define USART_CR2_STOP_MASK GENMASK(13, 12)
110 #define USART_GTPR_PSC_MASK GENMASK(7, 0)
111 #define USART_GTPR_GT_MASK GENMASK(15, 8)
/drivers/mtd/nand/
Dsunxi_nand.c74 #define NFC_CE_SEL_MSK GENMASK(26, 24)
77 #define NFC_PAGE_SHIFT_MSK GENMASK(11, 8)
110 #define NFC_CMD_LOW_BYTE_MSK GENMASK(7, 0)
111 #define NFC_CMD_HIGH_BYTE_MSK GENMASK(15, 8)
113 #define NFC_ADR_NUM_MSK GENMASK(18, 16)
126 #define NFC_CMD_TYPE_MSK GENMASK(31, 30)
132 #define NFC_READ_CMD_MSK GENMASK(7, 0)
133 #define NFC_RND_READ_CMD0_MSK GENMASK(15, 8)
134 #define NFC_RND_READ_CMD1_MSK GENMASK(23, 16)
137 #define NFC_PROGRAM_CMD_MSK GENMASK(7, 0)
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/drivers/clk/sunxi/
Dclk-a10-pll2.c30 #define SUN4I_PLL2_PRE_DIV_MASK GENMASK(SUN4I_PLL2_PRE_DIV_WIDTH - 1, 0)
34 #define SUN4I_PLL2_N_MASK GENMASK(SUN4I_PLL2_N_WIDTH - 1, 0)
38 #define SUN4I_PLL2_POST_DIV_MASK GENMASK(SUN4I_PLL2_POST_DIV_WIDTH - 1, 0)
/drivers/clk/qcom/
Dclk-regmap-mux.c30 unsigned int mask = GENMASK(mux->width - 1, 0); in mux_get_parent()
45 unsigned int mask = GENMASK(mux->width + mux->shift - 1, mux->shift); in mux_set_parent()
/drivers/iio/accel/
Dmma9553.c34 #define MMA9553_MASK_CONF_WORD GENMASK(15, 0)
40 #define MMA9553_MASK_CONF_STEPLEN GENMASK(7, 0)
43 #define MMA9553_MASK_CONF_HEIGHT GENMASK(15, 8)
44 #define MMA9553_MASK_CONF_WEIGHT GENMASK(7, 0)
47 #define MMA9553_MASK_CONF_FILTSTEP GENMASK(15, 8)
49 #define MMA9553_MASK_CONF_FILTTIME GENMASK(6, 0)
52 #define MMA9553_MASK_CONF_SPDPRD GENMASK(15, 8)
53 #define MMA9553_MASK_CONF_STEPCOALESCE GENMASK(7, 0)
56 #define MMA9553_MAX_ACTTHD GENMASK(15, 0)
65 #define MMA9553_MASK_STATUS_ACTIVITY GENMASK(10, 8)
[all …]
/drivers/net/fjes/
Dfjes_regs.h122 REG_ICTL_MASK_ALL = GENMASK(20, 16),
127 REG_IS_MASK_EPID = GENMASK(15, 0),
/drivers/tee/optee/
Doptee_msg.h59 #define OPTEE_MSG_ATTR_TYPE_MASK GENMASK(7, 0)
105 #define OPTEE_MSG_ATTR_CACHE_MASK GENMASK(2, 0)

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