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Searched refs:HCR (Results 1 – 5 of 5) sorted by relevance

/drivers/net/irda/
Dw83977af_ir.c340 outb(HCR_EN_IRQ, iobase+HCR); in w83977af_probe()
348 outb(HCR_SIR, iobase+HCR); in w83977af_probe()
447 outb(ir_mode, iobase+HCR); in w83977af_change_speed()
563 outb(inb(iobase+HCR) & ~HCR_EN_DMA, iobase+HCR); in w83977af_dma_write()
574 outb(inb(iobase+HCR) | HCR_EN_DMA | HCR_TX_WT, iobase+HCR); in w83977af_dma_write()
641 outb(inb(iobase+HCR) & ~HCR_EN_DMA, iobase+HCR); in w83977af_dma_xmit_complete()
695 outb(inb(iobase+HCR) & ~HCR_EN_DMA, iobase+HCR); in w83977af_dma_receive()
729 hcr = inb(iobase+HCR); in w83977af_dma_receive()
730 outb(hcr | HCR_EN_DMA, iobase+HCR); in w83977af_dma_receive()
734 outb(inb(iobase+HCR) | HCR_EN_DMA, iobase+HCR); in w83977af_dma_receive()
Dw83977af_ir.h81 #define HCR 0x04 macro
/drivers/gpu/drm/rcar-du/
Drcar_du_regs.h271 #define HCR 0x00050 macro
Drcar_du_crtc.c162 rcar_du_crtc_write(rcrtc, HCR, mode->htotal - 1); in rcar_du_crtc_set_display_timing()
/drivers/tty/
Dsynclink.c348 #define HCR 0x12 /* Hardware Configuration Register */ macro
5013 usc_OutReg( info, HCR, RegValue ); in usc_set_sdlc_mode()
5240 usc_OutReg( info, HCR, (u16)((usc_InReg( info, HCR ) & ~BIT1) | BIT0) ); in usc_enable_loopback()
5303 usc_OutReg( info, HCR, (u16)((usc_InReg( info, HCR ) & ~BIT1) | BIT0) ); in usc_enable_aux_clock()
5309 usc_OutReg( info, HCR, (u16)(usc_InReg( info, HCR ) & ~BIT0) ); in usc_enable_aux_clock()
6328 usc_OutReg( info, HCR, in usc_enable_async_clock()
6329 (u16)((usc_InReg( info, HCR ) & ~BIT1) | BIT0) ); in usc_enable_async_clock()
6338 usc_OutReg( info, HCR, (u16)(usc_InReg( info, HCR ) & ~BIT0) ); in usc_enable_async_clock()