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Searched refs:HDMI0_ACR_32_0 (Results 1 – 3 of 3) sorted by relevance

/drivers/gpu/drm/radeon/
Ddce3_1_afmt.c180 WREG32_P(HDMI0_ACR_32_0 + offset, in dce3_2_hdmi_update_acr()
Dr600_hdmi.c192 WREG32_P(HDMI0_ACR_32_0 + offset, in r600_hdmi_update_acr()
Dr600d.h1142 #define HDMI0_ACR_32_0 0x74ac macro