1 /* 2 * Hardware specific macros, defines and structures 3 * 4 * This software may be used and distributed according to the terms 5 * of the GNU General Public License, incorporated herein by reference. 6 * 7 */ 8 9 #ifndef HARDWARE_H 10 #define HARDWARE_H 11 12 #include <asm/param.h> /* For HZ */ 13 14 /* 15 * General hardware parameters common to all ISA adapters 16 */ 17 18 #define MAX_CARDS 4 /* The maximum number of cards to 19 control or probe for. */ 20 21 #define SIGNATURE 0x87654321 /* Board reset signature */ 22 #define SIG_OFFSET 0x1004 /* Where to find signature in shared RAM */ 23 #define TRACE_OFFSET 0x1008 /* Trace enable word offset in shared RAM */ 24 #define BUFFER_OFFSET 0x1800 /* Beginning of buffers */ 25 26 /* I/O Port parameters */ 27 #define IOBASE_MIN 0x180 /* Lowest I/O port address */ 28 #define IOBASE_MAX 0x3C0 /* Highest I/O port address */ 29 #define IOBASE_OFFSET 0x20 /* Inter-board I/O port gap used during 30 probing */ 31 #define FIFORD_OFFSET 0x0 32 #define FIFOWR_OFFSET 0x400 33 #define FIFOSTAT_OFFSET 0x1000 34 #define RESET_OFFSET 0x2800 35 #define PG0_OFFSET 0x3000 /* Offset from I/O Base for Page 0 register */ 36 #define PG1_OFFSET 0x3400 /* Offset from I/O Base for Page 1 register */ 37 #define PG2_OFFSET 0x3800 /* Offset from I/O Base for Page 2 register */ 38 #define PG3_OFFSET 0x3C00 /* Offset from I/O Base for Page 3 register */ 39 40 #define FIFO_READ 0 /* FIFO Read register */ 41 #define FIFO_WRITE 1 /* FIFO Write rgister */ 42 #define LO_ADDR_PTR 2 /* Extended RAM Low Addr Pointer */ 43 #define HI_ADDR_PTR 3 /* Extended RAM High Addr Pointer */ 44 #define NOT_USED_1 4 45 #define FIFO_STATUS 5 /* FIFO Status Register */ 46 #define NOT_USED_2 6 47 #define MEM_OFFSET 7 48 #define SFT_RESET 10 /* Reset Register */ 49 #define EXP_BASE 11 /* Shared RAM Base address */ 50 #define EXP_PAGE0 12 /* Shared RAM Page0 register */ 51 #define EXP_PAGE1 13 /* Shared RAM Page1 register */ 52 #define EXP_PAGE2 14 /* Shared RAM Page2 register */ 53 #define EXP_PAGE3 15 /* Shared RAM Page3 register */ 54 #define IRQ_SELECT 16 /* IRQ selection register */ 55 #define MAX_IO_REGS 17 /* Total number of I/O ports */ 56 57 /* FIFO register values */ 58 #define RF_HAS_DATA 0x01 /* fifo has data */ 59 #define RF_QUART_FULL 0x02 /* fifo quarter full */ 60 #define RF_HALF_FULL 0x04 /* fifo half full */ 61 #define RF_NOT_FULL 0x08 /* fifo not full */ 62 #define WF_HAS_DATA 0x10 /* fifo has data */ 63 #define WF_QUART_FULL 0x20 /* fifo quarter full */ 64 #define WF_HALF_FULL 0x40 /* fifo half full */ 65 #define WF_NOT_FULL 0x80 /* fifo not full */ 66 67 /* Shared RAM parameters */ 68 #define SRAM_MIN 0xC0000 /* Lowest host shared RAM address */ 69 #define SRAM_MAX 0xEFFFF /* Highest host shared RAM address */ 70 #define SRAM_PAGESIZE 0x4000 /* Size of one RAM page (16K) */ 71 72 /* Shared RAM buffer parameters */ 73 #define BUFFER_SIZE 0x800 /* The size of a buffer in bytes */ 74 #define BUFFER_BASE BUFFER_OFFSET /* Offset from start of shared RAM 75 where buffer start */ 76 #define BUFFERS_MAX 16 /* Maximum number of send/receive 77 buffers per channel */ 78 #define HDLC_PROTO 0x01 /* Frame Format for Layer 2 */ 79 80 #define BRI_BOARD 0 81 #define POTS_BOARD 1 82 #define PRI_BOARD 2 83 84 /* 85 * Specific hardware parameters for the DataCommute/BRI 86 */ 87 #define BRI_CHANNELS 2 /* Number of B channels */ 88 #define BRI_BASEPG_VAL 0x98 89 #define BRI_MAGIC 0x60000 /* Magic Number */ 90 #define BRI_MEMSIZE 0x10000 /* Amount of RAM (64K) */ 91 #define BRI_PARTNO "72-029" 92 #define BRI_FEATURES ISDN_FEATURE_L2_HDLC | ISDN_FEATURE_L3_TRANS; 93 /* 94 * Specific hardware parameters for the DataCommute/PRI 95 */ 96 #define PRI_CHANNELS 23 /* Number of B channels */ 97 #define PRI_BASEPG_VAL 0x88 98 #define PRI_MAGIC 0x20000 /* Magic Number */ 99 #define PRI_MEMSIZE 0x100000 /* Amount of RAM (1M) */ 100 #define PRI_PARTNO "72-030" 101 #define PRI_FEATURES ISDN_FEATURE_L2_HDLC | ISDN_FEATURE_L3_TRANS; 102 103 /* 104 * Some handy macros 105 */ 106 107 /* Determine if a channel number is valid for the adapter */ 108 #define IS_VALID_CHANNEL(y, x) ((x > 0) && (x <= sc_adapter[y]->channels)) 109 110 #endif 111