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Searched refs:LANE_PLL_MASK (Results 1 – 2 of 2) sorted by relevance

/drivers/gpu/drm/gma500/
Dcdv_intel_display.c347 lane_value &= ~(LANE_PLL_MASK); in cdv_dpll_set_clock_cdv()
353 lane_value &= ~(LANE_PLL_MASK); in cdv_dpll_set_clock_cdv()
359 lane_value &= ~(LANE_PLL_MASK); in cdv_dpll_set_clock_cdv()
365 lane_value &= ~(LANE_PLL_MASK); in cdv_dpll_set_clock_cdv()
Dpsb_intel_reg.h1380 #define LANE_PLL_MASK (0x7 << 20) macro