Home
last modified time | relevance | path

Searched refs:LANE_PLL_PIPE (Results 1 – 2 of 2) sorted by relevance

/drivers/gpu/drm/gma500/
Dcdv_intel_display.c348 lane_value |= LANE_PLL_ENABLE | LANE_PLL_PIPE(pipe); in cdv_dpll_set_clock_cdv()
354 lane_value |= LANE_PLL_ENABLE | LANE_PLL_PIPE(pipe); in cdv_dpll_set_clock_cdv()
360 lane_value |= LANE_PLL_ENABLE | LANE_PLL_PIPE(pipe); in cdv_dpll_set_clock_cdv()
366 lane_value |= LANE_PLL_ENABLE | LANE_PLL_PIPE(pipe); in cdv_dpll_set_clock_cdv()
Dpsb_intel_reg.h1382 #define LANE_PLL_PIPE(p) (((p) == 0) ? (1 << 21) : (0 << 21)) macro