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Searched refs:LVDS_PORT_EN (Results 1 – 11 of 11) sorted by relevance

/drivers/gpu/drm/i915/
Dintel_lvds.c85 if (!(tmp & LVDS_PORT_EN)) in intel_lvds_get_hw_state()
151 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP; in intel_pre_enable_lvds()
223 I915_WRITE(lvds_encoder->reg, I915_READ(lvds_encoder->reg) | LVDS_PORT_EN); in intel_enable_lvds()
252 I915_WRITE(lvds_encoder->reg, I915_READ(lvds_encoder->reg) & ~LVDS_PORT_EN); in intel_disable_lvds()
991 if ((lvds & LVDS_PORT_EN) == 0) { in intel_lvds_init()
1152 if (crtc && (lvds & LVDS_PORT_EN)) { in intel_lvds_init()
Di915_suspend.c73 mask = ~LVDS_PORT_EN; in i915_restore_display()
Di915_reg.h3433 #define LVDS_PORT_EN (1 << 31) macro
Dintel_display.c1520 if ((val & LVDS_PORT_EN) == 0) in lvds_pipe_enabled()
10622 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN); in i9xx_crtc_clock_get()
/drivers/gpu/drm/gma500/
Dpsb_intel_display.c241 lvds |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP; in psb_intel_crtc_mode_set()
327 is_lvds = (pipe == 1) && (REG_READ(LVDS) & LVDS_PORT_EN); in psb_intel_crtc_clock_get()
338 LVDS_PORT_EN); in psb_intel_crtc_clock_get()
Dcdv_intel_display.c754 LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP | in cdv_intel_crtc_mode_set()
870 is_lvds = (pipe == 1) && (REG_READ(LVDS) & LVDS_PORT_EN); in cdv_intel_crtc_clock_get()
880 (dev_priv->regs.psb.saveLVDS & LVDS_PORT_EN); in cdv_intel_crtc_clock_get()
Doaktrail_lvds.c114 LVDS_PORT_EN | in oaktrail_lvds_mode_set()
Dcdv_intel_lvds.c748 if (crtc && (lvds & LVDS_PORT_EN)) { in cdv_intel_lvds_init()
Dpsb_intel_reg.h453 #define LVDS_PORT_EN (1 << 31) macro
Dpsb_intel_lvds.c813 if (crtc && (lvds & LVDS_PORT_EN)) { in psb_intel_lvds_init()
Dgma_display.c741 (REG_READ(LVDS) & LVDS_PORT_EN) != 0) { in gma_find_best_pll()