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Searched refs:MC_SEQ_MISC_TIMING (Results 1 – 10 of 10) sorted by relevance

/drivers/gpu/drm/radeon/
Dbtcd.h106 #define MC_SEQ_MISC_TIMING 0x28a8 macro
Dbtc_dpm.c1866 case MC_SEQ_MISC_TIMING >> 2: in btc_check_s0_mc_reg_index()
2032 WREG32(MC_SEQ_MISC_TIMING_LP, RREG32(MC_SEQ_MISC_TIMING)); in btc_initialize_mc_reg_table()
Dnid.h782 #define MC_SEQ_MISC_TIMING 0x28a8 macro
Dsid.h543 #define MC_SEQ_MISC_TIMING 0x28a8 macro
Dcikd.h658 #define MC_SEQ_MISC_TIMING 0x28a8 macro
Devergreend.h288 #define MC_SEQ_MISC_TIMING 0x28a8 macro
Dci_dpm.c4403 case MC_SEQ_MISC_TIMING >> 2: in ci_check_s0_mc_reg_index()
4570 case MC_SEQ_MISC_TIMING: in ci_register_patching_mc_seq()
4617 WREG32(MC_SEQ_MISC_TIMING_LP, RREG32(MC_SEQ_MISC_TIMING)); in ci_initialize_mc_reg_table()
Dni_dpm.c2779 case MC_SEQ_MISC_TIMING >> 2: in ni_check_s0_mc_reg_index()
2885 WREG32(MC_SEQ_MISC_TIMING_LP, RREG32(MC_SEQ_MISC_TIMING)); in ni_initialize_mc_reg_table()
Dcypress_dpm.c980 eg_pi->mc_reg_table.mc_reg_address[i].s1 = MC_SEQ_MISC_TIMING >> 2; in cypress_set_mc_reg_address_table()
Dsi_dpm.c5487 case MC_SEQ_MISC_TIMING >> 2: in si_check_s0_mc_reg_index()
5597 WREG32(MC_SEQ_MISC_TIMING_LP, RREG32(MC_SEQ_MISC_TIMING)); in si_initialize_mc_reg_table()