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Searched refs:MC_SEQ_MISC_TIMING_LP (Results 1 – 10 of 10) sorted by relevance

/drivers/gpu/drm/radeon/
Dbtcd.h149 #define MC_SEQ_MISC_TIMING_LP 0x2a74 macro
Dbtc_dpm.c1867 *out_reg = MC_SEQ_MISC_TIMING_LP >> 2; in btc_check_s0_mc_reg_index()
2032 WREG32(MC_SEQ_MISC_TIMING_LP, RREG32(MC_SEQ_MISC_TIMING)); in btc_initialize_mc_reg_table()
Dnid.h807 #define MC_SEQ_MISC_TIMING_LP 0x2a74 macro
Dsid.h575 #define MC_SEQ_MISC_TIMING_LP 0x2a74 macro
Dcikd.h702 #define MC_SEQ_MISC_TIMING_LP 0x2a74 macro
Devergreend.h325 #define MC_SEQ_MISC_TIMING_LP 0x2a74 macro
Dni_dpm.c2780 *out_reg = MC_SEQ_MISC_TIMING_LP >> 2; in ni_check_s0_mc_reg_index()
2885 WREG32(MC_SEQ_MISC_TIMING_LP, RREG32(MC_SEQ_MISC_TIMING)); in ni_initialize_mc_reg_table()
Dcypress_dpm.c979 eg_pi->mc_reg_table.mc_reg_address[i].s0 = MC_SEQ_MISC_TIMING_LP >> 2; in cypress_set_mc_reg_address_table()
Dsi_dpm.c5488 *out_reg = MC_SEQ_MISC_TIMING_LP >> 2; in si_check_s0_mc_reg_index()
5597 WREG32(MC_SEQ_MISC_TIMING_LP, RREG32(MC_SEQ_MISC_TIMING)); in si_initialize_mc_reg_table()
Dci_dpm.c4404 *out_reg = MC_SEQ_MISC_TIMING_LP >> 2; in ci_check_s0_mc_reg_index()
4617 WREG32(MC_SEQ_MISC_TIMING_LP, RREG32(MC_SEQ_MISC_TIMING)); in ci_initialize_mc_reg_table()