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Searched refs:MTK_PIN_DRV_GRP (Results 1 – 4 of 4) sorted by relevance

/drivers/pinctrl/mediatek/
Dpinctrl-mt8127.c37 MTK_PIN_DRV_GRP(0, 0xb00, 0, 1),
38 MTK_PIN_DRV_GRP(1, 0xb00, 0, 1),
39 MTK_PIN_DRV_GRP(2, 0xb00, 0, 1),
40 MTK_PIN_DRV_GRP(3, 0xb00, 0, 1),
41 MTK_PIN_DRV_GRP(4, 0xb00, 0, 1),
42 MTK_PIN_DRV_GRP(5, 0xb00, 0, 1),
43 MTK_PIN_DRV_GRP(6, 0xb00, 0, 1),
44 MTK_PIN_DRV_GRP(7, 0xb00, 12, 1),
45 MTK_PIN_DRV_GRP(8, 0xb00, 12, 1),
46 MTK_PIN_DRV_GRP(9, 0xb00, 12, 1),
[all …]
Dpinctrl-mt8173.c207 MTK_PIN_DRV_GRP(0, DRV_BASE+0x20, 12, 0),
208 MTK_PIN_DRV_GRP(1, DRV_BASE+0x20, 12, 0),
209 MTK_PIN_DRV_GRP(2, DRV_BASE+0x20, 12, 0),
210 MTK_PIN_DRV_GRP(3, DRV_BASE+0x20, 12, 0),
211 MTK_PIN_DRV_GRP(4, DRV_BASE+0x20, 12, 0),
212 MTK_PIN_DRV_GRP(5, DRV_BASE+0x30, 0, 0),
213 MTK_PIN_DRV_GRP(6, DRV_BASE+0x30, 0, 0),
214 MTK_PIN_DRV_GRP(7, DRV_BASE+0x30, 0, 0),
215 MTK_PIN_DRV_GRP(8, DRV_BASE+0x30, 0, 0),
216 MTK_PIN_DRV_GRP(9, DRV_BASE+0x30, 0, 0),
[all …]
Dpinctrl-mt8135.c68 MTK_PIN_DRV_GRP(0, DRV_BASE1, 0, 0),
69 MTK_PIN_DRV_GRP(1, DRV_BASE1, 0, 0),
70 MTK_PIN_DRV_GRP(2, DRV_BASE1, 0, 0),
71 MTK_PIN_DRV_GRP(3, DRV_BASE1, 0, 0),
72 MTK_PIN_DRV_GRP(4, DRV_BASE1, 4, 0),
73 MTK_PIN_DRV_GRP(5, DRV_BASE1, 8, 0),
74 MTK_PIN_DRV_GRP(6, DRV_BASE1, 0, 0),
75 MTK_PIN_DRV_GRP(7, DRV_BASE1, 0, 0),
76 MTK_PIN_DRV_GRP(8, DRV_BASE1, 0, 0),
77 MTK_PIN_DRV_GRP(9, DRV_BASE1, 0, 0),
[all …]
Dpinctrl-mtk-common.h115 #define MTK_PIN_DRV_GRP(_pin, _offset, _bit, _grp) \ macro