Searched refs:NCR5380_read (Results 1 – 15 of 15) sorted by relevance
534 if ((bl = NCR5380_read(C400_BLOCK_COUNTER_REG)) == 0) { in NCR5380_pread()537 if (NCR5380_read(C400_CONTROL_STATUS_REG) & CSR_GATED_53C80_IRQ) { in NCR5380_pread()541 while (NCR5380_read(C400_CONTROL_STATUS_REG) & CSR_HOST_BUF_NOT_RDY) in NCR5380_pread()550 dst[start + i] = NCR5380_read(C400_HOST_BUFFER); in NCR5380_pread()561 while (NCR5380_read(C400_CONTROL_STATUS_REG) & CSR_HOST_BUF_NOT_RDY) in NCR5380_pread()570 dst[start + i] = NCR5380_read(C400_HOST_BUFFER); in NCR5380_pread()580 if (!(NCR5380_read(C400_CONTROL_STATUS_REG) & CSR_GATED_53C80_IRQ)) in NCR5380_pread()588 while (NCR5380_read(C400_CONTROL_STATUS_REG) & CSR_53C80_REG) in NCR5380_pread()591 if (!(NCR5380_read(BUS_AND_STATUS_REG) & BASR_END_DMA_TRANSFER)) in NCR5380_pread()595 NCR5380_read(RESET_PARITY_INTERRUPT_REG); in NCR5380_pread()[all …]
325 r = NCR5380_read(reg); in NCR5380_poll_politely()334 r = NCR5380_read(reg); in NCR5380_poll_politely()413 data = NCR5380_read(CURRENT_SCSI_DATA_REG); in NCR5380_print()414 status = NCR5380_read(STATUS_REG); in NCR5380_print()415 mr = NCR5380_read(MODE_REG); in NCR5380_print()416 icr = NCR5380_read(INITIATOR_COMMAND_REG); in NCR5380_print()417 basr = NCR5380_read(BUS_AND_STATUS_REG); in NCR5380_print()455 status = NCR5380_read(STATUS_REG); in NCR5380_print_phase()864 for (pass = 1; (NCR5380_read(STATUS_REG) & SR_BSY) && pass <= 6; ++pass) { in NCR5380_init()1118 basr = NCR5380_read(BUS_AND_STATUS_REG); in NCR5380_intr()[all …]
517 data = NCR5380_read(CURRENT_SCSI_DATA_REG); in NCR5380_print()518 status = NCR5380_read(STATUS_REG); in NCR5380_print()519 mr = NCR5380_read(MODE_REG); in NCR5380_print()520 icr = NCR5380_read(INITIATOR_COMMAND_REG); in NCR5380_print()521 basr = NCR5380_read(BUS_AND_STATUS_REG); in NCR5380_print()565 status = NCR5380_read(STATUS_REG); in NCR5380_print_phase()1124 if ((NCR5380_read(BUS_AND_STATUS_REG) & in NCR5380_dma_complete()1127 saved_data = NCR5380_read(INPUT_DATA_REG); in NCR5380_dma_complete()1135 HOSTNO, NCR5380_read(BUS_AND_STATUS_REG), in NCR5380_dma_complete()1136 NCR5380_read(STATUS_REG)); in NCR5380_dma_complete()[all …]
38 #define NCR5380_read(reg) macscsi_read(_instance, reg) macro144 PHASE_SR_TO_TCR( NCR5380_read(STATUS_REG) )); in mac_scsi_reset_boot()152 NCR5380_read( RESET_PARITY_INTERRUPT_REG ); in mac_scsi_reset_boot()246 while (!(NCR5380_read(BUS_AND_STATUS_REG) & BASR_DRQ) && in macscsi_pread()247 !(NCR5380_read(STATUS_REG) & SR_REQ)) in macscsi_pread()250 if (!(NCR5380_read(BUS_AND_STATUS_REG) & BASR_DRQ) && in macscsi_pread()251 (NCR5380_read(BUS_AND_STATUS_REG) & BASR_PHASE_MATCH)) { in macscsi_pread()340 while (!(NCR5380_read(BUS_AND_STATUS_REG) & BASR_DRQ) && in macscsi_pwrite()341 (!(NCR5380_read(STATUS_REG) & SR_REQ) || in macscsi_pwrite()342 (NCR5380_read(BUS_AND_STATUS_REG) & BASR_PHASE_MATCH))) in macscsi_pwrite()[all …]
338 NCR5380_read(RESET_PARITY_INTERRUPT_REG); in NCR5380_pread()348 while (NCR5380_read(DTC_CONTROL_REG) & CSR_HOST_BUF_NOT_RDY) in NCR5380_pread()359 while (!(NCR5380_read(DTC_CONTROL_REG) & D_CR_ACCESS)) in NCR5380_pread()363 NCR5380_read(RESET_PARITY_INTERRUPT_REG); in NCR5380_pread()389 NCR5380_read(RESET_PARITY_INTERRUPT_REG); in NCR5380_pwrite()400 while (NCR5380_read(DTC_CONTROL_REG) & CSR_HOST_BUF_NOT_RDY) in NCR5380_pwrite()408 while (!(NCR5380_read(DTC_CONTROL_REG) & D_CR_ACCESS)) in NCR5380_pwrite()412 while (!(NCR5380_read(TARGET_COMMAND_REG) & TCR_LAST_BYTE_SENT)) in NCR5380_pwrite()
96 #define NCR5380_read(reg) readb(T128_address(reg)) macro99 #define NCR5380_read(reg) \ macro
48 #define NCR5380_read(reg) (readb(DTC_address(reg))) macro51 #define NCR5380_read(reg) (readb(DTC_address(reg))) macro
124 #define NCR5380_read(reg) ( inb(PAS16_io_port(reg)) ) macro127 #define NCR5380_read(reg) \ macro
52 #define NCR5380_read(reg) (inb(NCR5380_map_name + (reg))) macro77 #define NCR5380_read(reg) readb(iomem + NCR53C400_mem_base + (reg)) macro
208 NCR5380_read( RESET_PARITY_INTERRUPT_REG ); in init_board()285 if( NCR5380_read( MODE_REG ) != 0x20 ) /* Write to a reg. */ in pas16_hw_detect()288 if( NCR5380_read( MODE_REG ) != 0x00 ) in pas16_hw_detect()
50 #define NCR5380_read(reg) sun3scsi_read(reg) macro164 PHASE_SR_TO_TCR( NCR5380_read(STATUS_REG) )); in sun3_scsi_reset_boot()174 NCR5380_read( RESET_PARITY_INTERRUPT_REG ); in sun3_scsi_reset_boot()
96 #define NCR5380_read(reg) atari_scsi_reg_read(reg) macro533 PHASE_SR_TO_TCR(NCR5380_read(STATUS_REG))); in atari_scsi_reset_boot()541 NCR5380_read(RESET_PARITY_INTERRUPT_REG); in atari_scsi_reset_boot()
39 #define NCR5380_read(reg) inb(port + reg) macro
26 #define NCR5380_read(reg) readb(_base + ((reg) << 2)) macro
25 #define NCR5380_read(reg) cumanascsi_read(_instance, reg) macro