| /drivers/scsi/ |
| D | NCR5380.c | 592 NCR5380_write(TARGET_COMMAND_REG, 0); in NCR5380_probe_irq()
593 NCR5380_write(SELECT_ENABLE_REG, hostdata->id_mask); in NCR5380_probe_irq()
594 NCR5380_write(OUTPUT_DATA_REG, hostdata->id_mask); in NCR5380_probe_irq()
595 NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE | ICR_ASSERT_DATA | ICR_ASSERT_SEL); in NCR5380_probe_irq()
600 NCR5380_write(SELECT_ENABLE_REG, 0); in NCR5380_probe_irq()
601 NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE); in NCR5380_probe_irq()
841 NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE); in NCR5380_init()
842 NCR5380_write(MODE_REG, MR_BASE); in NCR5380_init()
843 NCR5380_write(TARGET_COMMAND_REG, 0); in NCR5380_init()
844 NCR5380_write(SELECT_ENABLE_REG, 0); in NCR5380_init()
[all …]
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| D | atari_NCR5380.c | 795 NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE); in NCR5380_init()
796 NCR5380_write(MODE_REG, MR_BASE); in NCR5380_init()
797 NCR5380_write(TARGET_COMMAND_REG, 0); in NCR5380_init()
798 NCR5380_write(SELECT_ENABLE_REG, 0); in NCR5380_init()
1157 NCR5380_write(MODE_REG, MR_BASE); in NCR5380_dma_complete()
1158 NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE); in NCR5380_dma_complete()
1331 NCR5380_write(TARGET_COMMAND_REG, 0); in NCR5380_select()
1337 NCR5380_write(OUTPUT_DATA_REG, hostdata->id_mask); in NCR5380_select()
1338 NCR5380_write(MODE_REG, MR_ARBITRATE); in NCR5380_select()
1352 NCR5380_write(MODE_REG, MR_BASE); in NCR5380_select()
[all …]
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| D | dtc.c | 245 NCR5380_write(DTC_CONTROL_REG, CSR_5380_INTR); /* Enable int's */ in dtc_detect()
339 NCR5380_write(MODE_REG, MR_ENABLE_EOP_INTR | MR_DMA_MODE); in NCR5380_pread()
341 NCR5380_write(DTC_CONTROL_REG, CSR_DIR_READ); in NCR5380_pread()
343 NCR5380_write(DTC_CONTROL_REG, CSR_DIR_READ | CSR_INT_BASE); in NCR5380_pread()
344 NCR5380_write(DTC_BLK_CNT, len >> 7); /* Block count */ in NCR5380_pread()
361 NCR5380_write(MODE_REG, 0); /* Clear the operating mode */ in NCR5380_pread()
390 NCR5380_write(MODE_REG, MR_ENABLE_EOP_INTR | MR_DMA_MODE); in NCR5380_pwrite()
393 NCR5380_write(DTC_CONTROL_REG, 0); in NCR5380_pwrite()
395 NCR5380_write(DTC_CONTROL_REG, CSR_5380_INTR); in NCR5380_pwrite()
396 NCR5380_write(DTC_BLK_CNT, len >> 7); /* Block count */ in NCR5380_pwrite()
[all …]
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| D | g_NCR5380.c | 531 NCR5380_write(C400_CONTROL_STATUS_REG, CSR_BASE | CSR_TRANS_DIR); in NCR5380_pread()
532 NCR5380_write(C400_BLOCK_COUNTER_REG, blocks); in NCR5380_pread()
594 NCR5380_write(MODE_REG, MR_BASE); in NCR5380_pread()
619 NCR5380_write(C400_CONTROL_STATUS_REG, CSR_BASE); in NCR5380_pwrite()
620 NCR5380_write(C400_BLOCK_COUNTER_REG, blocks); in NCR5380_pwrite()
635 NCR5380_write(C400_HOST_BUFFER, src[start + i]); in NCR5380_pwrite()
651 NCR5380_write(C400_HOST_BUFFER, src[start + i]); in NCR5380_pwrite()
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| D | mac_scsi.c | 39 #define NCR5380_write(reg, value) macscsi_write(_instance, reg, value) macro
143 NCR5380_write( TARGET_COMMAND_REG, in mac_scsi_reset_boot()
147 NCR5380_write( INITIATOR_COMMAND_REG, ICR_BASE | ICR_ASSERT_RST ); in mac_scsi_reset_boot()
151 NCR5380_write( INITIATOR_COMMAND_REG, ICR_BASE ); in mac_scsi_reset_boot()
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| D | t128.h | 97 #define NCR5380_write(reg, value) writeb((value),(T128_address(reg))) macro
103 #define NCR5380_write(reg, value) { \ macro
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| D | dtc.h | 49 #define NCR5380_write(reg, value) (writeb(value, DTC_address(reg))) macro
56 #define NCR5380_write(reg, value) do { \ macro
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| D | pas16.h | 125 #define NCR5380_write(reg, value) ( outb((value),PAS16_io_port(reg)) ) macro
131 #define NCR5380_write(reg, value) \ macro
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| D | g_NCR5380.h | 53 #define NCR5380_write(reg, value) (outb((value), (NCR5380_map_name + (reg)))) macro
78 #define NCR5380_write(reg, value) writeb(value, iomem + NCR53C400_mem_base + (reg)) macro
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| D | sun3_scsi.c | 51 #define NCR5380_write(reg, value) sun3scsi_write(reg, value) macro
163 NCR5380_write( TARGET_COMMAND_REG, in sun3_scsi_reset_boot()
167 NCR5380_write( INITIATOR_COMMAND_REG, ICR_BASE | ICR_ASSERT_RST ); in sun3_scsi_reset_boot()
173 NCR5380_write( INITIATOR_COMMAND_REG, ICR_BASE ); in sun3_scsi_reset_boot()
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| D | atari_scsi.c | 97 #define NCR5380_write(reg, value) atari_scsi_reg_write(reg, value) macro
532 NCR5380_write(TARGET_COMMAND_REG, in atari_scsi_reset_boot()
536 NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE | ICR_ASSERT_RST); in atari_scsi_reset_boot()
540 NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE); in atari_scsi_reset_boot()
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| D | pas16.c | 284 NCR5380_write( MODE_REG, 0x20 ); /* Is it really SCSI? */ in pas16_hw_detect()
287 NCR5380_write( MODE_REG, 0x00 ); /* it back. */ in pas16_hw_detect()
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| D | dmx3191d.c | 40 #define NCR5380_write(reg, value) outb(value, port + reg) macro
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| /drivers/scsi/arm/ |
| D | oak.c | 27 #define NCR5380_write(reg, value) writeb(value, _base + ((reg) << 2)) macro
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| D | cumana_1.c | 26 #define NCR5380_write(reg, value) cumanascsi_write(_instance, reg, value) macro
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